2011 LINKS 2011 Edition 2011 Executive Summary 2011 ORTC Tables Tables in this file

Table DESN1 Table DESN2a Table DESN2b Table DESN3 Table DESN4 Table DESN5 Table DESN6 Table DESN7 Table DESN8 Table DESN9 Table DESN10 Table DESN11 Table DESN12 Table DESN13 Table DESN14 Table DESN15

Link to all 2011 ITRS Files Includes the Overall Technology Roadmap Characteristics (ORTC) section Tables of Key Roadmap Drivers

Overall Design Technology Challenges Near-term System-Level Design Technology Requirements Long-term System-Level Design Technology Requirements Correspondence between System-Level Design Requirements and Solutions Logical/Circuit/Physical Design Technology Requirements Correspondence between Logical/Circuit/Physical Requirements and Solutions Design Verification Technology Requirements Verification Strategy Planning Correspondence between Design Verification Requirements and Solutions Design for Test Technology Requirements Design for Manufacturability Technology Requirements Correspondence between Design for Manufacturability Requirements and Solutions Required Simulation Models for AMSRF Design Design Technology Improvements and Impact on Designer Productivity Low-Power Design Technology Improvements and Impact on Dynamic and Static Power Three Phases of Design Product Maturity and Design Challenges in 3DIC

Table DESN1 Overall Design Technology Challenges

Challenges 22nm Design productivity Summary of Issues System-level: high level of abstraction (HW/SW) functionality spec, platform based design, multiprocessor programmability, system integration, AMS co-design and automation Verification: executable specification, ESL formal verification, intelligent test bench, coveragebased verification Logic/circuit/physical: analog circuit synthesis, multi-objective optimization Logic/circuit/physical: SiP and 3D (TSV-based) planning and implementation flows Heterogeneous component integration (optical, mechanical, chemical, bio, etc.) Power consumption Manufacturability Logic/circuit/physical: dynamic and static, system- and circuit-level power optimization Performance/power variability, device parameter variability, lithography limitations impact on design, mask cost, quality of (process) models ATE interface test (multi-Gb/s), mixed-signal test, delay BIST, test-volume-reducing DFT Logic/circuit/physical: signal integrity analysis, EMI analysis, thermal analysis Logic/circuit/physical: MTTF-aware design, BISR, soft-error correction Summary of Issues Verification: complete formal verification of designs, complete verification code reuse, complete deployment of functional coverage Tools specific for SOI and non-static logic, and emerging devices Cost-driven design flow Power consumption Logic/circuit/physical: SOI power management Logic/circuit/physical : Reliability and resilience- and temperature-constrained 3D physical implementation flows Uncontrollable threshold voltage variability Advanced analog/mixed signal DFT (digital, structural, radio), statistical and yieldimprovement DFT Thermal BIST, system-level BIST Interference Reliability and resilience EMIelectromagnetic interference insulator Interactions between heterogeneous components (optical, mechanical, chemical, bio, etc.) Autonomic computing, robust design, SW reliability and resilience ESLElectronic System-Level HW/SWhardware/software MTTFmean time to failure SOIsilicon on

Interference Reliability and resilience Challenges <22nm Design productivity

Manufacturability

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN2a Near-term System-Level Design Requirements

Year of Production MPU/ASIC Metal 1 (M1) Pitch (nm) Design Reuse Design block reuse [1] % to all logic size Platform Based Design Available platforms [2] Normalized to 100% in the start year [3] Platforms supported [4] % of platforms fully supported by tools [5] High Level Synthesis Accuracy of high level estimates (performance, area, power, costs) [6] % versus measurements Reconfigurability SOC reconfigurability [7] % of SOC functionality reconfigurable Analog/Mixed Signal Analog automation [8] % versus digital automation [9] Modeling methodology, description languages, and simulation environments [10] % versus digital methodology [11] [12] Embedded Software HW productivity increase SW productivity increase Hardware productivity Software productivity ESL behavioral level -- % impact on total power reduction ESL architectural level -- % impact on total power reduction ESL RT level -- % impact on total power reduction ESL circuit level -- % impact on total power reduction ESL physical level -- % impact on total power reduction Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 2011 38.0 2012 32.0 2013 27.0 2014 24.0 2015 21.0 2016 18.9 2017 16.9 2018 15.0

41%

42%

44%

46%

48%

49%

51%

52%

60% 57%

55% 64%

52% 75%

48% 80%

45% 85%

43% 90%

40% 92%

37% 94%

73%

76%

80%

83%

86%

90%

92%

94%

38%

40%

42%

45%

48%

50%

53%

56%

27% 67%

30% 70%

32% 73%

35% 76%

38% 78%

40% 80%

43% 83%

46% 86%

0.0% 300.0% 275.0% 800.0% 30% 20% 20% 20% 10%

37.5% 0.0% 378.1% 800.0% 30% 20% 20% 20% 10%

200% 100% 1134% 1600% 40% 30% 10% 10% 10% 1134% 1600% 40% 30% 10% 10% 10%

100% 0% 2268% 1600% 50% 30% 10% 5% 5% 2268% 1600% 50% 30% 10% 5% 5%

100% 100% 4536% 3200% 50% 30% 10% 5% 5% 4536% 3200% 50% 30% 10% 5% 5%

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN2b Long-term System-Level Design Requirements

Year of Production MPU/ASIC Metal 1 (M1) Pitch (nm) Design Reuse Design block reuse [1] % to all logic size Platform Based Design Available platforms [2] Normalized to 100% in the start year [3] Platforms supported [4] % of platforms fully supported by tools [5] High Level Synthesis Accuracy of high level estimates (performance, area, power, costs) [6] % versus measurements Reconfigurability SOC reconfigurability [7] % of SOC functionality reconfigurable Analog/Mixed Signal Analog automation [8] % versus digital automation [9] Modeling methodology, description languages, and simulation environments [10] % versus digital methodology [11] [12] Embedded Software HW productivity increase SW productivity increase Hardware productivity Software productivity ESL behavioral level -- % impact on total power reduction ESL architectural level -- % impact on total power reduction ESL RT level -- % impact on total power reduction ESL circuit level -- % impact on total power reduction ESL physical level -- % impact on total power reduction Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 2019 13.4 2020 11.9 2021 10.6 2022 9.5 2023 8.4 2024 7.5 2025 6.7 2026 6.0

54%

55%

57%

58%

59%

60%

59%

60%

35% 95%

32% 97%

29% 99%

27% 100%

26% 100%

25% 100%

25% 100%

25% 100%

95%

97%

99%

100%

100%

100%

100%

100%

60%

62%

65%

68%

69%

70%

70%

70%

50% 90%

52% 92%

55% 95%

58% 98%

59% 99%

60% 100%

60% 100%

60% 100%

0% 200% 4536% 9600% 50% 30% 10% 5% 5%

4536% 9600% 50% 30% 10% 5% 5%

200% 200% 13608% 19200% 50% 30% 10% 5% 5%

13608% 19200% 50% 30% 10% 5% 5%

60% 38% 21773% 26400% 50% 30% 10% 5% 5%

21773% 26400% 50% 30% 10% 5% 5%

200% 200% 65319% 79200% 50% 30% 10% 5% 5%

65319% 79200% 50% 30% 10% 5% 5%

The International Technology Roadmap for Semiconductors, 2011 Edition

Notes for Table DESN2a and 2b

[1] This requirement is not unique to system-level design, but is also a requirement for design in general (see the SoC Consumer Design Productivity Trends in the System Drivers chapter ). Definition : The portion of a design which is not newly developed but which is composed of pre-existing components. Rationale : Reuse is one of the main factors which drive design productivity, and is one of the key concepts behind system-level design.

The reuse in year n from a particular reference year can be calculated as reuse(n) = 1 - (1 reuse) ( (1 + pgrowth)^n / ( 1 + cgrowth )^n ) where reuse = reuse in reference year; pgrowth = (expected) mean annual productivity growth rate, excluding the effect of reuse; and cgrowth= (expected) mean annual growth rate of design complexity. The calculation further assumes that the size of the design staff as well as the design cycle time stay constant over the given period of time. The rationale for the formula is that the gap between the productivity growth (without effect of reuse) and the complexity growth must be filled by reuse if the silicon process technology is to be fully exploited in SoC design. [2] Definition : A platform is a specific combination of system components that supports a specific application area (e.g. wireless, automotive, consumer electronics/multimedia, Small Office Home Office (SOHO) networks, etc.). System components comprise one or more processors, (real time) operating system, communication infrastructure, memory, customizable analog and digital logic, and virtual sockets for new logic. Basic functionality for the application area is provided by a number of already integrated components. System differentiation is achieved by integration of few new components either in hardware or software. Rationale : Platform based design is an important driver for design productivity, since it highly promotes reuse. In addition, system-level specifications require platforms to which they can be mapped. [3] Different platforms are expected to converge in the future, owing to advances in manufacturing technology and higher integration densities; hence, the total number of platforms is expected to decrease. [4] Definition : (Full) Support for a particular platform means an integrated development environment that supports and automates architectural exploration, HW/SW partitioning, architectural/platform mapping, HW/SW co-verification, performance/area/power/cost tradeoffs, HW and SW synthesis, and HW/SW interface synthesis for that platform. Rationale: A high degree of automation is a key to the success of system-level design. [5] Although there already exist some solutions today for some aspects of platform-based modeling, full integration has not yet been achieved.

[6] Definition : The degree to which the estimated results match measurements taken on the fabricated IC. Rationale : For high-level synthesis techniques a high accuracy of estimations is essential to delivery of high-quality synthesis results that meet user constraints, such as minimum performance, maximum area, etc.

[7] Definition : The portion of an SoC or of a design, in terms of functionality, that is implemented in SW or HW that is reconfigurable. Rationale : Growing system complexity will make it impossible to ship designs without errors in the future. Hence, it is essential to be able to fix errors after fabrication. In addition, reconfigurability increases reuse, since existing devices can be reprogrammed to fulfill new tasks. [8] Definition : Degree of automation in analog design. Rationale : Analog components are to be found in most electronic systems today and analog/mixed-signal design is an essential and important part of electronic design. Hence, as for digital design, a high degree of automation in analog design across as many levels as possible is required in the future, if design productivity growth is to be maintained or increased. [9] The degree to which the degree of automation in analog design matches the degree of automation in digital design.

[10] Definition : The degree to which analog methodology, description languages, and simulation environments match the maturity of their digital counterparts. Rationale : As digital and analog design become nearly equally important at a system level, analog design and modeling methodologies must reach a similar maturity as their digital counterparts in order to be able to support required productivity growth in system-level design.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN3 Correspondence Between System-Level Design Requirements and Solutions

Requirement Design block reuse Solution System-level component reuse On-chip network design methods Multi-fabric implementation planning (AMS, RF, MEMS, ) Automated interface synthesis Automated HW-SW co-design and verification Accuracy of high level estimates Improved system-level power estimation techniques Chip-package co-design methods SOC reconfigurability On-chip network design methods Multi-fabric implementation planning (AMS, RF, MEMS, ) Mixed-Signal/RF verification Explanation of the Correspondence The larger and more complex the components that can be reused, the greater the expected overall design reuse Standardized communication structures and interfaces support reuse: IPs with standardized interfaces can be easily integrated and exchanged, and communication structures reused Enables integration of different fabrics on same die or in same package (SiP); hence, enables reduced number of platforms Automated interface synthesis is one building block to an integrated synthesis flow for whole platforms. Required for integrated, platform-based system development System-level power estimation needs to match progress in high-level area and performance estimation Packaging effects, e.g., on timing, must be accounted for in higher-level estimations To provide flexible, reconfigurable communication structures Multi-fabric implementation planning for AMS and RF components are a building block to analog automation As in digital design, verification is an increasingly critical and timeconsuming activity in the design flow Due to thermal and power limitations further performance increases have to be realized with multi-core systems. SW simulation, formal verification and automated testbenches for SW will reduce the verification effort for embedded software and enhance quality.

Available platforms

Platforms supported

Analog automation Modeling methodology, description languages, simulation environments HW offers multi-core systems that have to be exploited by SW Reduce SW verification effort

Parallel Processing

Intelligent Testbench

Productivity increase required for SW since SW cost >> 50% of total system cost Increase SW execution performance

Concurrent Software Infrastructure set of tools that allow concurrent software development and debug A Parallel processing using different application-specific processors for each of Heterogeneous Parallel Processing the separate functions in the system A concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing. It functions as an alternative to lock-based synchronization

SW Productivity increase required

Transactional Memory

Productivity increase required for HW/SW codesign

True system-level design including electronic hardware and software, System Design Automation (SDA) mechanical, bio, opto, chemical and fluids domains Specifications written in a formal language allow automated verification process starting early in the design process and at high abstraction levels without the need to code several new verification models. This enables an integrated design flow from the specification to completed system and that can be completely validated at each step.

Reduce verification effort

Executable Specification

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN4 Logical/Circuit/Physical Design Technology Requirements

Year of Production Asynchronous global signaling: % of a design driven by handshake clocking Parameter uncertainty:%-effect (on signoff delay) Simultaneous analysis objectives: # of objectives during optimization Circuit families: # of families in a single design Synthesized analog content: % of total design analog content Full-chip leakage (normalized to full-chip leakage power dissipation in 2011) % native 3D design technology in 3D implementation flow

2011 19% 11% 6 4 19% 1.00 25

2012 20% 12% 6 4 20% 1.09 33

2013 22% 14% 6 4 23% 1.27 40

2014 23% 15% 7 4 25% 1.45 48

2015 25% 18% 7 4 28% 2.18 55

2016 30% 20% 8 4 30% 2.91 60

2017 30% 20% 8 4 35% 2.91 65

2018 30% 20% 8 4 40% 2.91 70

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN4 Logical/Circuit/Physical Design Technology Requirements

Year of Production Asynchronous global signaling: % of a design driven by handshake clocking Parameter uncertainty:%-effect (on signoff delay) Simultaneous analysis objectives: # of objectives during optimization Circuit families: # of families in a single design Synthesized analog content: % of total design analog content Full-chip leakage (normalized to full-chip leakage power dissipation in 2011) % native 3D design technology in 3D implementation flow Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Manufacturable solutions are NOT known

2019 35% 22% 8 4 45% 2.91 75

2020 40% 25% 8 4 50% 2.91 80

2021 43% 26% 8 4 55% 2.91 85

2022 45% 28% 8 4 60% 2.91 90

2023 47% 30% 8 4 62% 2.91 95

2024 49% 32% 8 4 64% 2.91 100

2025 52% 35% 8 4 66% 2.91 100

2026 54% 38% 8 4 67% 2.91 100

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN5 Correspondence Between Logical/Circuit/Physical Requirements and Solutions

Requirement Asynchronous global signaling % of a design (SOC) Parameter uncertainty %-effect (on signoff delay) Simultaneous analysis objectives Simultaneous analysis objectives

Solution Automated handshake logic/circuit tools Synthesis and timing analysis accounting for variability Circuit/layout enhancement accounting for variability Power management analysis and logic insertion SOI SOC tools

Explanation of the Correspondence Departure from fully synchronous design paradigm needed for power reduction, latency insensitivity, variation-tolerance Tools that account for process uncertainty, and resulting parametric uncertainty, will reduce guardbanding and increase chip yields Optimizations which consider parametric uncertainty Requires budgeting of area/power/timing constraints

Simultaneous analysis objectives

Cost-driven implementation flow

Cost is an engineering parameter that affects turnaround times. Silicon cost no longer dominant; test and manufacturing costs increase emphasis on adaptive, self-repairing circuits Non-static implementations help improving different chip parameters Allows for larger portions of a chip to be analog Enables accurate leakage predictions Enables correct choice of 2D vs. 3D, and 3D granularity Required for co-optimization of reliability and manufacturability along with performance and power

Circuit families # of circuit families in a single design Synthesized analog content Full-chip leakage % Native 3D design tech in flow % Native 3D design tech in flow

Non-static logic implementation Analog synthesis (circuit/layout) Macro block/chip leakage analysis 3D design space exploration tools Native 3D power/thermal analyses, optimizations

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN6 Design Verification Requirements

2011 Productivity Design size verifiable by 1 engineer-year (in millions of transistors based on an SOC design and a 10-person engineering team) [1] Methodology Design errors exposed using formal or semi-formal verification (%, versus simulation) Effort spent on system-level verification: software, hardware and electrical effects (%) Portion of the design specification formalized for verifiability (%) Bugs Escape rate: bugs found after first tapeout (per each 100K lines of design code) Bugs found after system integration until tapeout (per each 100K lines of design code) Reuse Portion of the verification infrastructure (e.g., test beds, coverage, checkers) which is newly developed (versus reused components and acquired IP) (%) [2] Portion of the verification infrastructure which is acquired from third parties (i.e., verification IP) (%) [2] Functional coverage Portion of design for which verification quality is evaluated through functional coverage (%) Coverage goal density (expressed as number of coverage goals for each million transistors of the design) [3]

2012

2013

2014

2015

2016

2017

2018

14.7

18.9

24.4

31.4

40.4

52.0

67.0

86.2

14.1 17.8 16.3

16.5 19.4 17.5

18.8 20.9 18.8

21.2 22.5 20.0

23.5 24.1 21.3

25.9 25.6 22.5

28.2 27.2 23.8

30.6 28.8 25.0

37 346

35 320

32 295

29 269

27 243

24 218

22 192

19 166

61.6

59

56

53

49

46

43

40.2

26.6

29.4

32.1

34.9

37.6

40

43

46

56 2549

58 2863

60 3176

63 3490

65 3804

67 4118

69 4431

72 4745

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN6 Design Verification Requirements

2019 Productivity Design size verifiable by 1 engineer-year (in millions of transistors based on an SOC design and a 10-person engineering team) [1] Methodology Design errors exposed using formal or semi-formal verification (%, versus simulation) Effort spent on system-level verification: software, hardware and electrical effects (%) Portion of the design specification formalized for verifiability (%) Bugs Escape rate: bugs found after first tapeout (per each 100K lines of design code) Bugs found after system integration until tapeout (per each 100K lines of design code) Reuse Portion of the verification infrastructure (e.g., test beds, coverage, checkers) which is newly developed (versus reused components and acquired IP) (%) [2] Portion of the verification infrastructure which is acquired from third parties (i.e., verification IP) (%) [2] Functional coverage Portion of design for which verification quality is evaluated through functional coverage (%) Coverage goal density (expressed as number of coverage goals for each million transistors of the design) [3]

2020

2021

2022

2023

2024

2025

2026

111.1

143.0

184.2

237.3

305.7

393.8

410.3

522.7

32.9 30.3 26.3

35.3 31.9 27.5

37.6 33.4 28.8

40 35 30.0

43 37 31.3

45 38 32.5

48 40 33.8

51 42 35.0

17 141

14 115

12 89

9 64

6 38

4 13

2 8

2 6

37.2

34.1

31.1

28

25

23

20

18

48.7

51.5

54.2

57

60

63

66

70

74 5059

76 5373

78 5686

81 6000

83 6331

85 6681

87 7050

90 7439

The International Technology Roadmap for Semiconductors, 2011 Edition

Notes for Table DESN6

All values, except for the first row (productivity) are linearly increasing or decreasing trends, where the initial values in 2007 are derived from industry survey data, and the final values are estimated. [1] The productivity requirement is derived from the SoC design productivity requirement of the System Drivers chapter, and divides it by the percentage of design effort spent on verification, so as to obtain the amount of logic that can be verified in a year. The percentage of the design effort spent on verification has a linear trend starting at 70% in 2007 and ending at 50% in 2022. [2] Verification reuse is modeled as: new verification infrastructure + reused + 3rd party verification IP = 100%. The table provides values for the new verification infrastructures and acquired 3rd party IP; these two values determine the proportion of reused verification components. [3] In other words, the number of assertions or checkers inserted in a design or referring to an aspect of the design, for each corresponding million of transistors of logic generated when synthesizing that design.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN7 Verification Planning

Verification Planning 1. Verification stratgey is decided adhoc, based on experiences, skills, and risk aversion of verification engineers 2. There is an increasing shift towards assertions which enable use of formal verification techniques 3. Virtual Prototyping is increasingly being used for system verification facilitating accelerated software development The strategy depends on individual experience and skill, there is no criteria and no systematic flow to make it. It is difficult to keep design quality because dependency of verification engineers skill and no criteria make it the variation of the design qualify. Standardizing internally because verification methodology is unified to UVM from OVM/VMM. 1.Make criteria of verification strategy for QCD. Long Term Solution 2.Promoting a platform based design development and bringing up the verification methodology with UVM as the mainstream, make designs of the same quality at high level.

Current Practice(2011)

Problem Statement Difficulties Short Term Solution

Bring up skilled expert human resource for verification 1.Few engineers who can develop UVM verification environment. Current Status(2011) 2.Many engineers can use assertion for dynamic simulation ,but formal verification is too difficult for most engineers. 3.Train a verification engineer locally not methodically. 1.Need new skills for new verification methodology like formal verification. Problem Statement 2.Not so many engineers can handle many kinds of verification methodology. Difficulties Short Term Solution Long Term Solution Few skilled persons in verification cause extending TAT and declining in design quality. Implementing a human resources program for verification such as promoting a guideline of IP verification. Need a system for developing verification engineers which has not only how they learn what kind of skills but also how much their skills are.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN8 Correspondence Between Design Verification Requirements and Solutions

Requirement

Solution Verification methodology centered on verification IPs and reuse Hierarchical hardware verification Reusable methodologies for functional coverage development

Explanation of the Correspondence Verification IPs and reuse reduce the amount of new verification development required in a project Structured methodologies improve design team productivity Functional coverage is time-consuming, and specific for each distinct design; development of reusability techniques is critical to boosting productivity

Productivity of verification tasks

Advancing the verification of hardware in parallel with that of software components can Concurrent verification of hardware and significantly shorten time-to-market of a product, in contrast to methodologies that begin software components during development software verification only after the first hardware prototype Hierarchical hardware verification methodology Enables the decomposition of the system into smaller blocks which are suitable for formal verification Design for verifiability organizes a design so as to simplify verification; additional verification-specific hardware structures further simplify design-time verification tasks Verification IP components enable an early start on system-level verification

Formal and semi-formal verification centered methodology Design development and structure taking into account verifiability Verification methodology centered on verification IPs and reuse Methodologies for system-level verification Integrated verification of hardware and embedded software and their interface

Directly provides solutions for effective system-level verification

Portion of design specification formalized for Design specification formalized for verifiability verifiability Escape rate after tapeout Design structure taking into account verifiability Analog and mixed-signal verification Simulation and verification solutions for the detection and correction of soft failures and manufacturing faults Hierarchical verification methodology Functional coverage Reusable methodologies for functional coverage development

Formal languages and methodologies to support the formal specification of a design Development of hardware structures (checker-like) which can be used to detect and correct a system entering an escaped erroneous configuration after customer shipment Limits the bug rate due to analog effects Manufacturing faults occurring in post-silicon are detected at system-level integration; techniques to detect and correct electrical and transient defects reduce the effort required to expose and correct these problems. Supports management of complexity through decomposition Reusable functional coverage solutions leverage the coverage development effort and boost quality of results

System integration bug rate

Incremental verification

Tools and techniques for determination of Such tools and techniques will allow for elimination of redundancy from re-verification redundancy in verification efforts Concrete decision making criteria, A clear decision making process within the framework of a common platform with common platform, specialized training for uniformity in skill level of engineers will facilitate successful execution of verification verification discipline strategy

Verification strategy planning

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN9 Design for Test Technology Requirements

Year of Production System Driver: Analog/Mixed-signal/RF % of analog/mixed-signal/RF circuits covered by DFT System Drivers: MPU/PE/DSP % of digital blocks or subsystems covered with DFT % digital blocks or subsystems covered by DFT for 'transition faults' [1] System Drivers: Memories % of memory and periphery covered by yield improvement DFT General SoC requirements % of logic and other non-memory circuits covered by DFT % of perfomance circuits validated by DFT % of DFT impacting system performance (noise, power, sensitivity, bandwidth, etc.) Test data volume reduction factor driven by DFT Systems with high reliability requirements % of ICs containing In-System Test 2011 40 98 90 2012 45 98 90 2013 50 98 95 2014 55 98 95 2015 60 98 98 2016 65 98 98 2017 70 98 98 2018 80 98 98

90 70 40 10 50x <1%

95 70 45 10 100x <1%

95 70 45 10 150x <1%

95 80 50 10 150x <1%

95 80 50 10 150x 2%

98 80 60 5 200x 2%

98 90 60 5 250x 2%

98 90 70 5 250x 2%

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known Notes for Table DESN9 [1] Other emerging fault models such as 'small delay' and 'bridging' not included

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN9 Design for Test Technology Requirements

Year of Production System Driver: Analog/Mixed-signal/RF % of analog/mixed-signal/RF circuits covered by DFT System Drivers: MPU/PE/DSP % of digital blocks or subsystems covered with DFT % digital blocks or subsystems covered by DFT for 'transition faults' [1] System Drivers: Memories % of memory and periphery covered by yield improvement DFT General SoC requirements % of logic and other non-memory circuits covered by DFT % of perfomance circuits validated by DFT % of DFT impacting system performance (noise, power, sensitivity, bandwidth, etc.) Test data volume reduction factor driven by DFT Systems with high reliability requirements % of ICs containing In-System Test Manufacturable solutions exist, and are being optimized 2019 90 98 98 2020 90 98 98 2021 100 98 98 2022 100 98 98 2023 100 98 98 2024 100 98 98 2025 100 98 98 2026 100 98 98

98 100 70 5 300x 3%

98 100 70 5 300x 3%

98 100 72.5 5 300x 4%

98 100 75 5 300x 4%

98 100 75 5 300x 5%

98 100 75 5 300x 6%

98 100 75 5 300x 7%

98 100 75 5 300x 8%

Notes for Table DESN9 [1] Other emerging fault models such as 'small delay' and 'bridging' not included

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN10 Design for Manufacturability Technology Requirements

Year of Production Normalized mask cost from public and IDM data % Vdd variability: % variability seen in on-chip circuits % Vth variability: doping variability impact on Vth, (minimum size devices, memory) % Vth variability: includes all sources % Vth variability: typical size logic devices, all sources % CD variability % circuit performance variability circuit comprising gates and wires % circuit total power variability circuit comprising gates and wires % circuit leakage power variability circuit comprising gates and wires

2011 1.0 10% 40% 42% 20% 12% 42% 51% 126%

2012 1.3 10% 40% 42% 20% 12% 42% 51% 126%

2013 1.7 10% 40% 42% 20% 12% 42% 51% 126%

2014 2.2 10% 45% 47% 23% 12% 45% 55% 129%

2015 2.8 10% 45% 47% 23% 12% 45% 55% 129%

2016 3.7 10% 50% 53% 25% 12% 47% 59% 132%

2017 4.9 10% 50% 53% 25% 12% 47% 59% 132%

2018 6.4 10% 55% 58% 28% 12% 50% 63% 135%

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN10 Design for Manufacturability Technology Requirements

Year of Production Normalized mask cost from public and IDM data % Vdd variability: % variability seen in on-chip circuits % Vth variability: doping variability impact on Vth, (minimum size devices, memory) % Vth variability: includes all sources % Vth variability: typical size logic devices, all sources % CD variability % circuit performance variability circuit comprising gates and wires % circuit total power variability circuit comprising gates and wires % circuit leakage power variability circuit comprising gates and wires

2019 8.4 10% 55% 58% 28% 12% 50% 63% 135%

2020 11.0 10% 60% 63% 30% 12% 52% 68% 138%

2021 14.4 10% 60% 63% 30% 12% 52% 68% 138%

2022 18.8 10% 65% 68% 33% 12% 55% 72% 141%

2023 24.6 10% 65% 68% 33% 12% 55% 72% 141%

2024 32.1 10% 70% 74% 35% 12% 57% 77% 145%

2025 ? 10% 70% 74% 35% 12% 57% 77% 145%

2026 ? 10% 75% 79% 38% 12% 60% 81% 148%

s exist, and are being optimized

Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN11 Correspondence between Design for Manufacturability Requirements and Solutions

Requirement Mask cost

Solution Tools that account for mask cost in their algorithms RDRs (grid-like layouts, no diagonals, etc.) RET tools aware of circuit metrics (timing, power) Statistical leakage analysis and optimization tools Post-tapeout RET interacting with synthesis, timing, P&R Model-based physical verification Model-based physical synthesis Manufacturing-friendly design rules (hard rules)

Explanation of the Correspondence Obvious Better manufacturability and yield, less mask complexity More effective optimization, fewer design iterations Estimation and control of soaring leakage variability By interacting with earlier-in-the-flow EDA tools, can more effectively address litho issues Can address litho issues with precision Explicit litho model-based approach moves into the physical synthesis toolset Reduces mask, manufacturing cost; addresses printability Obvious Better manufacturability and yield, less mask complexity More effective optimization, fewer design iterations Estimation and control of soaring leakage variability By interacting with earlier-in-the-flow EDA tools, can more effectively address litho issues Can address litho issues with precision Explicit litho model-based approach moves into the physical synthesis toolset Improves power delivery problem Better estimate of variability impact reduces overdesign Lowers outlook of % Vth variability by a factor of 2 to 3 Better estimate of variability impact reduces overdesign Inherent circuit robustness to variability Estimation and control of soaring leakage variability. Lowers outlook of % Vth variability by a factor of 2 to 3 More effective optimization, fewer design iterations Better manufacturability and yield, less mask complexity Inherent circuit robustness to variability Leakage power variability will soar. Statistical leakage tools are critical to estimate and control it. By interacting with earlier-in-the-flow EDA tools, can more effectively address litho issues Can address litho issues with precision Explicit litho model-based approach moves into the physical synthesis toolset Reduces mask, manufacturing cost; addresses printability Reduces critical dimension variability Routing-friendly rules reduce design, mask, and manufacturing complexity Inherent circuit robustness to variability Inherent circuit robustness to variability Estimation and control of soaring leakage variability. By interacting with earlier-in-the-flow EDA tools, can more effectively address litho issues Can address litho issues with precision Explicit litho model-based approach moves into the physical synthesis toolset Reduces mask, manufacturing cost; addresses printability Routing-friendly rules reduce design, mask, and manufacturing complexity improves power delivery Lowers outlook of % Vth variability by a factor of 2 to 3 Lowers outlook of % Vth variability by a factor of 2 to 3

% Vdd variability seen at on-chip circuits

Tools that account for mask cost in their algorithms RDRs (grid-like layouts, no diagonals, etc.) RET tools aware of circuit metrics (timing, power) Statistical leakage analysis and optimization tools Post-tapeout RET interacting with synthesis, timing, P&R Model-based physical verification Model-based physical synthesis 3D and integration of high-quality regulators and insultors

% Vth variability (doping variability impact) % Vth variability Includes all sources

Statistical analysis, opt tools and flows (Vdd, T, Vth) Fin-fets and thin-body-soi-fets Statistical analysis, opt tools and flows (Vdd, T, Vth) Adaptable and redundant circuits Statistical leakage analysis and optimization tools Fin-fets and thin-body-soi-fets

% CD variability

RET tools aware of circuit metrics (timing, power) RDRs (grid-like layouts, no diagonals, etc.) Adaptable and redundant circuits Statistical leakage analysis and optimization tools Post-tapeout RET interacting with synthesis, timing, P&R Model-based physical verification Model-based physical synthesis Manufacturing-friendly design rules (hard rules) Ultroviolet lithography

Circuit performance variability (gates and wires) Circuit power variability (gates and wires)

Router-friendly standard cells Adaptable and redundant circuits Adaptable and redundant circuits Statistical leakage analysis and optimization tools Post-tapeout RET interacting with synthesis, timing, P&R Model-based physical verification Model-based physical synthesis Manufacturing-friendly design rules (hard rules) Router-friendly standard cells 3D and integration of high-quality regulators and insultors Fin-fets and thin-body-soi-fets

Circuit leakage power variability (gates and wires)

Fin-fets and thin-body-soi-fets

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN12 Required Simulation Models for AMSRF Design

Available Transistor models

Required Immediately

Required As Soon As Possible

Transistor level models of Parameterized behavorial models of OpAmps, oscillators, mixers, oscillators, mixers, low-noise amplifiers, etc, low noise amplifiers which are pin-compatible with corresponding transistor-level models Parameterized behavioral models of phase-locked loops, A/D and D/A converters, receiver front ends, etc

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN13 Design Technology Improvements and Impact on Designer Productivity

DT Improvement None In-House Place and Route

Year 1990 1993

Productivity Delta

Productivity (Gates/Year/Designer) 4K HW 5.55K HW

Cost Component Affected PD Integration

Description of Improvement

38.90%

Automated block placement and routing, transferred from the semiconductor house to the design team Engineer capable of pursuing all required tasks to complete a design block, from RTL to GDSII Blocks from 2,50074,999 gates Blocks from 75,0001M gates

Tall-Thin Engineer

1995

63.60%

9.09K HW

Chip/circuit/PD verification Circuit/PD verification Chip/circuit/PD integration verification Chip/circuit/PD integration EDA support SW development verification SW development verification

ReuseSmall Blocks ReuseLarge Blocks

1997 1999

340% 38.90%

40K HW 56K HW

IC Implementation Suite

2001

63.60%

91K HW, 87K SW

Tightly integrated tool set that goes from RTL synthesis to GDSII through IC place and route Tightly integrated RTL verification tool suite including all simulators and formal tools needed to complete the verification process Level above RTL, including both HW and SW design and consisting of behavioral (where the system function has not been partitioned) and architectural (where HW and SW are identified and handed off to design teams) levels Blocks >1M gates; intellectual-property cores

RTL Functional Verification Tool Suite Transactional Modeling

2003

37.50%

125K HW, 87K SW

2005

60%

200K HW, 250K SW

Very Large Block Reuse

2007

200%

600K HW, 323K SW

Chip/circuit/PD verification

Homogeneous Parallel Processing

2009

100% HW, 100% SW

1200K HW, 646K SW

Chip/circuit/PD design Many identical cores provide specialized processing and verification around a main processor, enabling performance, power efficiency, and high reuse SW development System design and verification Chip/circuit/PD verification System design and verification SW development verification SW development SW development System design and verification Virtualization tools used to allow development prior to completed silicon Like RTL verification tool suite, but also with automation of the verification partitioning step Fully functional platforms used as a block in larger platform design (e.g., ARM in OMAP) A hardware virtualization platform that enables an RTL handoff of a SOC Many specialized cores provide processing around a main processor, which allows for performance, power efficiency, and high reuse Enables compilation and SW development in highly parallel processing SOCs Memories capable of on-chip memory management Automates true system design on- and off-chip for the first time, including electronic, mechanical and other heterogeneous technologies Describes the system specification in a manner that allows automated design and validation

Software Virtual Prototype Intelligent Testbench

2011 2012

300% SW 37.5% HW

1200K HW, 2584K SW 1650K HW, 2584K SW

Reusable Platform Blocks Silicon Virtual Prototype Heterogeneous (AMP) Parallel Processing Many-Core SW Development Tools Concurrent Memory System-Level Design Automation (SDA)

2013 2015 2017

200% HW, 100% SW 100% HW 100% HW, 100% SW

4949K HW, 5168K SW 9897K HW, 5168K SW 19794K HW, 10336K SW

2019 2021 2023

60% SW 100% SW 60% HW, 37.5% SW

19794K HW, 16537K SW 19794K HW, 33074K SW 31671K HW, 45476K SW

Executable Specification Total

2025

200% HW, 200% SW 7920% HW, 21119% SW

95013K HW, 136429K SW

System design and verification

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN14 Low-Power Design Technology Improvements and Impact on Dynamic and Static Power
DT Improvement Low Power Physical Libraries Year Dynamic Power Improvement (x) 1.50 Static Power Improvement (x) 1.50 Description of Improvements Optimizing transistor size, layout style and cell topology for the standard-cell library Biasing wells of devices independently of the sources to shift the threshold voltage Delivering a positive or negative voltage below a transistor to reduce leakage Turning off the power supplies to idle blocks for leakage reduction Dynamic management of supply voltage and operating frequency for power reduction Reduce amount of off-chip memory accesses for performance improvement and power reduction Using multithreads to improve hardware utilization with leakage reduction Using one physical server to support multiple guest operating systems simultaneously Parallel instruction issue and execution for performance improvement and power reduction Lowering the frequency by using multiple processors and parallel programing Virtualization tools to allow the programmer to develop software prior to silicon Designing blocks that operate at different frequencies Lowering Vdd to 400 - 500 mV Hardware/software partitioning at the behavioral level based on power Using multiple types of processors in a parallel computing architecture Using multiple types of processors in a parallel computing architecture Developing software using power consumption as a parameter Non-clock driven design

Back Biasing Adaptive Body Biasing (ABB) Power Gating Dynamic Voltage/Frequency Scaling (DVFS)

1.00 1.20 0.90 1.50

1.35 2.00 10.00 1.00

Multilevel Cache Architecture

Before 2011

1.00

1.20

Hardware Multithreading Hardware Virtualization

1.00 1.00

1.30 1.20

Superscalar Architecture

1.00

2.00

Symmetric Multiple Processing (SMP) Software Virtual Prototype 2011

1.50 1.23

1.00 1.20

Frequency Islands Near-Threshold Computing Hardware/Software Co-Partitioning Heterogeneous Parallel Processing (AMP) Many Core Software Development Tools Power-Aware Software Asynchronous Design Total

2013 2015 2017 2019 2021 2023 2025

1.26 1.23 1.18 1.18 1.20 1.21 1.21 4.66

1.00 0.80 1.00 1.00 1.00 1.00 1.00 0.96

The International Technology Roadmap for Semiconductors, 2011 Edition

Table DESN15 Three Phases of Design Product Maturity and Design Challenges in 3DIC

2011 - 2013 Interposers 3D Technologies Homogeneous silicon stack

2013 - 2017 Memory tightly integrated with Logic

2017-2020 Multiscale heterogeneous 3D Optimized 3D subsystems Monolithic 3DICs

Exemplar Product(s)

DRAM stack Yield enhancement

Mobile memory-on-logic Significant power savings Bandwidth enhancement, especially to 2-4 DRAMs

Exascale compute node Highly integrated systems Solve the memory wall Cost-optimized systems

Product Advantages Miniaturization Design Challenges Early Design (Pathfinding) Chip-package codesign with interposers Thermal-driven floorplanning, including transients Transient thermal prediction to 5 deg C accuracy. Total chip-package stress control Power integrity and IR drop with interposers and TSVs to 10 mV accuracy Chip-package and chip-chip design interchange to permit 5 deg C and 10 mV accuracy

Heterogeneous system optimization system planning; cost; thermal and power delivery cooptimization Transient thermal prediction to 1 deg C accuracy Low-overhead power delivery of 100+ Amps with 10 mV accuracy Interchange of complex tradeoffs including heterogeneous die and multiple package solutions

Thermal & Stress Power Delivery

TSV stress design rules Power integrity with interposers Chip-package design interchange for power and signal integrity and thermal design

Standards and Formats

Optimized test flow and yield management for Optimized test flow and yield management for logic on Test and Yield Management ~4 chip stacks. Cost-effective interposer memory ~ 4 chip stacks testing at < 10 micron pitch

Optimized test flow and yield management heterogeneous systems of > 10 die

The International Technology Roadmap for Semiconductors, 2011 Edition