Version 3.

ECE 18-760 FALL 2001 VLSI CAD: Logic to Layout

Rob A. Rutenbar HH 3105 Lyz Knight Amit Singhee HH 3107 HH 3104 x8-3334 x8-5087 x8-6646 rutenbar@ece.cmu.edu lyz@ece.cmu.edu asinghee@ece.cmu.edu

FACULTY COURSE SECRETARY TEACHING ASSISTANT MEETING TIMES CLASS WEB PAGE PRE-REQUISITES

Tuesday, Thursday 12:30 - 2:20pm, HH B131

http://www.ece.cmu.edu/~ee760

Necessary Background 15-211, 15-212 18-240 Some exposure to VLSI ideas

Comments about Assumed Skills Basic CS data structures and algorithms, programming in C language, UNIX Basic digital design and verification, with combinational and sequential logic 18-321 or 18-322, or by permission

TEXTBOOKS

Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, G. De Micheli. Also, extensive lecture notes will be provided. Graduate students and serious seniors interested in a broad exposure to the ideas behind the design of the algorithms inside VLSI CAD tools for logic and layout. Assignment 6 Homeworks Description Analysis & design of algorithms and small programs that illustrate core CAD ideas 3 Projects Programming assignments (JAVA/C++/UNIX) to build CAD tools 3 Paper reviews Analysis of topics from current CAD literature % of Grade 40% 45% 15%

INTENDED AUDIENCE

ASSIGNMENTS

WHAT 18-760 IS NOT

A circuits class. A design class where you mostly use other peoples CAD tools. Another class involving only mindless hacking (as opposed to thinking). Math-free, i.e., theres some discrete math in this class, and some continuous math. An applied algorithms class. A class where you get to look inside CAD tools and see what makes them work. A natural bridge between CE and CS applications and ideas. A class where you get to build (simplified chunks of) VLSI CAD tools. A good course for wouldbe CAD folks, or would-be VLSI designers, or folks just interested in nice algorithms that deal with 1s and 0s, graphs, time & waveforms, polygons.

WHAT 18-760 IS

TENTATIVE SYLLABUS (i.e., things may change...)

WEEK 1 8/28 8/30 WEEK 2 9/4 9/6 WEEK 3 9/11 9/13 WEEK 4 9/18 9/20 WEEK 5 9/25 9/27 WEEK 6 10/2 10/4 WEEK 7 10/9 10/11 WEEK 8 10/16 10/18 WEEK 9 10/23 10/25 WEEK 10 10/30 11/1 WEEK 11 11/6 11/8 WEEK 12 11/13 11/14 WEEK 13 11/20 11/22 WEEK 14 11/27 11/29 WEEK 15 12/4 12/6 WEEK 16 12/11 Introduction to CAD flow of ICs; Advanced Boolean Algebra Advanced Boolean Algebra, cont. Advanced Boolean Algebra, cont. JAVA Language Review Boolean Representation: BDDs Boolean Representation: BDDs, cont Boolean Representation: BDDs, cont Formal Verification: Finite State Machine Equiv Formal Verification: FSM Equivalence, continued 2-Level Logic Synthesis: ESPRESSO 2-Level Logic Synthesis: ESPRESSO, cont. Multilevel Logic Synthesis: Boolean Network Model Multilevel Logic Synthesis: Algebraic Division Project 2 Review Multilevel Logic Synthesis: Rectangle Covering Multilevel Logic Synthesis: Rectangle Covering, cont Multilevel Logic Synthesis: Role of Dont Cares Technology Mapping Component Placement for ASICs Component Placement for ASICs, cont Component Placement for ASICs, cont Component Routing for ASICs Project 3 Review Component Routing for ASICs, cont Static Timing Analysis. NO CLASS--THANKSGIVING BREAK Static Timing Analysis, cont. Electrical Delay Analysis RAR away; guest lecs RAR away; guest lec

HW

Proj Paper

hw1

hw2 Proj1

Pap1 hw3
note revised deadlines here

Proj2 hw4 Pap2

hw5 Proj3 Pap3

Geometric Data Structures for Analysis & Verification Geometric Data Structures, cont. Geometric Data Structures, cont. RAR away; guest lec

hw6