Brief Tutorial on SystemC

Hiren D. Patel
hiren@eecs.berkeley.edu http://www.eecs.berkeley.edu/hiren University of California, Berkeley, CA Thanks to Deian Tabakov for part of these slides dtabakov@rice.edu

November 1, 2007

Henri Matisse, Naked Blue IV, 1952, Nice, France

Outline

Motivation Needs from an ESL Methodology The SystemC Proposition Fundamentals of SystemC SystemC Language Simulation Semantics Example of an EXOR gate Example of a simple counter Summary Installation on Cygwin

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Motivation
Increasing design complexity Higher requirement demands Heterogeneous functionalities
Video, music, data, and communication

Faster and better

New architectures, and technology.

Intelligent and distributed

Power-aware technology, networked embedded systems

Shorter time-to-market Release design as a product in a shorter period of time Reduce design cycle by
Early design exploration Reduce validation and verication eorts Hardware and software co-design
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Motivation

Designers struggle with increasing requirements

Methodologies and tools do not scale

Employ Abstraction is the key [4] concept

Raise the abstraction layer to Electronic System Level (ESL) ESL: a level above RTL including hardware and software design

Lack of consensus as to the correct abstraction layer

Proliferation of methodologies, languages and tools that realize them. Examples:
Metropolis [3] Rosetta [1] SystemC-H [2]

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Needs from an ESL Methodology?

Testbenchs

ESL Model

Model Simulator

Model Simulator

Commercial IPs

Specification

Verification Engine

Analysis (performance, power, ...)

Test Generation

Behavioral Synthesis

HW/SW Partitioning

...

RTL

...

Equivalence Checkers

Specication at various levels of abstraction

Formal: analysis, reasoning and better comprehension. Informal: executable.

Hardware/software modeling and simulation. Fast simulation speed. Renement. Path to traditional synthesis tools
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The SystemC Proposition

An ESL design methodology
Multiple abstraction layers supported.
Open SystemC Initiative (OSCI) Open Core Protocol International Partnership (OCP-IP)

Algorithmic Level

Functional

Layer 3: Message Layer - Untimed functionality - Interface method call

Untimed Functional

Untimed Functional Untimed Functional

Untimed Functional

Untimed Functional

Programmers View: Memory map

Bus generics Masters/Slaves

Layer 2: Transaction Layer - Architectural decisions - Coarse grain timing Layer 1: Transfer Layer - Cycle accurate - Software development

TLM

TLM

TLM

Programmers View with Timing: Bus architectures Approx. Timing Time accurate protocols

TLM

TLM

TLM

TLM

Cycle Accurate Level: Synchronous (Clock edge)

Word transfers Cycle accurate Layer 0: Register Transfer Layer - Pin accurate

RTL

RTL

RTL

RT Level: Registers, gates

Pin/Bit/Signal Cycle accurate

RTL

RTL

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The SystemC Proposition

A free library of C++ classes for modeling at RTL and above RTL
Discrete-event simulation semantics Hardware-specic data-types, communication channels IEEE 1666 standard
Methodology-specific Libraries Master/slave libraries Layered Libraries Verification (SCV), SC-AMS

Primitive Channels sc_signal, sc_mutex, sc_semaphore, sc_fifo, etc. Core Language Modules Ports Processes Interfaces Channels Events Event-driven simulation kernel C++ Data Types 4-valued logic 4-valued logic vector Bits and bit vectors Arbitrary prcecision integers Fixed-point C++ user-defined

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Current SystemC Methodology

Concept De nition Phase Testing and Correction Phase

Implementation Phase Design Phase System Level Design Space Exploration Modeling & Validation Hardware/ Software Partitioning Hardware development Software development RTL Modeling & Validation Software

DISCONNECT

Logic Synthesis

Hardware

Disconnect between high-level model and traditional synthesis path. Designs are often times re-implemented in RTL. Mainly used for early design space exploration and concept realization.
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Fundamentals of SystemC
Modules: the building blocks of SystemC models Hierarchy Abstraction IP reuse
sc_signal SC_MODULE SC_MODULE (Child Module) (Child Modules)

sc_in

SC_METHOD

sc_out

sc_in

SC_THREAD
module memory (local variables)

sc_inout

Helper Method Helper Method

sc_out

Figure: SC MODULE
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Fundamentals of SystemC
Modules: the building blocks of SystemC models Example (Structure of a module)
SC_MODULE(Module_name) { // Declare ports, internal data, etc. // Declare and/or define module functions SC_CTOR(Module_name) { // Body of the constructor // Process declarations and sensitivities SC_METHOD(function1); sensitive << input1 << input2; SC_THREAD(function2); sensitive << input1 << clk; } };
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Fundamentals of SystemC

Processes: describe component behaviors SC THREADs

Can be suspended (wait()) Implicitly keep state of execution

SC METHODs
Execute their body from beginning to end Function call equivalent (Simulates faster) Does not keep implicit state of execution

Processes must be contained in a module (but not every member function is a process!)

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Fundamentals of SystemC

Data types Four-valued logic types (01XZ) Arbitrary-precision integers Time

SC SEC, SC MS, SC US, SC NS, etc. sc time t1(42, SC NS) creates a time object representing 42 nanoseconds Integer-valued model of time

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Mechanisms for Abstraction

Interfaces: contract between modules for communication C++ interface Ports: helper objects for communication Agents for connecting modules with their environment Forward calls to the channel on behalf of the module Channels: workhorses for transmitting data Communication between modules Implements the functionality dened in the interfaces

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Mechanisms for Abstraction

ports MODULE 2

MODULE 1 signals

MODULE 3 channels

Figure: Modules, channels, ports, signals

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Interfaces and Ports

Every port expects a particular type of interface Example (nand.h) #include "systemc.h" SC MODULE(nand) { sc in<bool> A, B; sc out<bool> F; ...

// declare a NAND sc module // input signal ports // output signal ports

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Interfaces and Ports

Every port expects a particular type of interface Example (nand.h) #include "systemc.h" SC MODULE(nand) { // declare a NAND sc module sc port<sc signal in if<bool>,1> A,B; // input sig. sc out<bool> F; // output signal ports ...

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Interfaces and Ports

Every port expects a particular type of interface Example (nand.h) #include "systemc.h" SC MODULE(nand) { // declare a NAND sc module sc port<sc signal in if<bool>,1> A,B; // input sig. sc port<sc signal out if<bool>,1> F; // output sig. ...

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Interfaces and Ports

Every port expects a particular type of interface Example (nand.h) #include "systemc.h" SC MODULE(nand) { // declare a NAND sc module sc port<sc signal in if<bool>,1> A,B; // input sig. sc port<sc signal out if<bool>,1> F; // output sig. ... Every port can use only the methods dened in the interface Example (nand.h) ... void do it() { // a C++ function F.write( !(A.read() && B.read()) ); } ...
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Channels
Channels implement interfaces One channel can implement multiple interfaces Many channels can implement the same interface Example (exor.h) SC MODULE(exor) { sc in<bool> A, B; sc out<bool> F; nand n1, n2, n3, n4; sc signal<bool> S1, S2, S3; ... For example, sc signal<T> implements two interfaces: sc signal in if<T> and sc signal inout if<T>
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Events
In SystemC events are objects (sc event) that determine whether a process execution should be triggered or resumed An event is notied when a particular condition occurs Rising edge of a clock Change of a value of a signal Explicit call (e.notify()) Many others Three types of notication: Immediate: function call equivalent. Delta: delayed for a small increment of time (delta-delayed). Timed: delayed for a dened increment of time. Event notication schedules processes that are sensitive to it, to be triggered.
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Simulation Semantics
Initialization Stage

notify();

// immediate notification
Ready-to-run processes

Evaluate Stage Progress Time

Delta Events Update Events

Update Stage

notify(n); // timed notification

notify(SC_ZERO_TIME); // delayed notification

Figure: SystemC Discrete-event Kernel

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Simulation Semantics

Initialize
Mark all processes runnable Each SC METHOD will be executed once Each SC THREAD will be executed until the rst synch point

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Simulation Semantics

1 2

Initialize Evaluate
Select an eligible process and run it If the process uses immediate notication, other processes may become eligible too Continue selecting eligible processes until none are left

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Simulation Semantics

1 2 3

Initialize Evaluate Update

Primitive channels are allowed to perform an update() May generate additional delta-event notications, thus rendering more processes runnable

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Simulation Semantics

1 2 3 4

Initialize Evaluate Update If there are runnable processes, loop back to the Evaluate phase (step 2)

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Simulation Semantics

1 2 3 4

Initialize Evaluate Update If there are runnable processes, loop back to the Evaluate phase (step 2) Advance the time
At this point there are no runnable processes Advance simulation clock to the earliest pending timed notication

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Simulation Semantics

1 2 3 4

Initialize Evaluate Update If there are runnable processes, loop back to the Evaluate phase (step 2) Advance the time Determine runnable processes and go to Evaluate phase (step 2)

5 6

Note: Simulation Kernel = SystemC Scheduler = Simulation Scheduler

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Modeling an EXOR gate

Figure: NAND gate

Example source: http://www.doulos.com/knowhow/systemc/tutorial/

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Modeling an EXOR gate

Example (nand.h) #include "systemc.h" SC_MODULE(nand) { sc_in<bool> A, B; sc_out<bool> F; // declare a NAND sc_module // input signal ports // output signal ports

void do_it() { // a C++ function F.write( !(A.read() && B.read()) ); } SC_CTOR(nand) { SC_METHOD(do_it); sensitive << A << B; } }; // constructor for the module // register do_it() w/ kernel // sensitivity list

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Modeling an EXOR gate

Figure: EXOR gate

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Modeling an EXOR gate

Example (exor.h) #include "nand.h" SC_MODULE(exor) { sc_in<bool> A, B; sc_out<bool> F; nand n1, n2, n3, n4; sc_signal<bool> S1, S2, S3; SC_CTOR(exor) : n1("N1"), n2("N2"), n3("N3"), n4("N4") { n1.A(A); n1.B(B); n1.F(S1); n2 << A << S1 << S2; n3(S1); n3(B); n3(S3); n4 << S2 << S3 << F; } };
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Modeling an EXOR gate

Figure: Test Bench

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Modeling an EXOR gate

Example (stim.h) #include "systemc.h" SC_MODULE(stim) { sc_out<bool> A, B; sc_in<bool> Clk; void StimGen() { A.write(false); B.write(false); wait(); // wait for the next clock tick A.write(false); B.write(true); wait(); // wait for the next clock tick ... sc_stop(); // notify kernel to stop simulation } SC_CTOR(stim) { SC_THREAD(StimGen); sensitive << Clk.pos(); } };
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Modeling an EXOR gate

Example (mon.h) #include "systemc.h" SC_MODULE(mon) { sc_in<bool> A, B, F; sc_in_clk Clk; void Monitor() { while(1) { wait(); cout << sc_time_stamp() << "\t" << A.read() << " " << B.read() << " " << F.read() << endl; } } SC_CTOR(mon) { SC_THREAD(Monitor); sensitive << Clk.pos(); cout << "Time\tA B F" << endl; } };
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Modeling an EXOR gate

Example (Putting it all together) #include "stim.h" #include "exor.h" #include "mon.h" int sc_main(int argc, char* argv[]) { sc_signal<bool> ASig, BSig, FSig; sc_clock TestClk("TestClock", 10, SC_NS, 0.5); stim Stim1("Stimulus"); Stim1.A(ASig); Stim1.B(BSig); Stim1.Clk(TestClk); exor DUV("exor"); DUV.A(ASig); DUV.B(BSig); DUV.F(FSig); sc_start(); return 0; }
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mon Monitor1("Monitor"); Monitor1.A(ASig); Monitor1.B(BSig); Monitor1.F(FSig); Monitor1.Clk(TestClk);

// run forever

Modeling an EXOR gate

Example (Putting it all together) #> ./sandbox SystemC 2.1.v1 --- Jun 13 2007 04:39:21 Copyright (c) 1996-2005 by all Contributors ALL RIGHTS RESERVED A B F 0 0 1 0 1 1 1 0 1 1 1 0

Time 0 s 10 ns 20 ns 30 ns

Simulation stopped by user. #>

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Simulation Semantics
Example (main.cc)
#include "stim.h" #include "exor.h" #include "mon.h" int sc main(int argc, char* argv[]) { sc signal<bool> ASig, BSig, FSig; sc clock TestClk("TestClock", 10, SC NS, 0.5); ...

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Simulation Semantics
Example (main.cc)
#include "stim.h" #include "exor.h" #include "mon.h" int sc main(int argc, char* argv[]) { sc signal<bool> ASig, BSig, FSig; sc clock TestClk("TestClock", 10, SC NS, 0.5, 1, SC NS); ...

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Simulation Semantics
Example (main.cc)
#include "stim.h" #include "exor.h" #include "mon.h" int sc main(int argc, char* argv[]) { sc signal<bool> ASig, BSig, FSig; sc clock TestClk("TestClock", 10, SC NS, 0.5, 1, SC NS); ...

Example (Post-correction output) Time A B F 1 s 0 0 0 11 ns 0 1 1 21 ns 1 0 1 31 ns 1 1 0 Simulation stopped by user. #>

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Simple Counter

Clock Reset Test Case Enable Counter

Monitor

Example from: http://www.asic-world.com/systemc

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Modeling a Simple Counter

Example (counter.h) #include "systemc.h" SC_MODULE (first_counter) { sc_in_clk clock ; sc_in<bool> reset ; sc_in<bool> enable; sc_out<sc_uint<4> > counter_out; sc_uint<4>count; void incr_count () { if (reset.read() == 1) { count = 0; counter_out.write(count); } else if (enable.read() == 1) { count = count + 1; counter_out.write(count); ...
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Modeling a Simple Counter

Example (counter.h) ... cout<<"@" << sc_time_stamp() << " :: Incremented Counter " << counter_out.read()<<endl; } } // End of function incr_count SC_CTOR(first_counter) { cout<<"Executing new"<<endl; SC_METHOD(incr_count); sensitive << reset; sensitive << clock.pos(); } };

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Modeling a Simple Counter

Example (main.cpp) #include "systemc.h" #include "counter.h" int sc_main (int argc, char* argv[]) { sc_signal<bool> clock; sc_signal<bool> reset; sc_signal<bool> enable; sc_signal<sc_uint<4> > counter_out; int i = 0; // Connect the DUT first_counter counter("COUNTER"); counter.clock(clock); counter.reset(reset); counter.enable(enable); counter.counter_out(counter_out); sc_start(1); ...
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Modeling a Simple Counter

Example (main.cpp) // Open VCD file sc_trace_file *wf = sc_create_vcd_trace_file("counter"); // Dump the desired signals sc_trace(wf, clock, "clock"); sc_trace(wf, reset, "reset"); sc_trace(wf, enable, "enable"); sc_trace(wf, counter_out, "count"); // Initialize all variables reset = 0; // initial value of reset enable = 0; // initial value of enable for (i=0;i<5;i++) { clock = 0; sc_start(1); clock = 1; sc_start(1); } ...
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Modeling a Simple Counter

Example (main.cpp) reset = 1; // Assert the reset cout << "@" << sc_time_stamp() <<" reset=1\n" << endl; for (i=0;i<10;i++) { clock = 0; sc_start(1); clock = 1; sc_start(1); } reset = 0; // De-assert the reset cout << "@" << sc_time_stamp() <<" reset=0\n" << endl; for (i=0;i<5;i++) { clock = 0; sc_start(1); clock = 1; sc_start(1); } ...
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Modeling a Simple Counter

Example (main.cpp) ... cout << "@" << sc_time_stamp() <<"enable=1\n" << endl; enable = 1; // Assert enable for (i=0;i<20;i++) { clock = 0; sc_start(1); clock = 1; sc_start(1); } cout << "@" << sc_time_stamp() <<"enable=0\n" << endl; enable = 0; // De-assert enable cout << "@" << sc_time_stamp() << " Terminating simulation\n" << endl; sc_close_vcd_trace_file(wf); return 0;// Terminate simulation }
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Modeling a Simple Counter

Example (main.cpp) SystemC 2.0.1 --- Oct 6 2006 19:17:37 Copyright (c) 1996-2002 by all Contributors ALL RIGHTS RESERVED Executing new @0 s reset=1 WARNING: Default time step is used for VCD tracing. @10 ns reset=0 @40 ns enable=1 @41 @43 @45 @47 @49 @51 @53 @55 @57 @59 @61 @63 @65 @67 @69 @71 @73 @75 @77 @79 @80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented :: Incremented enable=0 Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter Counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3

@80 ns Terminating simulation

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Summary

SystemC is currently poised as the ESL language of choice Modeling and simulation using SystemC at higher abstractions than RTL TLM (not covered) is the way to go Lots of resources available online Download and try it out

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Summary

Core SystemC concepts Process : functionality Event : process synchronization Sensitivity : basis of event-driven simulation Channel : process communication Module : encapsulation Ports : external view of the module

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Problematic Cygwin Installation

Systemc version 2.2 compiles ne on Linux/Unix distributions Cygwin - always has problems
std::wctomb not declared ... Stack size issues

Solution
Compile using pthreads instead of QuickThreads Set SC DEFAULT STACK SIZE in sysc/kernel/sc constant.h to 0x50000

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Cygwin Installation
Patch available at:
http://www.eecs.berkeley.edu/hiren/patches/sc-cygwin-hiren.patch

$ $ $ $ $ $ $ $ $ $ $ $

cd workspace tar xvf systemc-2.2.0.tgz mkdir systemc wget patch -p0 < sc-cygwin-hiren.patch cd systemc-2.2.0 mkdir objdir; cd objdir; ../configure --prefix=/cygdrive/c/workspace/systemc make pthreads make pthreads install make pthreads_check

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Buzzwords
EDA Electronic Design Automation SoC System-on-chip TLM Transaction-Level Model(ing) PV Programmers View PVt Programmers View with Time HDL Hardware Description Language RTL Register Transfer Level ASIC Application-Specic Integrated Circuit IP Intellectual Property DSP Digital Signal Processing DUV Design Under Verication

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References
P. Alexander. System-level Design with Rosetta. Elsevier Science [distributor], 2006. FERMAT. Systemc-h. Website: http://fermat.ece.vt.edu/systemc-h/. Metropolis Group. Metropolis: Design Environment for Heterogeneous Systems. Website: http://embedded.eecs.berkeley.edu/metropolis/index.html. J. Kramer. Is abstraction the key to computing? Communications of the ACM, 50(4):3642, 2007.
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