Week 3

Physics of MOS Transistors

1. Metal-Oxide-Semiconductor (MOS) Capacitor Structure

The MOS structure can be thought of as a parallel-plate capacitor, with the top plate being the conductive positive plate, insulator oxide being the dielectric, and doped piece of Si substrate being the negative plate. (We are assuming P-substrate.)

Q=CV1 , C: the capacitance between the 2 plates ; V1: density of electrons varies with V1 Operation as a capacitor: i. As positive charge is placed on the top plate, it attracts negative charge ii. Thus, a channel of free electrons is created at the interface between the insulator and the piece of silicon , potentially serving as a good conducting path if the electron density is sufficiently high

Current flow as a result of potential difference

i.

Current flow from left to right through silicon material, V1 can control the current by adjusting the resistivity of the channel. Thus a voltage-controlled current source can be builded.

Top conductive plate resides on a thin dielectric(insulator) layer, which deposited on the underlying p-type silicon substrate Two contacts are attached to the substrate through two heavily-doped n-type region to allow current flow through the silicon material since direct connection of metal to the substrate would not produce a good ohmic contact. Two contacts : Source(provide charge carriers) and Drain(absorb charge carriers) This device is symmetric, so either of the n+ regions can be source or drain.

The gate plate serve as a good conductor and made by polysilicon, the dielectric layer sandwiched between the gate and the substrate plays a critical role in the performance of transistors and is created by growing silicon dioxide . The n+ regions are called source/drain diffusion.

2. Operation of MOSFET

2.1 Qualitative analysis Formation of channel

MOSPET contains three terminal, thus incur many combinations of terminal voltages and current. Thus a study on the dependence of current upon gate voltage( for a constant drain voltage) and upon the drain voltage ( for a constant gate voltage) have been carried out. Figure (a) show that the source and drain are grounded and the gate voltage is varied. As VG increases from zero, the positive charge on the gate repels the holes in the substrate, thus exposing negative ions and creating a depletion region as shown in Figure (b) First, the holes are repelled by the positive gate voltage, leaving behind negative ions and forming a depletion region. Next, electrons are attracted to the interface, creating a channel (inversion layer) The device still acts as a capacitor-positive charge on the gate is mirrored by negative charge in the substrate- but no channel of mobile charge is created yet. Thus, no current can flow from the source to the drain. MOSFET is off As shown on figure (c), more negative ions are exposed to mirror the charge on the gate and the depletion region under the oxide become deeper. If VG becomes sufficiently positive , free electrons are attracted to the oxide-silicon interface, forming a conductance channel. MOSFET is on. Threshold voltage: gate potential at which the channel begins to appear

Voltage-Dependent Resistor

Conductive channel between S and D can be seen as resistor Since the charge density inside the channel depends on the gate voltage, this resistance is also voltage-dependent.

Voltage controlled attenuator

As the gate voltage decreases, the output drops because the channel resistance increases. This type of gain control finds application in cell phones to avoid saturation near base stations.

3. K 4. K 5.