Coventor SEMulator3D is a powerful 3D semiconductor process modeling platform that offers wide ranging technology development capabilities in a simple

high-speed application. Studies in Virtual Fabrication, Variation Analysis and DesignProcess Prediction are shown to benefit all aspects of semiconductor product development.

Coventor SEMulator3D

Semiconductor Technology Modeling Highlights

David M. Fried, PhD CTO - Semiconductor

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Semiconductor Overview
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Introduction: Recent semiconductor technology advances, including FinFET, TriGate, High-K/Metal-Gate, embedded memories and advanced patterning, have dramatically increased the complexity of integrated processes. The cost and duration of technology development using antiquated trial-and-error experimental methodologies has concurrently increased. A more systematic virtual development approach is required for advanced technologies to achieve their time-to-market objectives. Coventors SEMulator3D software is a powerful 3D semiconductor process modeling platform that offers wide ranging technology development capabilities in a simple, robust, high-speed application. Three key examples of the capabilities of SEMulator3D are demonstrated in Virtual Fabrication, Variation Analysis and Design-Process Interaction. Virtual Fabrication: A Virtual Fabrication Environment offers a platform for semiconductor process development at a lower cost and higher speed than trial-and-error silicon experimentation. This enables fast validation of process assumptions, and visualization of the complex interrelationship of design and process. SEMulator3Ds Process Editor provides a simple GUI for entering a parameterized process description. Any fully integrated flow or any partial flow for a production process or simpler experimental evaluations can be modeled.

Figure 1. SEMulator3D Process Editor enables parameterized evaluation of fully integrated semiconductor processes

Figure 2. Large circuit areas can be modeled quickly for high-resolution structurally accurate 3D models

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Using the Process Editor to develop an integrated flow, individual processes are specified in physical terms, leading to inline specifications for unit process development, equipment/tool development and inline measurement and metrology. The interaction of these process parameters (deposition conformality, etch anisotropy, selectivity, etc.) can be explored in terms of the overall flow. The downstream structural implications of process descriptions are easily visible and measurable in the resulting model. The complexity of state-of-the-art technology makes spreadsheet-analysis of these interactions impossible.

Figure 3. SEMulator3D model showing partial completion of a FinFET gate-stack etch.

Figure 4. The completed gate-stack etch shows minimal metal undercut beneath the polysilicon gate electrode.

To demonstrate the benefits of technology modeling with SEMulator3D, well explore a complex multi-step FinFET gate-stack etch. Due to the 3D nature of the structure, the etch requirements are extremely complex. Etch selectivity, anisotropy, sidewall angle and overetch must be carefully understood and optimized. Undercut of the metal-gate stack will lead to variation of electrical properties and potential downstream yield implications. Differential stacks for NFET and PFET must be explored within the same process model. SEMulator3Ds Viewer allows 3-axis control, material visualization, crosssectioning, and manual measurement capabilities to provide a thorough 3D investigation of any generated model. Fundamental understanding of this structure through this complex etch process is required for technology development, and can eliminate many iterations of trial-and-error integration experiments along with the characterization and analysis resources required by current silicon engineering practice.

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Virtual Metrology and Variation Analysis: Visualization of complex 3D models is critical for development, but quantitative analyses of these models, such as variation studies, are far more valuable. Automated 3D structure measurements are enabled in SEMulator3D by adding virtual metrology operations to any process flow. Iterative parameterized modeling is executed using Batch DOE features of SEMulator3D. Using the powerful capabilities of virtual metrology and Batch DOE together, sensitivity analyses can be performed quickly to understand complex 3D structural variation.

Figure 5. SEMulator3D models showing the impact of mandrel lithography and sidewall spacer thickness on the position and pitch of resulting fins in a Sidewall Image Transfer (SIT) process

Figure 6. Fin-spacing (inner/outer) resulting from variations in mandrel lithography and SIT spacer thickness

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From this data, it is clear that the inner fin spacing is completely controlled by the mandrel lithography. At low lithography biases (large mandrel sizes), the spacers in the SIT process merge, and the process failure is properly captured by the virtual metrology. The outer fin spacing is dictated by both the mandrel lithography and the SIT spacer deposited thickness. Balancing these two process parameters carefully is critical to producing consistent pitch fins (even inner and outer spaces). If fin spacing is not properly controlled, there may be several negative downstream implications, including implant shadowing and epitaxial merging. Predictive Modeling of Design-Process Interaction: Input designs can be automatically manipulated to produce generated (non-design-level) masks, or specific shape adjustments to design data. The modeling engine is flexible enough to apply the process to design data (from the included Layout Editor tool, or via the Virtuoso Bridge to the Cadence design environment), OPC output or even simulated lithographic patterns for the highest accuracy. The result is a process description that can be applied to any design, providing a predictive view into design-technology interactions. SEMulator3Ds advanced Virtual Metrology features enable quantitative analysis of 3D models. Measurement locations can be specified in any design, mimicking production process measurements and metrology such as ellipsometry, profilometry, AFM, CD-SEM and overlay.

Figure 7. SEMulator3D Layout Editor view showing the additional of metrology spots to focus measurements on a design sensitivity, a PFET shorting mechanism in a specific SRAM cell design

This physical extraction allows technologists to validate process conditions throughout the process, and carefully calibrate the SEMulator3D process models with actual hardware measurements. With accurate, high-resolution dimensional

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extraction, a thorough view of process variations can be conducted through batch execution of the parameterized SEMulator3D process model and design data.

Figure 8. Post-Epitaxial PFET space resulting from variations of SIT spacer deposited thickness and PFET epitaxial thickness

Figure 8 is based on a batch run and shows that the post-epitaxial PFET space is sensitive to both parameters. Adequate shorting margin is demonstrated for the nominal 20nm epitaxial thickness for all variations of spacer deposition thickness. This type of sensitivity analysis is essential for establishing process centering conditions. Sensitivity analyses can be also be used to identify process variation parameters that are critical to designers in the presilicon phase of product development. For instance, the resulting data from this DOE study shows some odd, unexpected behavior in the 30nm epitaxial case, which is extremely close to the shorting criterion. Visual examination of the 3D models (Figure 9) shows that this effect is real, and stems from the incomplete removal of the fin-top oxide in the thicker spacer cases, which alters the epitaxial morphology. This has exposed a design-process sensitivity in a process corner that might be rare enough that it will not manifest in silicon until a significant volume of production wafers have been fabricated. Discovering these sensitivities early, during design rule development and DFM analysis, is essential to ensuring robust manufacturing margins on production designs.

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Figure 9. SEMulator3D visualization of three model data points in the PFET shorting process DOE showing the remaining fin-top oxide in Case 2 altering the epitaxial morphology

Conclusion: It is obvious from the recent explosion of process complexity in the semiconductor industry that technologies at 22nm and beyond require advanced virtual development environments to deliver products to market on time. SEMulator3D is the most robust, fastest and most accurate 3D semiconductor process modeling platform in the industry. It provides a virtual fabrication environment that allows technology developers to study complex structures and process interactions. SEMulator3Ds advanced virtual metrology and batch DOE capabilities provide critical quantitative analyses for process centering, electrical sensitivity analyses and design-process interaction. These capabilities benefit all participants in the semiconductor supply chain, from the technology developers to fabless IP providers to equipment and process vendors.