Logic Gates

IRISH S.
JAIME Slide 1
E3/ BS COE
CENGO1(*Prelims*) Slide 2
Digital Fundamentals
Tenth Edition
outline Inverter Timing diagram and application AND gate A X The Inverter OR gate Example waveforms: NAND gate A NOR gate X Exclusive-OR and Exclusive-NOR gates
1 0 0 0 1 1 0 1
Floyd
Chapter 3
A group of inverters can be used to form the 1 s complement of a binary number: Binary number
Floyd, Digital Funda mentals, 10 th ed
Upper 2008 Pearson Education 2009 Pearson Education, Saddle River, NJ 07458. All Rights Reserved
Floy d, Digital Fundamentals, 10th ed
2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Slide 3 Slide 4
1 0 0 1s complement
3- 1
The Inverter A X The inverter performs the Boolean NOT operation. When the input is LOW, the output is HIGH; when the input is HIGH, the output is LOW.
Input
A
LOW (0) HIGH (1)
Slide 5
3-2
The AND Gate The AND Gate
B A A X B
Summary
A B
&X
A B
&
Output
X
HIGH (1) LOW(0)
The NOT operation (complement) is shown with an overbar. Thus, the Boolean expression for an inverter is X = A.
Floyd, Digital Funda mentals, 10 th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The AND gateExample produces waveforms: a HIGH output when all inputs are HIGH; otherwise, the output is LOW. For a 2 - input gate, A the truth table is Inputs Output B A B X in computer programming as a to retain certain bits of a binary number but reset the other bits to 0, you could set a mask with The AND operation is usually shown with a dot between the 1s in the position of the retained bits. variables but it may be implied (no dot). Thus, the AND binary number operation is written as XIf =the A .B or X = AB. 10100011 is ANDed with the mask 00001111, what is the result? 00000011
th Floyd, Digital Funda mentals, Floyd, 10Digital ed Funda mentals, 10 th ed 2009 Pearson Education, Upper 2009 Pearson Saddle River, Education, NJ 07458. Upper All Saddle Rights River, Reserved NJ 07458. All Rights Reserved
0 0 0 0 1 0 The AND1 operation 0 0 is used 1 1 If you 1 want selective mask.
Slide 6
Slide 7
Slide 8
Summary
The AND Gate
A Multisim circuit is shown. XW G1 is a word generator set in the count down mode. XLA 1 is a logic analyzer with the output of the AND gate connected to first (upper) line of the analyzer. What signal do you expect to on this line?
Application Application
The AND Gate
A common application of the AND gate is to enable (that is, to allo w) the passage of a signal (pulse waveform) fro m one point to another at certain times and to inhibit (prevent) the passage A X A =1 X The OR Gate at other times.
B B
Summary
The output (line 1) will be HIGH only when all of the inputs are HIGH.
The OR gate produces a HIGH output if any input is HIGH; if all inputs are LOW, the output is LOW. For a 2 - input gate, the truth table is Inputs Output
A B X
0 0 1 1
Floyd, Digital Funda mentals, 10 th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Funda mentals, 10th ed
0 1 0 1
0 1 1 1
2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved The OR operation is shown with a plus sign (+) between the variables. Thus, the OR operation is written as X = A + B.
Slide 9 Slide 10
Design
The AND Gate
Design a seat belt alarm system to detect when the ignition switch is on, a time r is on for 30 s and when the seat belt is unbuckled.
Slide 11
Slide 12
Summary
The OR Gate
A Multisim c ircuit is shown. XW G1 is a word generator set to count down. XLA1 is a logic analy zer with the output connected to first (top) line of the analyzer. The three 2-input OR gates act as a single 4-input gate. What signal do you expect on the output line?
Summary
X
The OR Gate
A B
A B
=1
The output (line 1) will be HIGH if any input is HIGH; X otherwise it will be LOW.
Example waveforms:
Summary
A B X A B
&
A B X
The NAND Gate
Example waveforms:
th
Slide 13
A The OR operation used to set Upper certain Floyd, Digitalcan Fundabe mentals, 10 in ed computer programming 2009 Pearson Education, Saddle River, NJ 07458. All Rights Reserved bits of a binary number to 1. B ASCII letters have a 1 in the bit 5 position for lower case letters and a 0 in this position for capitals. (Bit positions are numbered X fro m right to left starting with 0.) What will be the result if you The NAND gate is with particularly useful because it is a OR an ASCII letter the 8-b it mask 00100000?
Summary
The NAND Gate
A B X A B
&
Floyd, Digital Funda mentals, 10th ed
universal gate will all other basic gates can be constructed The resulting letter be lower case. from NAND gates. How would you connect a 2- input NAND gate to form a basic inverter?
The NAND gate produces a LOW output when all inputs are HIGH; otherwise, the output is HIGH. For a 2 -input gate, the truth table is Inputs Output
A B X
Slide 14
0 0 1 1
0 1 0 1
1 1 1 0
The NAND operation is shown with a dot between the variables and an overbar covering them. Thus, the NAND operation is written as X = A .B (Alternatively, X = AB.)
Slide 15
Slide 16
Summary
The NAND Gate
A Multisim c ircuit is shown. XW G1 is a word generator set in the count up mode. A four-channel oscilloscope monitors the inputs and output. What output signal do you expect to see?
Summary
The NOR Gate
A B X A B
=1
The NOR gate produces a LOW output if any input is HIGH; if all inputs are HIGH, the output is LOW. For a 2-input gate, the truth table is
Inputs Output
X A B
The output (channel D) will be LOW only when a ll of the inputs are HIGH.
0 0 1 1
0 1 0 1
1 0 0 0
Inputs
The NOR operation is shown with a plus sign (+) between the variables and an overbar covering them. Thus, the NOR operation is written as X = A + B.
2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Funda mentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Slide 17
Slide 18
Summary
The NOR Gate
A B X A B
=1
Summary
X
The XOR Gate
A B
A B
=1
Example waveforms: A B X
The NOR operation will produce a LOW if any input is HIGH.
+5.0 V
The XOR gate produces a HIGH output only when both Summary inputs are at opposite logic levels. The truth table is
Inputs The XNOR Gate
A A B B
Output
X
A B
=1
The XNOR gate 0 produces 0 0 a HIGH output only when both 1 logic 1 level. The truth table is inputs are at the 0 same
1 1 0 1 Inputs 1 0
A B
Output
X
When is the LED is ON for the circuit shown? The LED will be on when any of the four inputs are HIGH.
330 2 X
A B C D
0 as 0 X = AB 1 + AB. The XOR operation is written 0 with 1 0 Alternatively, it can be written a circled plus sign 1 0 0 between the variables as X =1A 1 + B. 1
The XNOR operation shown as X = AB + AB. Alternatively, 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved the XNOR operation can be shown with a circled dot between the variables. Thus, it can be shown as X = A . B.
Slide 19 Slide 20
Summary
The XOR Gate
A B X A B
=1
Slide 21
X
Notice that the XOR gate will produce a HIGH only when e xactly one input is HIGH. If the A and B waveforms are both inverted for the above waveforms, how is the output affected? There is no change in the output.
Summary
Slide 22
Fixed Function Logic Two major fixed function logic families are TTL and CMOS. A third technology is BiCMOS, which combines the first two. Packaging for fixed function logic is shown.
0.335 0.334 in. 0.740 0.770 in.
14 13 12 1 1 10 9 8 14 13 12 1 1 10 9 8
0.250 2 0.010 in.

1 2 3 4 5 6 7
0. 228 0. 244 in.
Pin no.1 ident if iers

14 1
Lead no. 1 identifier

14 1
DIP package
SOIC package
Summary
The XNOR Gate
A B X A B
=1
Slide 23
X
Notice that the XNOR gate will p roduce a HIGH when both inputs are the same. Th is makes it useful for co mparison functions. If the A waveform is inverted but B remains the same, how is the output affected? The output will be inverted.
Slide 24
Summary
Fixed Function Logic Logic symbols show the gates and associated pin numbers.
Summary (1)
(2) (4)
VCC (14)
(1) (2) (4) Fixed Function Logic (5) (5) (9) (9) (8) Some common gate configurations are shown. (10) V V V V (10) 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 (12) (12) (11) (13) (13) (6)
CC CC
(3)
&
(3) (6) (8)
Summary
CC
CC
12 11
10 9
(11)
3 4 5 6 7 GND
Programmable Logic
4 5 6 7 1 2 3 4 5 6 7 G ND
7 GND
VCC
14 13 12 11 10
Slide 25 Slide 26
VCC
A Programmable Logic Device (PLD) can be programmed GND to implement logic. There are various technologies available for PLDs. internal array of AND Floyd, Digital Funda mentals, 10 ed Many use an 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved gates to form logic terms. Many PLDs can be programmed '10 '11 '2 0 '2 1 multiple times. A A B B
VCC 14 V CC 14 VCC 9 8 13 12 11 10 9 8 13 12 11 10 9 8 14 13 12 11 10 9 8 th 4 5 6 7 G ND 1 2 3 4 5 6 7 GND 1 2 3 4 5 6 7 GND 1 2 3 4 5 6 7 GND VCC 14 V CC 14 VCC 9 8 13 12 11 10 9 8 13 12 11 10 9 8 14 13 12 11 10 9 8
'00
'0 2
GND
'0 4 (7)
'08
14 13 12 11 10
SRAM cell
1 2 3 4 5 6 7 G ND 1 2 3 4 5 6 7 GND 1 2 3 4
SRAM cell
5 6 7 GND
SRAM cell
1 2
SRAM cell
3 4 5 6 7 GND
'27
'30
'3 2 SRAM cell SRAM cell
'8 6 SRAM cell SRAM cell
X = AB 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Fixed Function Logic Data sheets include limits and conditions set by the manufacturer as well as DC and AC characteristics. For example, some maximum ratings for a 74HC00A are:
MAXIMUM RATINGS Symbol P arameter Value Unit VCC DC Supply Voltage (Referenced to GND) 0.5 to + 7.0 V V Vin DC Input V oltage (Referenced to GND) 0.5 to V +0.5 V V CC V out DC Output Volt age (Referenced to GND) 0.5 to V V CC +0.5 V I in DC Input Current, per pin 20 mA Iout DC Output Current, per pin 25 mA ICC DC Supply Current, V 50 mA CC and GND pins P Power Dissipation in StillAir, Plastic or Ceramic DIP 750 mW D 500 SOIC Package TSSOP Package 450 Tstg Storage Temperature 65 to + 150 C TL Lead Temperature, 1 mm from Case for 10 S econds C 260 Plastic DIP, SOIC, or TSSOP Package 300 Ceramic DIP
Floyd, Digital Funda mentals, 10 th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Funda mentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Slide 27
Summary
Programmable Logic
entity NandGate is port(A, B: in bit ; LED: out bit); end entity NandGate; architecture GateBehavior of NandGate is signal A, B: bit; begin X <= A nand B; LED <= X; end architecture GateBehavior;
Slide 28
Summary
Programmable Logic In general, the required logic for a PLD is developed with the aid of a computer. The logic can be entered using a Hardware Description Language (HDL) such as VHDL. Logic can be specified to the HDL as a text file, a schematic diagram, or a state diagram.
A text entry for a programming a PLD in VHDL as a 2-input NAND gate is shown for refe rence in the fo llo wing slide. In this case, the inputs and outputs are first specified. Then the signals are described. Although you are probably not familiar with VHDL, you can see that the program is simple to read.
Slide 29 Slide 30
Selected Key Terms

Inverter A logic circuit that inverts or complements its inputs. Truth table A table showing the inputs and corresponding output(s) of a logic circuit. Timing A diagram of waveforms showing the proper time diagram relationship of all of the waveforms. Boolean The mathematics of logic circuits. algebra AND gate A logic gate that produces a HIGH output only when all of its inputs are HIGH.
Floy d, Digital Fundamentals, 10 th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Selected Key Terms

OR gate A logic gate that produces a HIGH output when one or more inputs are HIGH. NAND gate A logic gate that produces a LOW output only when all of its inputs are HIGH. NOR gate A logic gate that produces a LOW output when one or more inputs are HIGH. Exclusive-OR A logic gate that produces a HIGH output only gate when its two inputs are at opposite levels. Exclusive-NOR A logic gate that produces a LOW output only gate when its two inputs are at opposite levels.
Floy d, Digital Fundamentals, 10 th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Slide 31
Slide 32
1. The truth table for a 2- input AND gate is

Inputs
A B
2. The truth table for a 2- input NOR gate is

Inputs
A B
Output
X
Inputs
A B
Output
X
Output
X
Inputs
A B
Output
X
a.
0 0 1 1
0 1 0 1
0 1 1 0 Output
X
b.
0 0 1 1
0 1 0 1
1 0 0 0 Output
X
a.
0 0 0 1 0 4.1The 1 1 Inputs
A B
0 1 A 1 symbol B 0
b.
=1
0 0 X 1 1
0 1 1 0 0 is0for a(n) 1 0 Output

X
a. OR gate
Inputs
A B
Inputs
A B
b. AND gate X
0 c. NOR gate 0 0 d. XOR gate 1
Output
Inputs
A B
c.
0 0 1 1
0 1 0 1
0 0 0 1
d.
0 0 1 1
0 1 0 1
0 1 1 1
c.
0 0 1 1
0 1 0 1
d.
0 0 1 1
0 1 0 1
0 1 1 1
Floy d, Digital Fundamentals, 10 th ed
2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education
Slide 33 Slide 34 Slide 35

3. The truth table for a 2- input XOR gate is
Inputs
A B
Slide 36
Output
X
Output
X
Inputs
A B
a.
0 0 1 1
0 1 0 1
0 1 1 0 Output
X
b.
0 0 1 1
0 1 0 1
1 0 0 0 Output
X
Inputs
A B
Inputs
A B
c.
0 0 1 1
0 1 0 1
0 0 0 1
d.
0 0 1 1
0 1 0 1
0 1 1 1
5. The symbol 6. A is produces for a(n) a HIGH output only when B logic gate that all of its inputs are HIGH is a(n) a. OR gate a. OR gate 8. AND A 2-input b. gate gate produces the output shown. ( X represents b. AND gate the output.) This is a(n) c. NOR gate NOR gate a. ORc. gate d. XOR gate d. NAND b. AND gate gate c. NOR gate d. NAND gate
Floy d, Digital Fundamentals, Floy 10 d,thDigital ed Fundamentals, 10 th ed 2009 Pearson Education, Upper 2009 Pearson Saddle River, Education, NJ 07458. Upper All Saddle Rights River, Reserved NJ 07458. All Rights Reserved 2008 Pearson Education 2008 Pearson Education
A B X
Slide 37
7. The expression X = A + B means a. A OR B b. A AND B c. A XOR B d. A XNOR B
Slide 38
Slide 39
Slide 40
9. A 2-input gate produces a HIGH output only when the inputs agree. This type of gate is a(n) a. OR gate b. AND gate c. NOR gate d. XNOR gate
10. The required logic for a PLD can be specified in an Hardware Description Language by a. text entry b. schematic entry c. state diagrams d. all of the above
Slide 41
Answers: 1. c 2. b 3. a 4. a 5. d 6. b 7. c 8. d 9. d 10. d

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IRISH S.

Floyd, Digital Funda mentals, 10 th ed

Floy d, Digital Fundamentals, 10th ed

0 0 0 0 1 0 The AND1 operation 0 0 is used 1 1 If you 1 want selective mask.

Floyd, Digital Funda mentals, 10 th ed

The NAND Gate

Floyd, Digital Funda mentals, 10th ed

Floyd, Digital Funda mentals, 10th ed

Floyd, Digital Funda mentals, 10 th ed

The XOR Gate

Floyd, Digital Funda mentals, 10 th ed

0.250 2 0.010 in.

0. 228 0. 244 in.

Pin no.1 ident if iers

Lead no. 1 identifier

(3) (6) (8)

'3 2 SRAM cell SRAM cell

'8 6 SRAM cell SRAM cell

Floyd, Digital Funda mentals, 10th ed

Floyd, Digital Funda mentals, 10 th ed

Selected Key Terms

Selected Key Terms

1. The truth table for a 2- input AND gate is

2. The truth table for a 2- input NOR gate is

0 1 1 0 0 is0for a(n) 1 0 Output

Floy d, Digital Fundamentals, 10 th ed

Floy d, Digital Fundamentals, 10th ed

Slide 33 Slide 34 Slide 35

Floy d, Digital Fundamentals, 10 th ed

Floy d, Digital Fundamentals, 10 th ed

Floy d, Digital Fundamentals, 10th ed

Floy d, Digital Fundamentals, 10 th ed

Floy d, Digital Fundamentals, 10 th ed

Floy d, Digital Fundamentals, 10th ed

Floy d, Digital Fundamentals, 10 th ed

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