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3/19/13
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Here is the breadboarded system, together with an annotated picture showing the location of functional blocks. There are a total of 18 556 packages, equivalent to 36 555s.
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Why two-phase clocking rather than edge-triggered logic in the modern style? Well, edge-triggered flip-flops are somewhat trickier to design and
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3/19/13
verify. A two-phase clock feeding a pair of transparent latches is almost bulletproof. One has complete control over the duration of non-overlap between the two phases (to control skew) as well as the overall frequency of the clock. Even clock glitches can be tolerated (provided there is no crosstalk between the phases), since a single clock phase is idempotent. This logic technology should have no trouble scaling up to larger systems. I had hoped to do this small 4-bit CPU:
/ / / /t i n yH a r v a r d a r c h i t e c t u r e4 b i tC P U / / / /F e b r u a r y2 0 1 1 / /P e t e rM o n t a / / m o d u l ec p u ( i n p u tc l k ,r e s e t , o u t p u tr e g[ 4 : 0 ]p c , i n p u t[ 7 : 0 ]i r , o u t p u t[ 3 : 0 ]a d d r , i n p u t[ 3 : 0 ]d i n , o u t p u t[ 3 : 0 ]d o u t , o u t p u tw r ) ; r e g[ 3 : 0 ]a ; r e gc ;
/ /p r o g r a mc o u n t e r / /i n s t r u c t i o n / /d a t aa d d r e s s / /d a t ai n p u t / /d a t ao u t p u t / /w r i t es i g n a l
/ /a c c u m u l a t o r / /c a r r yf l a g
a s s i g na d d r=i r [ 3 : 0 ] ; a s s i g nd o u t=a ; a s s i g nw r=i r [ 7 : 5 ] = = 3 ' b 0 0 1 ; w i r e[ 3 : 0 ]b=i r [ 4 ]?i r [ 3 : 0 ]:d i n ; w i r ez=a = = 4 ' d 0 ; a l w a y s@ ( p o s e d g ec l k ) i f( r e s e t ) p c=0 ; e l s eb e g i n p c=p c + 1 ; c a s e( i r [ 7 : 5 ] ) 3 ' b 0 0 0 :a=b ; 3 ' b 0 0 1 :; 3 ' b 0 1 0 :{ c , a }=a+b+c ; 3 ' b 0 1 1 :a=~ ( a | b ) ; 3 ' b 1 0 0 :p c=i r [ 4 : 0 ] ; 3 ' b 1 0 1 :i f( ! c )p c=i r [ 4 : 0 ] ; 3 ' b 1 1 0 :i f( ! z )p c=i r [ 4 : 0 ] ; 3 ' b 1 1 1 :c=i r [ 0 ] ; e n d c a s e e n d e n d m o d u l e / /d a t am e m o r yo rl i t e r a l / /z e r of l a g
/ /l d a / /s t a / /a d c / /n o r / /j m p / /j n c / /j n z / /s e t c
but there just wasn't time. Its size (after doing the synthesis manually) is 387 555-chips, or 194 packages using the 556. That would need a PCB; it's too big to wire by hand. Here's a PDF of the schematic and the kicad source files. Possible future directions: try for some sort of pass-transistor logic by floating a 555's ground pin and using the open-drain FET in a series mode dynamic latches (with capacitors as storage elements), precharge schemes, DRAM
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