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Howto: Creating a Custom Symbol Library with ABEL-HDL Modules

The Generic Symbol Library included in Synario contains symbols for basic gates and flip-flops that are found in programmable devices. Because every symbol in this library must be able to map to all of the devices that Synario supports, it does not contain every possible device architecture possibility. It also does not contain complex symbols such as counters. You can, however, create your own custom symbol library using ABEL-HDL modules to describe the behavior and architecture of the associated symbol.

Creating ABEL-HDL Modules

If you are not familiar with ABEL-HDL, it is a logic description language that can describe complex circuits in detail. An ABEL-HDL module contains a description of the logical relationship between the moduleís inputs and outputs and may contain information about the architecture of the device it is to be implemented in. You can create entire designs out of ABEL-HDL modules, or create sub-modules that can be linked together in a hierarchical fashion to create larger designs.

The inputs and outputs to ABEL-HDL modules are always called pins, even when the module is not at the top level of the hierarchy. Synario always treats ABEL-HDL PINs as connections to the world outside the module, and NODEs as signals internal to the module. When connected to a higher level schematic, the ABEL-HDL PINs connect to the schematic through the pins on the associated block symbol. This is illustrated in Figure 1 which shows a block symbol for the ABEL-HDL module Example1. In this figure, the pins on the symbol connect to wires in the schematic. The pins on the symbol also connect to the signals that are declared as PINs in the lower-level ABEL-HDL module. The next section, ABEL-HDL Structure, gives a brief description of the structure of ABEL-HDL modules. For more information, refer to the ABEL-HDL Reference Manual.

Keyword: howto AHDL Symbol

structure of ABEL-HDL modules. For more information, refer to the ABEL-HDL Reference Manual . Keyword: howto

Howto: ABEL-HDL Custom Symbol Library

Figure 1: Symbol for ABEL-HDL Module Example1.

Library Figure 1: Symbol for ABEL-HDL Module Example1. ABEL-HDL Structure An ABEL-HDL module consists of a

ABEL-HDL Structure

An ABEL-HDL module consists of a MODULE statement, signal declarations, equations, an optional test vectors section, and an END statement. See the ABEL-HDL Reference for more information on creating ABEL-HDL sources. The module Example1 shows the structure of a small ABEL-HDL module.

MODULE Example1

in1, in2, in3, in4

PIN;

out1, out2, out3, out4 EQUATIONS

out1.D = in1 & in2;

out2.D = in3 & in4;

out3.D = in4 & in1;

PIN ISTYPE ëreg_d, bufferí;

out4.D =

END

in4 & in2 # in3 & in1;

The MODULE keyword defines the module name of the ABEL module. When you create a block symbol for an ABEL-HDL module in a higher level schematic, the symbol name must match the ABEL-HDL module name. This is how Synario identifies where to connect the lower-level ABEL-HDL module.

The declaration section immediately follows the MODULE statement and contains the input and output pin declarations. It may optionally contain node declarations as well as constant definitions. When you create a block symbol for an ABEL-HDL module in a higher level schematic, the symbol pin names must match the spelling and case of the ABEL-HDL pins. Because hierarchical connections are case sensitive, if the symbol pins do not match the case of the ABEL-HDL pins, Synario will not be able to connect the hierarchy and you will get errors during linking.

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Howto: ABEL-HDL Custom Symbol Library

The equations section contains the logic description relating the outputs to the inputs. ABEL-HDL allows logic to be described with Boolean equations, state diagrams, and truth tables. Dot extensions on the signals in Boolean equations describe the device architecture, such as flip-flop types, and controls for presets, resets, clocks, and other device specific features.

Creating Block Symbols

Create a New Block Symbol

To create a block symbol for an ABEL-HDL sub-module in a schematic source, open the Add menu and select New Block Symbol. A window titled New Block Symbol will be opened where you can enter the symbol name (Block Name), and the names of the Input, Output and Bi-directional pins of the ABEL-HDL module. Figure 2 shows how the New Block Symbol editor was used to create the symbol for the Example1 module above.

Figure 2: New Block Symbol

for the Example1 module above. Figure 2: New Block Symbol Edit Symbol After you have created

Edit Symbol

After you have created a block symbol for an ABEL-HDL module and placed it in the schematic, you can edit it to make it look more like the circuit element it represents. To edit a symbol you can either click on the Edit button in the New Block Symbol editor, or you can select Symbol from the Edit menu, and then select the symbol that you wish to edit.

When editing symbols, graphic elements and text can be added, moved, modified, or deleted. However, you should never edit or delete the symbol pins since they define the behavior of the symbol. Each pin has attributes that are set automatically by the New Block Symbol editor. Changing these attributes may cause errors or cause the design to fail.

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Howto: ABEL-HDL Custom Symbol Library

Connecting Busses to ABEL-HDL Modules

ABEL-HDL does not support iterated bus notation. When you create a set of signals in ABEL-HDL, such as

data = [data3 data0];

the set is flattened during compiling and the brackets are removed. In this example, during compiling every instance of the set data is replaced by the individual signals, data3, data2, data1, and data0.

Schematics (including symbols), however, support an iterated bus notation which looks like

data[3:0];

When a schematic bus (or symbol bus pin) is compiled, the elements of the bus remain in the bus and the brackets are not removed. In this example, the individual elements of data[3:0] are data[3], data[2], data[1], data[0]. You can see that if the elements of the symbol pin

data[3:0] and the elements of the ABEL-HDL set [data3 match. This will cause linking errors.

data0] do not

To work around this limitation in ABEL-HDL, you can use a comma delineated bus name for a symbol pin name, instead of a iterated bus name. In the above example, instead of using the symbol pin name data[3:0], you would use the names of the ABEL-HDL pins that you with to bus, separated by commas, e.g. data3, data2, data1, data0.

Important: When you create a symbol bus pin connecting to an ABEL-HDL module, do not use the ABEL-HDL set name as the symbol pin name. Again, during compiling, ABEL-HDL sets are flattened into the individual signals that comprise the set. The set name itself is meaningless once the module is compiled.

For example, the following ABEL-HDL module has four output pins that are grouped into the set outset. To connect a schematic bus to this ABEL-HDL module, create a symbol that has a comma delineated bus for the symbol output pin name, using the names of the ABEL-HDL output pins.

MODULE Example2

in1, in2

out1, out2, out3, out4

PIN;

outset = [out1 out4]; EQUATIONS

out1.D = in1 & in2;

out2.D = in3 & in4;

out3.D = in4 & in1;

PIN ISTYPE ëreg_d, bufferí;

out4.D =

END

in4 & in2 # in3 & in1;

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Howto: ABEL-HDL Custom Symbol Library

Figure 3 shows the New Block Symbol entries used to create a symbol for this ABEL-HDL module. Note that the signals that are to be grouped in a bus are surrounded by ë=í. Figure 4 shows a correctly created symbol. Figure 5 shows an incorrectly created symbol using the ABEL-HDL set name instead of the output pin names. For more information on creating and editing symbols, see the Schematic Entry User Manual.

Figure 3: New Block Symbol with Output Bus Pin.

Manual . Figure 3: New Block Symbol with Output Bus Pin. Figure 4: Correctly Created Block

Figure 4: Correctly Created Block Symbol with Bus Pin

EXAMPLE2 in1 out1,out2,out3,out4 in2 I_11
EXAMPLE2
in1
out1,out2,out3,out4
in2
I_11

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Howto: ABEL-HDL Custom Symbol Library

Figure 5: Incorrectly Created Block Symbol with ABEL-HDL Set Name.

EXAMPLE2 in1 outset in2 I_11
EXAMPLE2
in1
outset
in2
I_11

Hiding Long Bus Names

As you can see in Figure 4 above, block symbols that have comma delineated bus pins can get very long, making the symbol bigger than it needs to be. The symbol in Figure 5 actually looks better on a schematic even though it is incorrect.

You can, however, hide bus pin names and replace them with text. To hide the bus name:

1. Edit the symbol. You can do this by Clicking on the Edit button in the New Block Symbol editor, or by selecting Symbol from the Edit menu in the Schematic Editor.

2. In the Symbol editor select Pin Name Location from the Add menu.

3. In the pin location window, select the ìDonít Showî radio button and click on the bus pin on the symbol to hide the pin name on the symbol.

4. Select Text from the Add menu and type in a new name for the pin. Click on the location where you want to add the text.

5. Resize the symbol (if necessary) using the Drag and Move options from the Edit menu.

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Howto: ABEL-HDL Custom Symbol Library

Managing Symbol and ABEL-HDL Libraries

After you create ABEL-HDL modules and associated block symbols, you

can place them in places where they can be easily imported into a project. Symbols that are placed in the Misc symbol library will be available in the Schematic Editor, allowing you to easily add custom

symbols no matter where your project is located.

that you have created to the Generic\Misc symbol library, simply copy the .SYM file to the following directory

To add a symbol

<Synario>\generic\generic\misc

where <Synario> is the root directory where Synario is installed.

You can also copy the ABEL-HDL file to a central location where you can easily import into a project. There is no restriction to where you can store ABEL-HDL files, as long as you remember where they are. To add an ABEL-HDL source to your project, open the Source menu in the Project Navigator and select Import. Navigate to the directory where your ABEL-HDL files are stored and select the desired ABEL-HDL file to add it to your source. The file will automatically be copied to your local project directory for processing in Synario.

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Howto: ABEL-HDL Custom Symbol Library

A Simple Example

In this example, we will create a small ABEL-HDL module that has a D register with an Asynchronous reset and an Asynchronous preset. The current generic symbol library does not have a symbol like this (with a reset and preset), so this will be a useful addition to the library. The ABEL-HDL module is shown below:

MODULE DFFPC

Title ëD Flip-Flop with Preset and Clear //Inputs Pins

D, P, C, CLK

//Output Pins

Q

EQUATIONS

Q.D

= D;

Q.C

= CLK;

Q.AP = P;

Q.AR = C;

PIN;

PIN ISTYPEíREG_D,BUFFERí;

END

This module has four input pins, a D flip-flop input, controls for preset and reset, and the clock input. There is one output, Q, which is the output of the register. The equations section is very simple, using dot extensions to connect the various inputs to the appropriate register controls.

Once we have created the ABEL-HDL module, we need to create a symbol for it. From the Schematic Editor, we will select the Add menu, and select New Block Symbol. Enter the ABEL-HDL module name as the Block Name, and enter the input and output pins, as shown in Figure 6. Figure 7 shows the resulting block symbol.

Figure 6: New Block Symbol Entries for D Flip-flop.

as shown in Figure 6. Figure 7 shows the resulting block symbol. Figure 6: New Block

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Howto: ABEL-HDL Custom Symbol Library

Figure 7: Block Symbol for D Flip-flop

DFFPC D P Q C CLK I_14
DFFPC
D
P
Q
C
CLK
I_14

Once we have created the symbol, we can edit it to look more like a D flip-flop. Figure 8 illustrates how the edited symbol might look. For this example, I rearranged the symbol pins, hid the pin name of the CLK input and replaced it with a graphics, and moved the InstName and Type attributes to different locations.

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Howto: ABEL-HDL Custom Symbol Library

Figure 8: Edited D Flip-flop Symbol.

P D Q DFFPC C I_13
P
D
Q
DFFPC
C
I_13

To make this symbol available to all projects, simply copy it to the <Synario>\generic\generic\misc directory. It will now show up in the Generic\Misc library in the Schematic Editor when you select Symbol from the Add menu. Copy the file that contains ABEL-HDL module to a centralized directory as well so you can add it to future projects. To add it to a project, use Import from the Project Navigator Source menu, navigate to the directory where the file is located and import it.

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Howto: ABEL-HDL Custom Symbol Library

A More Complex Example

In this is a more complex example, we will create a 4-bit loadable counter that counts down to 0 and rolls. The counter will also have a hold and a reset. The ABEL-HDL module is shown below:

MODULE CNT4DLHR

Title ë4-bit loadable down-counter with hold and resetí //Input Pins CLK, LOAD, HOLD, RESET PIN;

DATA3

DATA0

//Output Pins (counter bits)

Q3

Q0

PIN

PIN ISTYPEíREG_D,BUFFERí;

//Define a set for the counter bits

COUNT = [Q3

Q0];

//Define a set for the DATA bits

DATA = [DATA3 DATA0]; EQUATIONS COUNT.C = CLK;

COUNT.AR = RESET; COUNT.D = (COUNT.Q - 1) & !HOLD & !LOAD

& !(COUNT.Q == 0);

//decrement

# COUNT.Q & HOLD

//hold

# DATA & LOAD

//load

# DATA & (COUNT.Q == 0);

END

This module has inputs for the register clock and reset controls, counter hold and load control, and four input data lines. There are four outputs, one for each of the counter bits. There are also defined two sets, one for the load data lines and one for the counter bits.

The equations consist of clock and reset equations for the counter bits using dot extensions, and counter logic which consists of four product terms. The first product term tells the counter to decrement while HOLD and LOAD are not active and the counter has not reached 0. The second product terms tells the counter to hold its current value if HOLD is active. The third product term loads the counter to the value of the DATA bits when LOAD is active. The fourth product term rolls the counter back to the value on the DATA lines when it reaches 0.

Again, once the ABEL-HDL module has been created, we need to create a symbol for it. From the Schematic Editor, select New Block Symbol from the Add menu. Enter the ABEL-HDL module name as the Block Name and the input and output pins, as shown in Figure 9. Note that in Figure 9, there was not enough room to show all of the inputs. The important thing to notice here is that the bus pins are defined using the =sig1,sig2,sig3Ö= notation. Figure 10 shows the resulting block symbol.

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Howto: ABEL-HDL Custom Symbol Library

Figure 9: New Block Symbol Entries for Counter.

Library Figure 9: New Block Symbol Entries for Counter. Figure 10: Block Symbol for Counter CNT4DLHR

Figure 10: Block Symbol for Counter

CNT4DLHR CLK LOAD HOLD Q3,Q2,Q1,Q0 RESET DATA3,DATA2,DATA1,DATA0
CNT4DLHR
CLK
LOAD
HOLD
Q3,Q2,Q1,Q0
RESET
DATA3,DATA2,DATA1,DATA0

Now you can edit the symbol to hide the bus pin names and to re-scale it. Figure 11 illustrates how the edited symbol might look. For this example, I hid the comma delineated bus names and replaced them with text that looks like schematic iterated bus names. I also re-scaled the symbol so that it doesnít take up as much room on the schematic.

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Howto: ABEL-HDL Custom Symbol Library

Figure 11: Edited Symbol for Counter

CNT4DLHR LOAD HOLD RESET Q[3:0] CLK DATADATA[3:0]
CNT4DLHR
LOAD
HOLD
RESET
Q[3:0]
CLK
DATADATA[3:0]

Concluding Remarks

Using generic ABEL-HDL modules in Synario is an easy way to develop re-usable modules that are tailored for the types of designs you create and the kind of devices you target. You can create modules to describe very simple circuit elements such as flip-flops or large AND gates. You can also create complex modules of counters and other functions that can be quickly re-used. Taking advantage of ABEL-HDL higher order operators can save design time and simplify the design process.

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Howto: ABEL-HDL Custom Symbol Library

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