1

EL 303
Analog Integrated Circuits
Lab4: Second-Order Notch Filter Design


E.Selin Baytok
8088

12.01.2007




Purposes

Designing a Second-Order Notch Filter within the Iollowing speciIications;

Quality Factor Q _ 5
Notch Irequency w
0
at 10MHz













2
INDEX

1. Introduction

2.Determining the Transfer Function
2.1. Approximation Methods
2.1.1. Butterworth Filter
2.1.2. Chebishew Filter
2.1.3 Other Filter Types
2.2 Transfer Function of the Second Order Notch Filter

3. Topology Selection
3.1. Alternative Topologies: Two-Integrator-Loop Biquadratic Circuits
3.1.1. Kerwin-Heulsman-Newcomb (KHN) Biquad
3.1.2. Tow-Thomas Biquad

3.2. Selected Topology
3.2.1. RLC Resonator
3.2.2. RLC resonator with Antoniou Inductance-Simulation Circuit

4. Schematic Design and Schematic Simulations
4.1. Design with Ideal Op-Amps
4.2. Redesign of Previous Op-amp
4.3. Schematic Results

5. Layout Design and Post-Layout Simulations
5.1. Op-amp Layout
5.2. Simulation Results of Op-Amp Layout
5.3. Overall Filter Layout
5.4. Post-Layout Simulations of Overall Layout

6. Conclusion
















3

1.Introduction

In the simplest manner, Iilters are employed in the electronic systems in order to select
or cut out required parts oI the input signal introduced to that system. Their behaviour is
usually modelled with a transIer Iunction which is considered to be the ratio oI the Irequency
dependent output voltage Iunction to that oI input voltage and expressed such as:

T(s) Vout(s) / Vin(s) (a
N
s
N
a
N-1
s
N-1
...a
0
) / (s
M
b
M-1
s
M-1
....b
0
)
(a
N
(s-z
1
) (s-z
2
)...(s-z
N
)) / ((s-p
1
)(s-p
2
)...(s-p
N
))

'z values stand Ior the 'zeros oI this Iunction that makes the output value 0 Ior that
Irequency, while 'p values draws the transIer Iunction to inIinity and is denoted as
'poles.The degree oI the denominator M is considered to be the order oI the Iilter which
determines the ideality oI the system. In the early times oI Iilters, they were designed with Iirst
order characteristics which were in RC, RL or LC conIigurations and less eIIective due to their
wide transition bands between the passband and stopband regions in which the signal is
allowed and rejected by the system respectively. ThereIore there was a need to construct multi-
pole Iilters with better selective Irequency responses.

The second order Iilters as an example to these multi-pole Iilters that we are to
use in this project has a general transIer Iunction oI

T(s) (a
2
s
2
a
1
s ...a
0
) / (s
2
(w
0
/ Q)s w
0
2
)

The distribution oI zeros oI this Iunction on the pole-zero plot determines the Iilter`s
characteristic. There are Iour major possible Iilter characteristic Ior this system:

Lowpass filter is observed when the zeros oI the system are both at inIinity. The poles
dominate the system and causes the input signals to be allowed Ior Irequencies smaller than
second pole Irequency and rejects signals with higher Irequencies. The resulting Iunction oI the
system and a possible realization oI the circuit is shown as Iollows:

T(s) (a
0
) / (s
2
(w
0
/ Q)s w
0
2
)





Fig 1.1. Realization oI a second Fig 1.2. Frequency Response oI a
order Lowpass Filter second order LP Iilter

Highpass filter is observed when both zeros oI the system are at zero. ThereIore the system
rejects the signals at zero Irequency and allows Ior higher Irequencies.Series capacitor and the
4
parallel inductor in Fig 1.2 introduces the zeros at 0 Irequeny which are the required zeros to
realize the highpass characteristic modelled as Iollows:

T(s) (a
2
s
2
) / (s
2
(w
0
/ Q)s w
0
2
)





Fig 1.3. Realization oI a second Fig 1.4. Frequency Response oI a
order Highpass Filter second order HP Iilter


Bandpass Filter is observed when the zeros oI the system is placed beIore and aIter the
slelcted Irequency band to be allowed. In the Iollowing realization Ior a bandpass Iilter using
an RLC conIiguration one oI the zeros is placed at 0 Irequency by the parallel inductor while
the other zero is placed at inIinity by the parallel capacitor. Both oI these zeros pushes the
circuit to rejection Irom the center Irequency (w
0
), at which the circuit is at resonance, to zero
and inIinity. The quality Iactor (Q) oI a bandpass Iilter can be stataed as a criteria that
determines the steepness oI this change in behaviour. The transIer Iunction oI a bandpass Iilter
can be stated as:

T(s) (a
1
s) / (s
2
(w
0
/ Q)s w
0
2
)




Fig 1.5. Realization oI a second Fig 1.6. Frequency Response oI a
order Bandpass Filter second order BP Filter


Bandstop Filter is observed when the zeros oI the transIer Iunction are placed on jw axis. As a
contrast to bandpass bandstop Iilter starts to allow signals Irom the center Irequency to both
sides. Bandstop Iilters with narrow stopbands are called as notch Iilters which are obtained by
locating zeros oI the transIer Iunction as complex conjugates on the zero pole plane at notch
Irequency (w
n
). At center Irequency (w
0
w
n
) an ideal regular notch Iilter shows no
transmission. The characteristics oI a regular notch Iilter which can also be realized as in Fig
1.7 can be moelled with the Iollowing Iormula:
T(s) a
2
(s
2
w
0
2
) / (s
2
(w
0
/ Q)s w
0
2
)


5






Fig 1.7. Realization oI a second Fig 1.8. Frequency Response oI a
order Notch Filter second orderRegular Notch Filter

II the zeros oI the system are located at w
n
w
0
the Iilter behaves as a highpass notch
Iilter, while vice versa produces a lowpass notch Iilter whose Irequency responses are shown in
Fig 1.9 and Fig1.10 respectively.


Fig 1.9. Frequency Response oI a Fig 1.10. Frequency Response oI a
Highpass Notch Filter Lowpass Notch Filter


2.Determining the Transfer Function

2.1. Approximation Methods

In a typical Iilter design there are multiple ways to construct a transIer Iunction to be
realized on the circuit. Two major methods can be listed to be used in approximating the
transmission characteristics as Butterworth and Chebishew. The methods are modelled Ior
lowpass Iilters but can also be applied on the other characterized Iilters by replacing
components.

2.1.1.Butterworth Filter

In this approximation method zeros oI the tarnsIer Iunction are accepted to be at
inIinity. The magnitude Ior the transIer Iunction oI such kind oI a Iilter with an order oI N is
modelled to be

,T(jw), 1/ (1 c
2
(w/w
p
)
2N
)
0.5
c (10
Amax/10
-1 )
0.5

w
p
pass band edge Irequency
6
while the ripple Iactor c is calculated Irom the maximum deviaton in the passband region
(Amax) as above.

Since c` Iirst 2N-1 derivative are zero Ior Irequencies closer to zero Butterworth Iilters
tend to be Ilat Ior passbands. Also the Iact that zeros oI those Iilters are at inIinity drives the
Irequency response oI the system to decrease with a relatively smaller slope. ThereIore
Butterworth Iilters are required to be at higher orders in order to decrease the transition band
and make the Iilter more ideal.

Once the c is determined it is required to Iind the minimum Iilter order N needed Irom
the Iunction:
A(ws) -20 log|1/ (1 c
2
(ws/wp)
2N
|
T(s) (K.w0
N
) /(s-p1) (s-p2).(s-pN)
ws stop band edge Irequency
KDC gain

Finally, Irom the general transIer Iunction the poles Ior the Iilter`s transIer Iunction are chosen
on circle with a radius oI w0 on s plane, to be placed in the transIer Iunction above to construct
the approximated transIer Iunction.

2.1.2.Chebishew Filter

When the magnitude oI the transIer Iunctions Ior Chebishew Filters are observed it is
seen that



the pass band oI the transIer Iunction exhibits ripples and decreases in the stop band. Also it
approximates the ideal, sharp decrease in the stop band which can also be observed in the Fig
2.1.












Fig 2.1.1. Butterworth vs. Chebishew Filters

In order to determine the transIer Iunction oI the Iilter ripple Iactor should be extracted
Irom gain Iunction according to
c (10
Amax/10
-1 )
0.5





7
Inserting that c value to A(w) Iunction the minimum order oI the Iilter N satisIying A(ws)
_Amin is derived while Amin is a speciIied value Ior the minimum ripple gain. Once c and N
are known the poles can be calculated Irom


and inserted into the Iollowing transIer Iunction such as:

T(s) (K.wp
N
) / c 2
N-1
(s-p1) (s-p2).(s-pN)

2.1.3 Other Filter Types

Besides these Iilters there are also Chebishev type 2 Iilters with zeros at Iinite distances
which shows less ripple in the pass band region, Cauer (elliptic) Iilters that distributes the poles
oI the system on an elliptic shape on s plane that leads the response oI the Iunction to show
more ripples than that oI Chebishev with an advantage oI very steep transition capability,
Bessel Filters with maximally linear phase responses and Gaussian Filters with minimum
possible group delay property giving the advantage oI less overshooting are available.

2.2 Transfer Function of the Second Order Notch Filter

In order to determine the notch Iilter characteristics zeros oI the Iunction are given to be
complex conjugate oI each other, on the jw axis and equal to center Irequency w
0
. When the
given speciIications oI w
0
as 10 MHz and quality Iactor (Q) oI 5 with unity DC gain are
considered to be


p1, p2 (- 2a* 10`7/ 2*5) + j 2a* 10`7 (1-(1/ (4*25))
0.5

(-2a*10`6) + j (0.6a*10`7)

z1 -z2 jw
0
j2a* 10`7
yielding a transIer Iunction oI

T(s) a
2
(s
2
w
0
2
) / (s
2
(w
0
/ Q)s w
0
2
)
(s
2
3.948*10`15 ) / (s
2
(1.26*10`7)s 6.283*10`7)

Wo/Qw2-w12a*10`7 / 5 3 db Irequencies oI w1 9 MHz w2 11 MHz


3. Topology Selection

3.1. Alternative Topologies: Two-Integrator-Loop Biquadratic Circuits

The main idea underlying the Two-Integrator-Loop Biquads is to conIigure Miller integrator
circuits in a conIiguration in which the weighted sum oI the intermediate step results produce
the desired transIer Iunction. As it also can be seen Irom Fig 3.1.1 the output oI the Iirst
integrator displays a band pass characteristic while the output oI the second integrator
displays a low pass one. In theory, adding negative oI the last output and the second output
8
which passed through a system with a 1/Q gain onto the original Vi will produce the high pass
characteristic required.

Fig 3.1.1 Block Diagram oI the Two-Integrator-Loop Biquad

3.1.1 Kerwin-Heulsman-Newcomb (KHN) Biquad

In a KHN, the two-integrator-loop biquadratic circuits are realized by employing Miller
integrators with Rc 1/w0 Ior integrator boxes and a summer op-amp conIiguration that can
evaluate its inputs with negative and positive weights Ior the summing Iunction, in the
conIiguration with a transIer Iunction as Iollows:



Fig 3.1.1.1. Implementation oI a KHN circuit Fig 3.1.1.2. Summing circuit Ior KHN

3.1.2. Tow-Thomas Biquad

Instead oI an extra op-amp used Ior the summer ampliIier that can evaluate both negative and
positive inputs in KHN biquad the negative component is produced via an inverter and
summed over a Ieedback in Tow-Thomas conIiguration in a more economic Iashion.
9

Fig 3.1.2.1 Implementation oI a Tow Thomas Biquad

Also the existence oI the virtual ground at the input oI each op-amp provides the possibility oI
giving input signal to all op-amps. But the disadvantage oI this conIiguration to KHN is the
lack oI a high pass output. A Ieedback net is required to obtain all Iilter characteristics. Once
the net is constructed the transIer Iunction oI the system will be as Iollows:




3.2. Selected Topology

3.2.1. RLC Resonator

According to the points that the input signal is given to the RLC system and output is
measured the RLC resonator shows diIIerent Iilter characteristics. In order to obtain a notch
Iilter input signal is given to LC tank circuit which is the reason oI observing zero
transmission at resonance Irequency oI w0, as the characteristic oI a notch Iilter, and output is
measured over the parallel resistor.









Fig 3.2.1.2. Notch Filter by Using RLC conIiguration
Fig 3.2.1.2. Notch Filter by Using RLC


3.2.2. RLC resonator with Antoniou Inductance-Simulation Circuit




Fig 3.2.1.1. RLC Resonator
10
Inductor component oI an RLC resonator can be used as passive or modeled with active
components. In our selected topology the inductor is modeled with an Antoniou inductance-
simulation circuit (Fig 3.2.2.1) which is composed oI op-amps and RC components.


Fig 3.2.2.1. Antoniou Inductance-Simulation Circuit

In the analysis oI this circuit op-amps are considered to be ideal with inIinite input and zero
output impedances. Then a virtual short circuit is observed between the inputs oI the op-amps.
According to Ilow oI the current within the system it is observed that the input impedance oI
an Antoniou inductance-simulation circuit changes with Irequency, showing the behavior oI
an inductor.


Replacing the inductor in RLC in Fig 3.2.1.2. with op-amp RC resonators we obtain the
conIiguration in Fig 3.2.2.2. which has a transIer Iunction as:


When the general notch Iilter Iunction given in section 1 is considered w0 and Q Iactor can be
extracted Irom the Iunction above as:



In our design in the name oI simplicity a common value is assigned Ior 5 R values while the
same is done Ior 2 C values, too. This act simpliIied the above Iunctions to

11


Fig 3.2.2.2 RLC resonator with Antoniou Inductance-Simulation Circuit

Employing such a conIiguration to simulate the inductor had a cost in the quality Iactor oI the
circuit. II the circuit was built up with a passive L, quality Iactor would be much more
signiIicant. But the required space Ior such an inductor would be quite large, too. Also it
would not tolerate the non-idealities oI the real op-amps that are to be used. I this
conIiguration the inductor value can be said to be more under control.

4. Schematic Design and Schematic Simulations

4.1. Design with Ideal Op-Amps

BeIore using the previously designed real op-amp, it is decided to use an ideal op-amp in the
RLC resonator with Antoniou inductance-simulation circuit to determine what specs should
the new real op-amp to be used in the circuit should have and veriIy whether hand
calculations will satisIy the goals or not . ThereIore the op-amp is simulated with a voltage
controlled voltage source (vcvs) ( Fig 4.1.1) Irom analog library whose gain can be adjusted
and whose gain bandwidth product in unlimited.


Fig 4.1.1. Filter Schematic with Ideal Op-Amps
12
The gain oI the vcvs is swept Irom 50 to 150 V/V. The parametrical sweep results in Fig 4.1.2
gave the idea to redesign the previous op-amp with a gain oI at least 100 V/V.


Fig 4.1.2. Parametric Sweep oI Vcvs Gain From 50 to 150 V/V

According to the Iormulas in section 3.2.2., when R R1R2 R3 R3 R510kO and
CC4C6:

w0 2a * 10`7 1/RC 1/ (10`4) C C1.59pF

In order to obtain a quality Iactor oI 5 R6 should be at least:

QR6/R5R6/10kO R650kO

The circuit composed oI these calculated values and ideal op-amp with 300 gain in the Fig
4.1.1 conIiguration generated the ac response in Fig 4.1.3.




Fig 4.1.3. Ac Response oI the Circuit n Fig 4.1.1.
13
4.2. Redesign of Previous Op-amp

In the previous design gain oI the op-amp was 98 db with a gain-bandwidth product (GB) oI
10.8 MHz. In this Iilter design it was required to obtain a higher gain bandwidth since the
Iilter is expected to also work Ior the notch Irequency oI 10 MHz. ThereIore the gain oI the
op-amp is reduced in order to increase the GB. To achieve this the widths oI MN0, MN1,
MN2 and MN3 is increased to 4.5u while the overdrive voltage on these transistor decreased
leading to an increase in both the transconductance oI gm2, gm3 and the transition Irequency
(It).The ac response and phase margin oI the resulting circuit in Fig 4.2.2. is as Iollows:




Fig 4.1.1. Ac Response and Phase Margin oI Op-amp in Fig 4.2.2.


Fig 4.2.2. First Redesigned Op-amp
14
When this op-amp is replaced with the ideal op-amp in Fig 4.1.1, the distorted ac response in
Fig 4.2.3. is observed.


Fig 4.2.3. Ac Response and Phase Margin oI the Filter with First Redesigned op-amp


The decrease oI w0 Irom 9.68 to 5.85MHz gave the impression that the output capacitance oI
the real op-amp was too high and was pushing w0 to decrease according to the Iormula oI
w01/RC. ThereIore the compensation capacitor and resistance are removed Irom the circuit
and an ac response and phase margin graphic in Fig 4.2.4 is observed.



Fig.4.2.3. The Schematic oI Filter with Real Op-amp


15




Fig 4.2.4. Ac response and Phase Margin Graphic oI Second Redesigned Op-amp


4.3. Schematic Results

When the second redesigned op-amp is employed in the Iilter schematic optimum notch Iilter
with the Iollowing ac response is observed:



Fig 4.3.1. Ac Response oI Real Op-Amp Schematic


In the transient measurements input signal is chosen to 1 mV. And at 10 MHz notch
Irequency a decrease Irom 1.21312 mV to 1.21231mV on output signal is observed.
16


Fig. 4.3.2. Transient Response oI Real Op-Amp Schematic at 1MHz


Fig. 4.3.3. Transient Response oI Real Op-Amp Schematic at 10 MHz



5. Layout Design and Post-Layout Simulations

5.1. Op-amp Layout

AIter redesigning the op-amp a more eIIicient layout was designed than that oI the previous
one. Since there were MP8 and MP16 with 37u width in the previous design those pmos
transistors were generating signiIicant parasitics. In this version their width are reduced to 11u
and on the overall the design became more compact.
17


Fig 5.1.1. Layout Design oI Second Redesigned Op-Amp

5.2. Post-Layout Simulation Results of Op-Amp Layout

The extracted version oI the op-amp was symbolized and replaced with the schematic
symbols in the circuit in Fig 4.2.3. Due to compact parasitic capacitances were too much but
their sizes were reasonably small. ThereIore results Ior this simulation did not diIIer Irom the
simulation done with schematic symbols. There was a slight diIIerence in the notch Irequency
which is reasoned to be the eIIect oI the additional extracted parasitic capacitances.



Fig 5.2.1. Ac Response oI Real Op-Amp Fig 5.2.2. Number oI overall
Post-Layout Simulation capacitances
18


Fig 5.2.4. Transient Response oI Real Fig. 5.2.5. Transient Response oI Real
Op-Amp Post-Layout Simulation Op-Amp Post-Layout Simulation
at 1MHz at 10 MHz

5.3. Overall Filter Layout

Op-Amp layout was extended with the other resistors and capacitor in the Ieedback network
and RLC resonator. The Iirst version oI the system lacked the 80k resistor on the right side oI
the layout design in Fig 5.3.1. AIter the problems in the post-layout simulations the layout
conIiguration is somewhat revised and Iinal version oI Fig 5.3.1. is Iormed.



Fig 5.3.1. Final Version oI Filter`s Overall Layout
19

5.4. Post-Layout Simulations of Overall Layout

Post-layout simulation oI the schematic seen in Fig 4.2.3 generated the red plot in Fig 5.4.1.
The problem with this plot was the peak observed beIore and the slow rise aIter the notch
Irequency. By decreasing the resistance R6 it was possible to decrease the decline oI the low
pass side line oI the notch and thereIore observe a smaller peak beIore the notch cavity with a
cost oI lower quality Iactor. Even though this was decreasing the peak, it was not a real
solution to the slow rise to the right side.


Fig 5.4.1. Ac Response oI the First Layout with R645k, R637k vs. Second Layout


Fig 5.4.2. Second Version oI Filter
20
Since the circuit was working Iinely Ior the symbol oI op-amp Irom the extracted version, the
reason Ior the peak beIore the notch cavity could be the parasitic capacitance Iormed parallel
to R6 which was making the conIiguration oI the regular notch Iilter similar to a low pass
notch Iilter. There was a long line oI Met3 between R6 and gnd in the layout. There was a
minor improvement when this line is optimized and the width oI the resistance thereIore its
capacitance is reduced. This Iact was supporting the reasoning. ThereIore in order to
compensate Ior this capacitance eIIect a resistance oI 80 k was connected between R5 and
ground as in the Fig 5.4.2. By doing this the zeros shiIted to values larger than w0 by the
parasitic capacitances were drawn back to their original locations on the s plane. The eIIect oI
80 k was considerable on the slow increase on high pass side and the peak beIore the notch
cavity but it was also decreasing the gain to 0.9. Since quality Iactor was adequate, notch
Irequency and attenuation was reasonable this decrease in gain was Iound tolerable and was
decided to be ampliIied iI it is necessary in the application.



Fig 5.4.3. Ac Response oI the Second Layout Fig 5.4.4. Number oI
Overall Parasitics



Fig 5.4.5. Ac response oI the Second Fig 5.4.6. Ac response oI the Second
Layout (in dB`s) Layout (in mV`s)


21



Fig 5.4.7. Transient Response oI the Fig 5.4.8. Transient Response oI the
Second Layout at 1MHz Second Layout at 10 MHz


Table 1 Change in Attenuation, Notch Irequency and Quality Factor Throughout the
Process

6. Conclusion

Goal oI this project was to design a second order active notch Iilter with a notch Irequency oI
10MHz and with a quality Iactor oI 5 by using 0.35u technology.

In each step oI the project achieved values Ior the required speciIications changed as it is
depicted in Table 1.Both the Iormulas and the Iirst simulated schematic were based on the
ideal op-amp assumptions. They were modeled to be zero output impedance, inIinite input
impedance and bandwidth. But clearly the output impedance and bandwidth oI the real op-
amp was limited. And the resistance introduced by the op-amp was reducing the w0. In order
to compensate Ior this, it was required to increase the C capacitances. This newly introduced
output impedance was reIlected over the Ieedback as an increase in quality Iactor. ThereIore
the 3 db points oI both sides in ac response are expected to get closer and the attenuation
magnitude determined by the merging point oI these lines decrease as a diIIerence that non-
ideal op-amp brought into scene.

In redesigning the previous op-amp process it was required to provide an op-amp with a gain
larger than 40 db. By removing the compensation resistance and capacitance, a wider
bandwidth and a smaller phase margin Ior the new op-amp are observed. Even though the
load capacitance is removed, the capacitance the op-amp sees at its output is non-zero,
generating more phase margin than it is calculated on an isolated op-amp. The distortion
amount is an indicator oI the capacitive eIIect at the output and high phase margin.
Attenuation (dB) Notch Frequency (MHz) Quality Factor (Q)
Ideal Op-amp -29.5 9.68 5.02
Real Op-Amp
Schematic
-22.76 10.35 5.72
Real Op-Amp Post-
Layout
-20.6 9.9 6.16
Overall Filter Post-
Layout
-15.5 9.97 4.37
22

The parasitic capacitances generated in the C-only extraction oI the op-amp decreased w0.
When the passive resistances oI 10k and 45 k included in the layout these parasitic
capacitances increased signiIicantly, leading to a deIormation in the simulation results. Low
pass notch-like graphics were indicating zero values larger than w0. These zeros are drawn
closer to origin on the s plane by decreasing the signiIicance oI the alternative path by
employing the R11 in Fig 5.4.2.

Throughout this project we improved ourselves on Iilter design approximations and
topologies, the concept oI pole-zero locating on a real-time system, the diIIerences between
ideal op-amp assumptions and non ideal characteristics oI a real op-amp and dealt with design
challenges.