METU NORTHERN CYPRUS CAMPUS

Logic Design EEE248/CNG 232 LABORATORIES

Spring 2013

METU Northern Cyprus Campus

EEE 248/CNG 232

Spring 2013

Regulations:
Students are not permitted to perform an experiment without doing the preliminary work before coming to the laboratory. It is not allowed to do the preliminary work at the laboratory during the experiment. Students who do not have complete preliminary work with them at the beginning of the laboratory session cannot attend the lab. No make-up is given in that case No food or drink in the lab. There may be a quiz before each laboratory session, which will start promptly at the beginning of the lab. Students who miss the quiz cannot attend the lab. No make-up is given in that case. There wont be any extensions in the quiz time for latecomers. Therefore, students have to be at the lab on time for the quiz. Only the following excuses are valid for taking a lab make-up: 1. Health Make-up: Having a health report from METU Medical Center. 2. Exam Make-up: Having an exam coinciding with the time of the laboratory session. The student needs to notify the instructor in advance if this is the case. Experiments will be done individually. The lab instructor will inform you of any part that you can do in groups. Preliminary works should be submitted before the lab session starts. Students who do not bring a hard copy of their preliminary work cannot attend the lab and will receive zero credit for the session. Cheating is not tolerated in this laboratory. Plagiarism is a form of cheating as is using someone elses written word with minor changes and no attribution. If you are caught cheating, you will, at the very least, receive a zero for the whole experiment. Students who miss the lab 3 times without a legal excuse get zero as the laboratory portion of the course grade. Those who fail to get a satisfactory score from the laboratory portion may fail the class. This score will be finalized later, but is expected to be 70%.

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EXPERIMENT #1 INTRODUCTION TO DIGITAL DESIGN ENTRY, SIMULATION, and IMPLEMENTATION

1.1 OBJECTIVE The purpose of the first laboratory exercise is getting familiar with Quartus II Project Navigator, DE0 Demo Board, and the associated toolset to facilitate digital design. The student will complete a step-bystep tutorial in the first part of the experiment to implement complex gates (XOR, NAND, NOR) on a Cyclone III FPGA (Field Programmable Gate Array) using schematic entry, simulation, and FPGA programming tools. VHDL (Very High Level Integrated Circuit Hardware Description Language) will be utilized in the second part of the experiment to implement a 1-bit full adder designed in the preliminary work. The relationship between minority-voter, even-detector and full-adder logic will also be studied. 1.2 PRELIMINARY WORK 1.2.1 Read through Section 1.3 to acquire general familiarity with VHDL. This is a very brief summary, and good references are available in the library if you need further information. Tables 1.2.1(a-c) depict the truth tables corresponding to (a) 2-input XOR, (b) 2-input NAND, (c) 2-input NOR logic gates. Derive a Boolean expression for each, and draw the corresponding logic schematic using AND, OR, and Inverter gates. Table 1.2.1. (a) 2-input XOR Truth Table A 0 0 1 1 1.2.3 B 0 1 0 1 Z 0 1 1 0 (b) 2-input NAND Truth Table A 0 0 1 1 B 0 1 0 1 Z 1 1 1 0 (c) 2-input NOR Truth Table A 0 0 1 1 B 0 1 0 1 Z 1 0 0 0

1.2.2

Tables 1.2.2(a-b) provide the truth tables corresponding to a 3-input minority-voter and 3-input even-detector. Table 1.2.2. (a) 3-input Minority-voter a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 MV-out 1 1 1 0 1 0 0 0 (b) 3-input Even-detector a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 EV-out 1 0 0 1 0 1 1 0

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i) ii)

iii) iv)

Explain briefly in words the function of each logic block represented by the truth tables (a) and (b) i.e. describe the condition for which the output becomes 1 for each function. Using AND, OR, and inverter gates, derive a Boolean expression for each of the two outputs as a function of the inputs: MV-out (a, b, c) = ? EV-out (a, b, c) = ? Draw the logic schematics corresponding to your answers in (ii) Given the logic XOR function in 1.2.2, redesign the EV-out output using XOR gates only.

1.2.4

A full adder has three inputs, a, b, cin (carry-in), and two output cout (carry-out), sum. As the name implies the 2-bit output represents the result from computing binary addition of the three inputs. Based on this, complete the blanks marked with (fill in) in the VHDL code, provided below, to implement the full adder:
------------------------------------------ Company: METU-NCC -- Engineer: Your name goes here --- Create Date: 27/02/2012 -- Design Name: Full Adder -- Module Name: fulladd - Logicfunc -- Project Name: Lab 1 -- Target Devices: Cyclone III EP3C16F484C -- Description: Full adder VHDL design --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: -----------------------------------------Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladd is Port ( cin (fill in) (fill in) (fill in) (fill in) end fulladd;

: : : : :

in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; out STD_LOGIC; out STD_LOGIC);

architecture LogicFunc of fulladd is begin sum <= (fill in) ; cout <= (a AND b) OR (fill in) ; end LogicFunc;

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1.3 Introduction to VHDL VHDL is an IEEE-standard high level language to describe hardware. It has broad capabilities. For example, the same hardware can be described using structural, behavioral, and data flow (Register Transfer Language or RTL) approaches. A VHDL design may be in a single block, or in several blocks. Each block in VHDL is called an entity. The entity describes the interface and the operation of the block. The interface description is analogous to a pin description in a data book, specifying the inputs and outputs to the block. The following is an entity declaration example:
entity latch is port (s, r: in bit; q, nq: out bit); end latch; -- Double dashes precede comments -- Use any word for the entity name -- We use the word latch here --

The first line indicates a definition of a new entity, named latch. The last line marks the end of the definition. The lines in between, called the port clause, describe the interface to the design. The port clause contains a list of interface declarations. Each interface declaration defines one or more signals that are inputs or outputs to the design. Each interface declaration contains a list of names, a mode, and a type. In the first interface declaration of this example, two input signals are defined, s and r. The list to the left of the colon contains the names of the signals, and to the right of the colon is the mode and type of the signals. The mode specifies whether this is an input (in), output (out), or both (inout). The type specifies what kind of values the signal can have. The signals s and r are of mode in (inputs) and type bit. Next the signals q and nq are defined to be of the mode out (outputs) and of the type bit (binary). Each interface declaration is followed by a semicolon, except the last one, and the entire port clause has a semicolon at the end. The signals in the given example are defined to be of the type bit. The type bit is a predefined type that can have two values represented by '0' and '1'. This type is used to represent two level logic signals. There are other popular types like std_logic, which can acquire additional values like x for unknown, u for uninitialized, z for high impedance, h for weak high, l for weak low, etc. The operation of the design is defined by the architecture declaration. The following is an example of an architecture declaration for the latch entity. There can be more than one description in a design file, we choose which description to run when we configure the simulator; this is very useful since we can begin with a crude behavioral or algorithmic description, simulate a complete system and then go through a design replacing each architecture with a more physical implementation, with more accurate time delays etc., the big advantage of VHDL is that we can simulate, at each stage of the design process, keeping the older representations aid our documentation of the design and allow easier changes.
architecture dataflow of latch is begin q <= r nor nq; nq <= s nor q; end dataflow; -----The word meaning, Note the operator function dataflow has no special it is not a keyword of VHDL special signal assignment <= and the predefined 'nor'

The first line of the declaration indicates that this is a definition of a new architecture called dataflow and that it belongs to the entity named latch. Hence, this architecture describes the operation of the latch entity. The lines in between begin and end describe the latch's operation. This example uses the data flow approach. 1.3.1 Behavioral Description: The behavioral approach to modeling hardware components is different from structural and dataflow methods in that it does not necessarily, in any way, reflect how the design is implemented. It is basically the black box approach to modeling. It accurately models what happens on the inputs and METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 5

outputs of the black box, but what is inside the box (how it works) is irrelevant. The behavioral description is usually used in two ways in VHDL. First, it can be used to model complex components that would be tedious to model using the other methods. Second, the behavioral capabilities of VHDL can be more powerful and is more convenient for some designs. In this case the behavioral description will likely imply some structure of the implementation. Also in the early part of the design process you can use behavioral models to quickly evaluate an algorithm and simulate it by passing real data through it. Behavioral descriptions are supported with the process statement. The process statement can appear in the body of an architecture declaration just as the signal assignment statement does. The contents of the process statement can include sequential statements like those found in software programming languages. These statements are used to compute the outputs of the process from its inputs. Sequential statements are often more powerful, but sometimes have no direct correspondence to a hardware implementation. The process statement can also contain signal assignments in order to specify the outputs of the process. A group of processes will be executed concurrently since the process is a concurrent statement, it usually contains sequential statements. We can also group a block of concurrent statements together and specify when they are to be executed. In the example given below, the process statement is trivial and would not normally be used as a process statement. However, it allows us to examine a process statement without learning any sequential statements first.
compute_xor: process (b, c) begin a <= b xor c; end process; -----we can name processes if we wish (its optional) note we list the signals that the process depends on. The process will only execute when a change occurs on b or c (or at power on) we call (b,c) the sensitivity list

This example process contains one statement, the signal assignment. Unlike signal assignments that appear outside the process statement, this signal assignment is only evaluated when events occur on the signals in the process' sensitivity list, regardless of which signals appear on the right side of the <= operators. This means it is critical to make sure the proper signals are in the sensitivity list. The statements in the body of the process are performed (or executed) in order from first to last. When the last statement is executed the process finishes and is said to be suspended. When an event occurs on a signal in the sensitivity list, the process is said to be resumed and the statements will be executed from top to bottom again. Each process is executed once during the beginning of a simulation to determine the initial values of its outputs. 1.4 EXPERIMENTAL WORK 1.4.1 Experimental Setup

Verify to make sure your workbench has all of the following items: - A Personal Computer (PC) with Altera Quartus II ISE 10.1 Project Navigator - DEO Demo Board with Cyclone III EP3C16F484C6 FPGA installed on a card with 10 input toggle switches, three push buttons, and four 7-Segment LED displays among other components. - A USB cable connected between the demo board and the PC using USB interface 1.4.2 XOR, NAND, NOR Schematic Entry, Simulation, and Implementation

1.4.2.1 Launch Quartus II Project Navigator 1.4.2.2 Create a New project which will target the FPGA device on the DE0 Demo Board. To create a new project: METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 6

i)

Select File > New Project Wizard... select New Quartus II Project. The New Project Wizard appears. ii) Look at the Introduction and click Next. iii) Type lab1xor in the Project Name field. Enter or browse to a location (directory path) for the new project. You can select the directory name as <YourInitials>_lab1. click Next. iv) You are given the chance to add existing design files to the project (if any). As you do not have any files to add click Next. v) Family and Device settings window appears. Select Cyclone III as the family first. You will see a list of available devices in the list table. Select EP3C16F484C6 and click Next. vi) The user can specify any third-party tools that should be used. A commonly used term for CAD software for electronic circuits is EDA tools, where the acronym stands for Electronic Design Automation. This term is used in Quartus III messages that refer to third-party tools, which are the tools developed and marketed by companies other than Altera. Since we will rely solely on Quartus III tools, we will not choose any other tools. Press Next. vii) A summary of the chosen settings. Press Finish, which returns to the main Quartus III window, but with lab1xor specied as the new project, in the display title bar. viii) The Quartus III Graphic Editor can be used to specify a circuit in the form of a block diagram. Select File > New and choose Block Diagram/Schematic File, and click OK. This opens the Graphic Editor window. The rst step is to specify a name for the le that will be created. Select File > Save As. In the box labeled File name type lab1xor, to match the name given to the project, which was specied when the project was created. Put a checkmark in the box Add le to current project. Click Save, which puts the le into the directory <YourInitials>_lab1 and leads back to the Graphic Editor window. 1.4.2.3 Enter the schematic: i) Double-click on the blank space in the Graphic Editor window, or click on the icon in the toolbar that looks like an AND gate. A pop-up window appears. Expand the hierarchy in the Libraries box.

ii) First expand libraries, and then expand the library primitives, followed by expanding the library logic which contains the logic gates. iii) Place the and2, or2, and not (inverter) gates as many times as needed for the xor design from the preliminary work Section 1.2.2. iv) Input and Output Symbols, Use the same procedure as for importing the gates, but choose the port symbols from the library primitives/pin. v) Assign names to the input and output symbols as follows. Make sure nothing is selected by clicking on an empty spot in the Graphic Editor window. Point to the word pin_name on the top input symbol and double-click the mouse. A dialog box will appear. Type the pin name, lets say x1, and click OK. Similarly, assign the name x2 to the other input and f to the output pin. Alternatively, it is possible to change the name of an element by selecting it rst, and then double-clicking on the name and typing a new one directly. vi) Finally Connecting Nodes with Wires. Click on the icon in the toolbar to activate the Orthogonal Node Tool. Position the mouse pointer over the right edge of one of your input pins. Click and hold the mouse button and drag the mouse to the right until the drawn line reaches the pinstub on the top input of one of the gates. METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 7

1.4.2.4 Compiling the design: i) Run the Compiler by selecting Processing > Start Compilation, or by clicking on the toolbar icon that looks like a purple triangle ii) Successful (or unsuccessful) compilation is indicated in a pop-up box. Acknowledge it by clicking OK. 1.4.2.5 Pin Assignment: i) ii) Pin assignments are made by using the Pin Planner. Select Assignments > Pin Planner to start. Select x1 as the rst pin to be assigned. To do this, double-click on the box in the column labeled Location to the right of x1 entry. A drop-down menu appears. Scroll down and select PIN_J6. Instead of scrolling down the menu to nd the desired pin, you can just type the name of the pin (J6) in the Location box. Use the same procedure to assign input x2 to pin H5 and output f to pin J1 To save and close the assignments made, choose File > close. Recompile the circuit, so that it will be compiled with the correct pin assignments. Run the Compiler by selecting Processing > Start Compilation.

iii) iv) v)

Table 1.4.1. DE0 Test Box Input Switch Cyclone III FPGA pin mapping

Table 1.4.2. DE0 Test Box Input Button Cyclone III FPGA pin mapping

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Table 1.4.3. DE0 Test Box HEX Output Cyclone III FPGA pin mapping for HEX0

Table 1.4.4. DE0 Test Box Output LED Cyclone III FPGA pin mapping

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1.4.2.6 Simulation: i) Open the Waveform Editor window by selecting File > New. ii) The Associated Source page shows that you are associating the test bench waveform with the source file xorgate. Click Next. iii) The Waveform Editor window opens. Save the le under the name lab1xor.vwf; note that this changes the name in the displayed window. iv) Set the desired simulation to run from 0 to 500 ns by selecting Edit > End Time and entering 500 ns in the dialog box that pops up. Selecting View > Fit in Window displays the entire simulation range of 0 to 500 ns in the window. You may wish to resize the window to its maximum size. v) Next, we want to include the input and output nodes of the circuit to be simulated. Click Edit > Insert > Insert Node or Bus. It is possible to type the name of a signal (pin) into the Name box, but it is easier to click on the button labeled Node Finder. The Node Finder utility has a lter used to indicate what type of nodes are to be found. Since we are interested in input and output pins, set the lter to Pins: all. Click the List button to nd the input and output nodes vi) Click on the x1 signal in the Nodes Found box, and then click the > sign to add it to the Selected Nodes box on the right side of the window. Do the same for x2 and f. Click OK to close the Node Finder window, and then click OK in the Insert Node or Bus window. This leaves a fully displayed Waveform Editor window. (If you did not select the nodes in the same order as explained above, it is possible to rearrange them. To move a waveform up or down in the Waveform Editor window, click on the node name (in the Name column) and release the mouse button. The waveform is now highlighted to show the selection. Click again on the waveform and drag it up or down in the Waveform Editor). vii) We will now specify the logic values to be used for the input signals x1 and x2 during simulation. The logic values at the output f will be generated automatically by the simulator. To make it easy to draw the desired waveforms, the Waveform Editor displays (by default) vertical guidelines and provides a drawing feature that snaps on these lines (which can otherwise be invoked by choosing View > Snap to Grid). viii) We will use four 100-ns time intervals to apply the four test vectors. We can generate the desired input waveforms as follows. o Click on the waveform name for the x1 node. Once a waveform is selected, the editing commands in the Waveform Editor can be used to draw the desired waveforms. (Commands are available for setting a selected signal to 0, 1, unknown (X), high impedance (Z), dont care (DC), inverting its existing value (INV), or dening a clock waveform). Each command can be activated by using the Edit > Value command, or via the toolbar for the Waveform Editor. The Edit menu can also be opened by right-clicking on a waveform name. ix) Set x1 to 0 in the time interval 0 to 100 ns, which is probably already set by default. Next, set x1 to 1 in the time interval 100 to 200 ns. Do this by pressing the mouse at the start of the interval and dragging it to its end, which highlights the selected interval, and choosing the logic value 1 in the toolbar. Next, set x1 to 0 in the time interval 200 to 300 ns. Next, set x1 to 1 in the interval 300 to 400 ns. x) Now, Make x2 = 1 from 200 to 400 ns. Observe that the output f is displayed as having an unknown value at this time, which is indicated by a hashed pattern; its value will be determined during simulation. Save the le. 1.4.2.6.1 i) Functional Simulation: To perform the functional simulation, select Assignments > Settings to open the Settings window. On the left side of this window click on Simulator Settings, choose Functional as EEE 248/CNG 232 Spring 2013 10

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the simulation mode, and click OK. The Quartus II simulator takes the inputs and generates the outputs dened in the lab1xor.vwf le. ii) Before running the functional simulation it is necessary to create the required netlist, which is done by selecting Processing > Generate Functional Simulation Netlist. A simulation run is started by Processing > Start Simulation, or by using the icon . At the end of the simulation, Quartus II software indicates its successful completion and displays a Simulation Report. If your report window does not show the entire simulation time range, click on the report window to select it and choose View > Fit in Window. 1.4.2.6.2 i) Timing Simulation:

Having ascertained that the designed circuit is functionally correct, we should now perform the timing simulation to see how it will behave when it is actually implemented in the chosen FPGA device. ii) Select Assignments > Settings > Simulator Settings, choose Timing as the simulation mode, and click OK. iii) Run the simulator, which should produce the resulting waveforms. 1.4.2.7 Implement the design: The programming and conguration task is performed as follows: i) Flip the RUN/PROG switch into the RUN position. ii) Select Tools > Programmer. Here it is necessary to specify the programming hardware and the mode that should be used. iii) If not already chosen by default, select JTAG in the Mode box. Also, if the USB-Blaster is not chosen by default, press the Hardware Setup... button and select the USB-Blaster in the window that pops up. iv) Observe that the conguration le lab1xor.sof is listed in the window. v) If the le is not already listed, then click Add File and select it. vi) Not that the device selected is EP3C16F484, which is the FPGA device used on the DE0 board. vii) Click on the Program/Congure check box viii) Now, press Start in the window. This loads the file on the processor. 1.4.2.8 Validate your design: i) The final step is the hardware validation to make sure the functionality of the FPGA chip is as you expected based on your design. ii) Use the switches and LEDs you have programmed in step 1.4.2.5 to test all possible combinations of inputs. iii) Once you are convinced your design works, go back, and add 2-input NOR and NAND designs to your schematic. You can use the same inputs or define completely different inputs (switches). However, ensure your outputs (LEDs) are distinct for each of XOR, NAND, and NOR. Demonstrate the hardware functionality on the DE0 board to your lab instructor. 1.4.3 1-Bit Full Adder VHDL Design, Simulation, and Implementation

1.4.3.1 To create a new project: i) Select File > New Project Wizard... The New Project Wizard appears. ii) Type lab1add in the Project Name field. Enter or browse to a location (directory path) for the new project. iii) You are given the chance to add existing design files to the project (if any). As you do not have any files to add click Next. METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 11

iv) Family and Device settings window appears. Select Cyclone III as the family first. You will see a list of available devices in the list table. Select EP3C16F484C6 and click Next. v) The user can specify any third-party tools that should be used. A commonly used term for CAD software for electronic circuits is EDA tools, where the acronym stands for Electronic Design Automation. This term is used in Quartus III messages that refer to third-party tools, which are the tools developed and marketed by companies other than Altera. Since we will rely solely on Quartus III tools, we will not choose any other tools. Press Next. vi) A summary of the chosen settings. Press Finish, which returns to the main Quartus III window, but with lab1xor specied as the new project, in the display title bar. vii) The Quartus III Graphic Editor can be used to specify a circuit in the form of a block diagram. Select File > New and choose VHDL File, and click OK. This opens the Text Editor window. The rst step is to specify a name for the le that will be created. Select File > Save As. In the box labeled File name type lab1add, to match the name given to the project, which was specied when the project was created. Put a checkmark in the box Add le to current project. Click Save, which puts the le into the project directory and leads back to the Graphic Editor window. 1.4.3.2 Enter the VHDL code: Follow the compilation, simulation, implementation, and validation steps as described in sections 1.4.2.4 - 1.4.2.8. Demonstrate the full adder simulation and hardware validation results to your lab instructor. 1.4.4 Use of Push-Buttons:

If you have completed early, go back to the Full-Adder experiment in 1.4.3, modify the pin assignments based on Table 1.4.2 so that you can control Cin input with a pushbutton instead of the toggle switch. Re-program your device and validate. What do you observe? Demonstrate to your lab instructor for possible potential bonus points if you can explain your observation.

REFERENCES: DE0 Board User Manual, Terasic Technologies Inc. Fundamentals of Digital Logic with VHDL Design, 2nd Edition, Stephen Brown & Zvonko Vranesic, McGraw-Hill Quartus II Introduction Using Schematic Design, ALTERA.

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EXPERIMENT #2 & #3 HIERARCHICAL DESCRIPTION OF COMBINATIONAL LOGIC (ADDERS, DECODERS, ENCODERS, MULTIPLEXERS) WITH MULTIBIT SIGNALS
2.1 OBJECTIVE This laboratory exercise will build on the design entry knowledge acquired in the first lab to design more advanced combinational circuits. 1-bit full adder will be designed in the first part of the experiment using behavioral description in contrast to the design entry method in Lab 1 using logic functions. This will then be extended to a 4-bit adder through hierarchical (structural) VHDL design. In the second part of the experiment, a decoder will be designed to display some letters at the 7-Segment LEDs on DE0 Demo Board. A priority encoder will be implemented next to encode the number of 8 active inputs into a 3-bit binary number using behavioral constructs. Finally, all of the VHDL design modules from the three parts will be integrated into a more complex combinational design with the assumption that output resources (7-Segment LEDs) are limited, and are therefore shared between the adder, HEX decoder, and encoder through multiplexing logic. 2.2 PRELIMINARY WORK 2.2.1. Read through Section 2.3 and 2.4 to learn about some of the VHDL behavioral modeling constructs, and hierarchical schematics with multibit signals. 2.2.2. 4-bit Ripple Carry Adder: Use the symbol in Figure 2.2.1(a) for 1-bit full adder, and indicate how you would interconnect four of such adders in order to build a 4-bit ripple carry adder for which a symbol is provided in Figure 2.2.1(b). a b x(3:0) y(3:0)

cout

cin

cout

cin

a)

sum

b)

s(3:0)

Figure 2.2.1 (a) 1-bit full adder symbol, (b) 4-bit ripple carry adder symbol 2.2.3 Use your answer to 2.2.2 above to fill in the missing portions of the code provided for the 4-bit ripple carry adder in 2.3.4. The missing portions are annotated as (fill in prelab). HEX Decoder: Use combinational logic design principles to design a 7-Segment Display decoding logic such that when a number is entered between 0 and 15, the number will show up in hex representation on the display HEX0. For example, when the user enters 1, two of the vertically aligned 7-Segment Display LEDs should light up. Similarly number 2 should light up five of the LEDs. Please optimize your logic as much as possible to yield the lowest cost i.e. lowest number of input switches, gates, literals, and gate inputs. Input-to-Output delay is not a concern in this application. EEE 248/CNG 232 Spring 2013 13

2.2.4

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Hint: Remember the 7-Segment Display on DE0 board is characterized by 8 independent active low outputs (including the dot in the lower right) that need to be all defined to determine the displayed character, as depicted in Table 2.2.1. Table 2.2.1. Mapping of DE0 HEX0 7-Segment Display to HEX Decoder HEX Value 0 1 2 3 F 2.2.5 2.2.6 A on off on B C D E on on on on on on off off on off on on on off off off on F on off off G off off on DP off off off

on on off

Write a VHDL code to implement the decoder module designed in Section 2.2.4. Priority Encoder: Use combinational logic design principles to design a 8-to-3 priority encoder with an additional valid (V) bit. For example, when the highest priority input is turned ON (1), the three output LEDs should encode 7 in binary, regardless of the values of the other inputs. The valid bit should turn on as long as at least one input is ON. Output should display 0 in binary and V=1, when the lowest priority input is turned ON and no other input is ON. Please optimize your logic as much as possible to yield the lowest cost i.e. lowest number of input switches, gates, literals, and gate inputs. Show your work step by step in your report. Input-toOutput delay is not a concern in this application. Write a VHDL code to implement the encoder module designed in Section 2.2.6. Mode Multiplexer: Design multiplexing logic such that the outputs from the ripple carry adder of 2.2.3, HEX decoder of 2.2.5 and priority encoder of 2.2.7 can share the 7-Segment Display. Introduce a Mode input in order to switch back and forth between the two sets of outputs as indicated in Table 2.2.2. The third (cout) bit of the addition result should map to the DP LED at the bottom right of the display. Table 2.2.2. Operation of 2 display modes Mode 0 1 7-Segment Display Ripple Carry Adder Output Priority Encoder Output

2.2.7 2.2.8

It is sufficient to show the multiplexer symbol in the answer, and label all the inputs and outputs. 2.2.9 Write a VHDL code module to implement the multiplexer designed in Section 2.2.8.

2.2.10 Complete Design: Draw the schematic of the combined logic including the four modules: 4-bit ripple carry adder, HEX decoder, Priority Encoder and the Multiplexer. Each module should be represented using a symbol (box) without showing its internals. However, input and output pins for all four modules as well as interconnections between modules should clearly be shown. Combine all of your modules (decoder, encoder, MUX and the 4-bit adder) to create one single unit, such that: METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 14

One of the MUX inputs should be connected with the output of the adder, The other MUX input should be connected with the output of the encoder, The output of the MUX is connected to the hex decoder, In order to save from using the number of switches, use the same inputs for the adder and the encoder.

2.2.11 Make a copy of all of your VHDL codes and schematics from Preliminary Work. Your Prelim will not be made available to you after you submit it at the beginning of the lab. 2.3 Behavioral VHDL Code 2.3.1 Multibit Signals

A number greater than one is represented in a logic circuit using binary signals on multiple wires. Similarly, a number is represented as a multibit SIGNAL data object in VHDL. For example, a 3bit signal declaration can be done in different ways: SIGNAL A : STD_LOGIC_VECTOR (1 TO 3); SIGNAL D: STD_LOGIC_VECTOR (2 DOWNTO 0); The STD_LOGIC_VECTOR data type represents a linear array of STD_LOGIC data objects. The multibit STD_LOGIC_VECTOR declaration can be used in the same way as the single bit counterpart STD_LOGIC when defining signals within an architecture, or ports within an entity. 2.3.2 VHDL Libraries

VHDL libraries contain commonly used packages of code to make high level hardware description easier. For example std_logic_1164 library, specified during the first few lines of the VHDL code using USE command, defines std_logic data types and a few functions. It is typically included in every VHDL code. std_logic_arith is another library that allows signals to be used in integer arithmetic operations. An extension to this is std_logic_signed library to handle STD_LOGIC_VECTOR values as signed integers. e.g. S <= X+Y; Note, + in this case is used for arithmetic addition, not logic OR operation. S, X, and Y may be multibit signals previously declared using STD_LOGIC_VECTOR. There are few other libraries useful for behavioral modeling, which will not be described for now. 2.3.3 Behavioral Modeling

One of the main reasons VHDL or similar languages are popular for hardware description is the capability of behavioral modeling. Behavioral modeling allows a designer to describe hardware using high level abstractions by focusing on the desired behavior instead of details of the logic to get to that behavior. It is important to recognize that a good digital designer still needs to be very familiar with the logic derivation in order to check if the final hardware solution delivered is optimal. Below is an example of a 1-bit full adder, which takes advantage of the arithmetic libraries to describe an adder at a higher abstraction level than what was done in Lab 1 using logic functions. -- It is important to include below libraries to get behavioral -- modeling capability for arithmetic operations: library IEEE; use IEEE.STD_LOGIC_1164.ALL; METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 15

use IEEE.STD_LOGIC_SIGNED.ALL; -- Entity declaration with ports entity add1bit is Port ( cin : in STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC); end add1bit; -- Architecture name is picked to indicate this is a behavioral model: architecture Behavior of add1bit is -- This is an internal signal, which does not go to any port: signal int_sum: STD_LOGIC_VECTOR(1 DOWNTO 0); begin int_sum <= ('0' & a) + b + cin; sum <= int_sum(0); cout <= int_sum(1); end Behavior; In the above example ('0' & a) is concatenation of bit 0 with signal a in order to extend the signal from 1 bit to 2 bits before doing the addition. You will most likely need to use this property while creating your multiplexer unit. VHDL requires that at least one of the operands of an arithmetic expression has the same number of bits as the result. ('0' & a) has 2 bits as does the result int_sum. There are many other operations associated with the std_logic_signed library, in addition to +, which can be used in a similar manner: arithmetic: (+, -, *), comparison: (<, <=, >, >=, =, /=) shift: (shl, shr) 2.3.4 Structural (Modular) Coding

Structural or modular coding refers to first creating modules of logic blocks that are functionally independent of each other, and then stitching up these blocks into a circuit with a more complex overall function. One method of doing such hierarchical design in VHDL is shown in the below example where 1-bit full adders are used to build a 4-bit ripple carry adder: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity add4bit is Port ( cin : in STD_LOGIC; x : in STD_LOGIC_VECTOR (3 downto 0); y : in STD_LOGIC_VECTOR (3 downto 0); s : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC); end add4bit; architecture Structure of add4bit is METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 16

-- declare internal signals used to interconnect 1-bit adders: signal c1, c2, c3 : STD_LOGIC; -- declare the component to be used in this architecture: component add1bit Port ( cin : in STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC); end component;

begin -- Instantiate 1-bit adder four times and interconnect: stage0: add1bit port map(cin,x(0),y(0),c1,s(0)); stage1: (fill in prelab) stage2: (fill in prelab) stage3: (fill in prelab) end Structure; The signals declared above preceding the BEGIN keyword in the architecture (c1, c2, c3) are used as carry-out signals from the first three stages of the adder. The next statement is called a component declaration statement, and uses syntax similar to that in an entity declaration. This statement allows the add1bit entity to be used as a component (subcircuit) in the architecture body. The 4-bit adder is described using four instantiations of the 1-bit adder. Each instantiation statement starts with an instance name (stage0, stage1, etc.), which can be any legal VHDL name followed by the colon character. The names must be unique. The colon is followed by the name of the component, add1bit, and then the keyword port map. The signal names in the add4bit entity that are to be connected to each input and output port on the add1bit component are then listed. The signals are listed in the same order as in the add1bit component declaration statement. Alternatively the signals can be listed in other orders by explicitly specifying which signal is to be connected to which port of the component. For example, the first instantiation in the code could be written as: stage0: add1bit port map(b=>y(0),sum=>s(0), cin=>cin,a=>x(0),cout=>c1); 2.3.5 Behavioral Constructs for a Multiplexer

2.3.5.1 Selected Signal Assignment A selected signal assignment allows a signal to be assigned one of several values, based on a selection criterion. The description of a 2-to-1 multiplexer has been provided as an example: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux2to1 is Port ( w0,w1,s f end mux2to1; : in STD_LOGIC; : out STD_LOGIC);

architecture Behavior of mux2to1 is begin WITH s SELECT METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 17

f <= w0 WHEN 0, w1 WHEN OTHERS; end Behavior; VHDL syntax requires that a WHEN clause must be included for every possible value of the selection signal s. Since this signal has the STD_LOGIC type, possible values include 0, 1, Z, -, and others. The keyword OTHERS provides a convenient way of accounting for all logic values that are not explicitly listed in a WHEN clause. The selected signal assignment also facilitates the implementation of any type of decoder. A sample decoder truth table is provided below in Table 2.3.1, followed by the VHDL implementation.

Table 2.3.1. 2-to-4 decoder example S(1:0) 00 01 1X library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mydecoder is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); A : out STD_LOGIC; B : out STD_LOGIC; C : out STD_LOGIC; D : out STD_LOGIC); end mydecoder; architecture Behavior of mydecoder is begin WITH S SELECT (A,B,C,D) <= std_logic_vector(0001) WHEN 00, std_logic_vector(0010) WHEN 01, std_logic_vector(1000) WHEN OTHERS; end Behavior; A sample 4-to-2 priority encoder truth table is provided below in Table 2.3.2, followed by the VHDL implementation. Table 2.3.2. 4-to-2 priority encoder example
x3 x2 x1 x0 | y1 y0 V ----------------------1 X X X | 1 1 1 0 1 X X | 1 0 1 0 0 1 X | 0 1 1 0 0 0 1 | 0 0 1 0 0 0 0 | 0 0 0

A 0 0 1

B 0 0 0

C 0 1 0

D 1 0 0

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity priorityencoder is Port (x : in STD_LOGIC_VECTOR(3 downto 0); y : out STD_LOGIC_VECTOR(1 downto 0); V : out STD_LOGIC); end priorityencoder; architecture Behavioral of priorityencoder is begin y <= "11" when x(3) = '1' else "10" when x(2) = '1' else "01" when x(1) = '1' else "00" when x(0) = '1' else "00"; V <= x(3) OR x(2) OR x(1) OR x(0); end Behavioral;

2.3.5.2 Conditional Signal Assignment A conditional signal assignment allows a signal to be set to one of several values, similar to the selected signal assignment. Below is an alternative architecture to describe the 2-to-1 multiplexer in the previous section: architecture Behavior of mux2to1 is begin f <= w0 WHEN s=0 ELSE w1, end Behavior; 2.4 Hierarchical Schematic Entry with Multibit Signals Modular design entry in VHDL has been described in Section 2.3.4. Similarly, multiple schematic or VHDL design modules can be pulled together in the schematic capture tool using their symbols. 2.4.1 Symbol Creation

Once a design has been fully completed, choose File from Top Menu, and roll the mouse over to Create/Update selection. A side menu appears, from this menu select Create Symbol Files for Current File in order to create a symbol (.bsf file) for your design. The procedure is the same for both Schematic and VHDL design modules. 2.4.2 Module Instantiation in Schematic Capture Tool

If the design module of interest has been created as part of another project, pull it into the current project using File Open , browse and choose the relevant schematic or VHDL design file, making sure that Add file to current project check box is selected. This can be repeated for all the modules that need to be pulled into the current project. The symbols created by the user can be used METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 19

for the current project in same fashion as other symbols such as AND gate, OR gate, etc in schematic design. 2.4.3 Multi-bit Signal Entry in Schematic Tool

Multi-bit signals are entered using Orthogonal Bus Tool. A signal is interpreted as multi-bit only after it is labeled. Some examples of valid multi-bit signals names are: X[3..0] : A 4-bit signal named using vector notation A,B,C,D : Four 1-bit signals grouped together to form a 4-bit signal Y[4..2] : A 3-bit signal; the name implies it may be a sub-branch of the Y signal with more bits 1-bit or multi-bit signals (or I/O ports) are sometimes combined into a multi-bit signal. Quartus II schematic tool requires that a multi-bit signal and each net connected to it through a bus are all clearly labeled. One clean way to do this is to right click on the segment you need to name and select Properties. Below is an example of multi-bit signal connectivity. As observed in the figure, different bits making up the signal LED[3..0] are sourced from different single -bit signals. In the figure below (used as an example to explain multi-bit entry not part of the actual lab work but necessary to understand in order to perform the lab work) you would notice that the outputs of the register_unit are eight bits wide, whereas the input to the HexDrivers are only four bits wide. We need to rip four-bit slices from the eight-bit signals so that they can be connected to the HexDrivers. In order to do so, we first use the Orthogonal Bus Tool to draw a bus from A[7..0] output of the register_unit to the inputs of both the upper HexDrivers. Similarly, we connect B[7..0] output to the other two HexDrivers. Notice that these wires are thicker than the ones you drew before; this indicates that they are multi-bit buses. In order to rip the slices we want, we need to give these buses recognizable names. We can do so by Right-clicking on the wire segment attached to the A output and select Properties and entering A[7..0] in the Name field, then clicking OK. In order to choose the slice that will be our input to the top HexDriver, we right-click on the segment that leads to the HexDriver and select Properties. Here, entering the name A[7..4] would mean the four bits 7 downto 4 are the input for this HexDriver. Notice how Reset, LoadA, LoadB and Execute signals are merged into the LED[3..0] output. In order to do this task we first draw a bus out from the LED[3..0] output to the left, under the control unit and just under the input pins. Then we drew a wire from each of the four signals individually and labeled them. Execute segment was labeled LED[3], LoadA was labeled LED[2], LoadB was labeled LED[1] and Reset was Labeled LED[0]. This merges 1-bit signals to multi-bit signals. Similar approach can be used to merge 1-bit signals with multi-bit signals to get a larger multi-bit signal.

Figure 2.4.1 Multi-bit signal connectivity and naming example METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 20

2.5 EXPERIMENTAL WORK 2.5.1 Experimental Setup

Verify to make sure your workbench has all of the following items: - A Personal Computer (PC) with Altera Quartus II ISE 9.0 Project Navigator - DEO Demo Board with Cyclone III EP3C16F484C6 FPGA installed on a card with 10 input toggle switches, three push buttons, and four 7-Segment LED displays among other components. - A USB cable connected between the demo board and the PC using USB interface 2.5.2 4-bit Ripple Carry Adder Design, Functional and Timing Simulation

2.5.2.1 Use the full design implementation flow from Lab 1 to create a project named <your_name>_add4, enter the design using VHDL, and simulate. Remember to enter the 1bit full adder behavioral VHDL model first in the same project area, and then use instantiations of it. ix) When defining the test bench waveform for functional simulation, make sure test is long enough to fit more than 10 test cycles. Use the pattern wizard to generate pseudorandom vectors for inputs x and y by right-clicking on the vector, choosing set value option, entering Pattern Wizard, and using the random bus pattern type. Pick different random seeds for the inputs x and y to avoid always adding the same number (e.g. 0 for one, 3 for the other). x) After package pin assignment, place and route steps, change test vectors as follows for the timing (post-routing) simulations (may want to also create a new test bench waveform i.e. .tbw file for this step): Assign 0000 to input x, 1111 to input y, 1 to input Cin. Then toggle each bit of the y input to 0 and back to 1, one at a time. Do the same with the Cin input. Measure the time delay between input and Cout for each case and note somewhere. xi) Once you are convinced, based on the functional and timing simulations, that your design module is correct, create a symbol for it as explained in Section 2.4.1. 2.5.2.2 Demonstrate the functional and timing simulation results from above to your lab instructor, after completing all of the steps up to 2.5.2.1(iii). Which input pin has the maximum input-to-output delay based on your experiment in (ii)? Why do you think this is the case? Be ready to comment on this to your lab instructor when you do your demonstration. 2.5.3 HEX Decoder Design, and Simulation

2.5.3.1 Create a project named <your_name>_decode, enter the decoder design using VHDL, and simulate functionality using the input combinations in Table 2.2.1. i) You do not need to do package pin assignments, place and route, or hardware programming for this design. ii) After you check the functionality of the design module, remember to create a symbol for it. 2.5.3.2 Demonstrate the functional simulation results from above to your lab instructor, after completing all of the steps up to 2.5.3.1(ii).

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2.5.4

Priority Encoder Design, and Simulation

2.5.4.1 Create a project named <your_name>_encode, enter the priority encoder design using VHDL, and simulate functionality. Ensure you verify all input scenarios with a unique output. i) You do not need to do package pin assignments, place and route, or hardware programming for this design. ii) After you check the functionality of the design module, remember to create a symbol for it. 2.5.4.2 Demonstrate the functional simulation results from above to your lab instructor, after completing all of the steps up to 2.5.4.1(ii). 2.5.5 Multiplexer Design, and Simulation

2.5.5.1 Create a project named <your_name>_mux, enter the multiplexer design using VHDL, and simulate functionality using all four modes in Table 2.2.2. i) Generate the input vectors for the functional simulation using the random vector assignment described in Section 2.5.2.1. ii) You do not need to do package pin assignments, place and route, or hardware programming for this design. iii) After you check the functionality of the design module, remember to create a symbol. 2.5.5.2 Demonstrate the functional simulation results from above to your lab instructor, after completing all of the steps up to 2.5.5.1(iii). 2.5.6 Complete Combinational Design, Simulation, and Implementation

2.5.6.1 Create a project named <your_name>_combo, enter the complete combinational design using Schematic Capture, simulate, program to FPGA, and test. i) Use the description of Section 2.4.2 to pull in all the previous design modules into the current project. ii) Instantiate the symbols for the design modules, interconnect, and assign I/O ports. Pay attention to multi-bit vs. single-bit wires and naming conventions as described in 2.4.3. iii) Replicate input vectors used in previous module simulations to fully check the functionality of the complete design in all of the four different operation modes. iv) Ensure in functional and timing simulations that your design works correctly before programming to the FPGA. Then program, and test the same vectors as in (iii) above to make sure you get the same results as your functional simulations. If you do not have sufficient number of switches to implement your inputs, remember you can also take advantage of push buttons on DE0 board as inputs. 2.5.6.2 Demonstrate the functional simulation and hardware test results from above to your lab instructor, after completing all of the steps up to 2.5.6.1(iv). REFERENCES: Fundamentals of Digital Logic with VHDL Design, 2nd Edition, Stephen Brown & Zvonko Vranesic, McGraw-Hill, 2005

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EXPERIMENT #4 SYNCHRONOUS BUILDING BLOCKS AND DIGITAL LOCK DESIGN

4.1 OBJECTIVE Simple synchronous storage elements with reset, load, and shift functions will be studied in this experiment with D Flip-Flops (DFFs). These will be used (as modules) to build various basic sequential circuits. A simple Digital Lock Design will be completed next. 4.1. PRELIMINARY WORK

4.1.1. Read through Section 4.3 to learn about VHDL modeling of sequential circuits of synchronous type (with clock.) 4.2.2 D Flip-Flop with Synchronous Reset and Load: Draw a schematic to show how you would add combinational logic along with two new inputs (RST, LOAD) to a conventional D Flip-Flop to have the reset and load functions as shown in the below figure. Note both of the new inputs take effect synchronously on the rising edge of the clock. Hint: You can use multiplexers.

(a) RST 1 0 0 X X X LOAD X 1 0 X X X D X X X X X X Q X X X X X X CLK Q+ 0 D Q Q Q Q Operation Synchronous reset Load Data Retain Value Retain Value Retain Value Retain Value

0 1

(b) Figure 4.2.1 (a) The symbol and b) the condensed truth table for the new Flip-Flop 4.2.3 Use your answer from above to modify the VHDL code provided for the D Flip-Flop in Section 4.3 to implement the new synchronous reset and load functions. Simulate functionality and add it to your report.

4.2.4. Four bit Shift Register with Synchronous Reset and Load: Use the new D Flip-Flop, for which a symbol is provided in Figure 4.2.1 above, to design a 4-bit shift register. The symbol and a table that describes the operation of the register are depicted in Figure 4.2.2. Note the register has three input and four output signals. Draw a schematic of your design. (You may omit the 7-segment LED design in your preliminary work as you designed it in the previous experiment. 7-segment LED decoder will be used to translate the output of your design to the 7segment LED displays.) METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 23

(a) RESET 0 1 1 1 1 DATA (1-bit) X D1 D2 D3 D4 (b) Figure 4.2.2 (a) The symbol and b) the table to describe the 4-bit Shift Register operation 4.2.5 Four-bit Register with Synchronous Reset and Parallel Load: Use the D Flip-Flop to create a similar design (4-bit shift register) as in 4.2.4, this time with parallel load function instead of serial load. Thus in your new design, you will have 4-bit data input instead of one. Figure 4.2.3 depicts the symbol with the desired inputs. Explain the advantages and disadvantages of serial and parallel loads. (Again, no need for designing the 7-segment LED decoder here as well, the decoder will be used during the experimental work.) OUT[3..0] 0000 D1000 D2D100 D3D2D10 D4D3D2D1

Figure 4.2.3. 4-bit Register with Parallel Load 4.2.6 Digital Lock Design with Hardcoded Password: By modifying the parallel load register design, create a digital lock design with a 4-bit hardcoded password. Hardcoded password refers to a set of logic values that cannot be changed. Such passwords can be hardcoded using VCC and GND. A LED should turn on once the correct password is entered. For example, if the password 1011 is hardcoded to your design, when the data is set to 1011 and loaded to the register, the LED (output) should turn on in the FPGA. In order to create the hardcoded password, use the Vcc and GND symbols in your design. An XNOR gate can be compared in order to compare each bit of the parallel-load register with the corresponding bit of the hardcoded password. 4 XNORs then allow the comparison of two 4-bit input signals (one from the password, and the other from the register output) in bitwise fashion. The outputs from the XNORs can be combined through an AND gate in order to have a single signal to drive one of the LEDs on the prototyping board. Bitwise XNOR function and the AND combiner can be referred to as a digital 4-bit comparator. Figure 4.2.4 depicts the implementation of the digital lock design, which includes a 1-bit comparator (does not need a combiner). METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 24

Figure 4.2.4. One-bit implementation of Digital Lock with Hardcoded Password (Vcc) 4.2.7 Digital Lock Design with Programmable Password: Hardcoded passwords are not much desired in real life. In almost all cases, we define a password, and we may want to change it afterwards whenever necessary. A register is necessary to store the programmable password. In this part of the experiment, we divide the system into two parts, i.e., admin side and user side. As admin, you first store your password, e.g. 1011, to your password storage register. Then, using the user side of your design, you hit the same code, e.g. 1011, to enter your password. As a result, your password is verified and so the output LED turns on. You will need 8 DFFs in total for your design, and a 4-bit comparator is required again to turn on one LED when the two 4-bit inputs match. A one-bit design is depicted in Figure 4.2.5.

Figure 4.2.5. One-bit implementation of Digital Lock with Admin/User Mode

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4.3 Implementing Synchronous Logic using VHDL 4.3.1 D Latch Figure 4.3.1 has a sample VHDL code for a D type latch. The process statement introduced within the architecture of the latch is a keyword. It is followed by a parenthesized list of signals, called the sensitivity list. When there is a change in the value of any signal in the processs sensitivity list, then the process becomes active. Once active, the statements inside the process are evaluated in sequential order. The assignments made to signals inside the process are only visible outside the process when all of the statements in the process have been evaluated. If there are multiple assignments to the same signal, only the last one takes effect. The output of the D latch (Q) can change as a result of a change in either Clk or D signal (since D latch is level-triggered and is therefore transparent when Clk=1). Therefore, both Clk and D inputs are included in the process sensitivity list. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dlatch is Port ( D : in STD_LOGIC; Clk : in STD_LOGIC; Q : out STD_LOGIC); end dlatch; architecture Behavioral of dlatch is begin process(D, Clk) begin if Clk = '1' then Q <= D; end if; end process; end Behavioral; Figure 4.3.1 D Latch VHDL Code 4.3.2 D Flip-Flop A positive-edge-triggered D flip-flop is defined in Figure 4.3.2. There are two differences in the VHDL code compared to the D latch. i) Since the only input that can cause an output change is Clk , this is the only signal in the process sensitivity list, ii) ClkEVENT in the if-then statement is an attribute construct that refers to any change in the Clk signal. Thus, output Q gets the value of input D if there is a change in the Clk signal AND the value of the Clk signal is 1. i.e. the condition checks for the presence of a rising (positive) Clk edge before it updates the output. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dflipflop is Port ( D : in STD_LOGIC; Clk : in STD_LOGIC; Q : out STD_LOGIC); end dflipflop; architecture Behavioral of dflipflop is begin process(Clk) begin if ClkEVENT AND Clk = '1' then Q <= D; end if; METU Northern Cyprus Campus EEE 248/CNG 232

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end process; end Behavioral; Figure 4.3.2 D Flip-Flop VHDL Code 4.3.3 D Flip-Flop with Asynchronous Reset

The flip-flop in Figure 4.3.3 is the same as in Figure 4.3.2 except it has an asynchronous active low reset input. Asynchronous reset refers to the fact that when Resetn=0, the output goes to 0 immediately without waiting for the next rising clock edge. i.e. Resetn is not synchronous with the Clk input. All input changes that take effect synchronously with the clock edge need to be checked after finding the ClkEVENT within the process statement, and not before. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dflipflop is Port ( D : in STD_LOGIC; Clk : in STD_LOGIC; Resetn : in STD_LOGIC; Q : out STD_LOGIC); end dflipflop; architecture Behavioral of dflipflop is begin process(Resetn,Clk) begin if Resetn=0 THEN Q <= 0; elsif ClkEVENT AND Clk = '1' then Q <= D; end if; end process; end Behavioral; Figure 4.3.3 VHDL Code for D Flip-Flop with Asynchronous Reset 4.4 EXPERIMENTAL WORK

4.4.1. Experimental Setup Verify to make sure your workbench has all of the following items: - A Personal Computer (PC) with Altera Quartus II ISE 9.1 Project Navigator - DE0 Demo Board with Cyclone III EP3C16F484C6 FPGA installed on a card with 10 input toggle switches, three push buttons, and four 7-Segment LED displays among other components. - A USB cable connected between the demo board and the PC using USB interface 4.4.2 Shift Register Design with Synchronous Reset and Load i) Create a project with a VHDL source as the top module. Implement the D type Flip Flop designed in 4.2.3 in VHDL. ii) Simulate the functionality of your design by creating an appropriate test bench waveform that covers all possible combinations of inputs. Assign the special clock type for signal that is used as a clock in your design. This will automatically generate a periodic square wave on that signal. iii) Create a schematic symbol for your design (under Design Utilities.) iv) Demonstrate the functionality of your design to the lab instructor before proceeding. METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 27

v) vi) vii) viii)

ix) x) xi)

Create a new project with a Schematic source as the top module. Add/Copy the D Flip Flop as a source from the previous project to the new project. Open the top level schematic and instantiate four copies of your flip-flops into it. Implement the 4-bit shift register design from Section 4.2.4, by adding all the required logic, I/O ports, and wiring in the schematic editor tool. After checking all connections are intact, carefully define your test vectors, and check the functionality of your design based on the operation table of Figure 4.2.2. Make sure all operation modes of the shift register are covered in your test vectors. Assign package pins and implement your design. When doing this, assign the clock input to a push button. Generate the programming file, upload your design to the on board FPGA, and test using the toggle switches to control all inputs except the clock, which is controlled by a pushbutton. Demonstrate the simulated and hardware-tested functionality as well as measured delay parameters in timing simulations to the lab instructor. Does pressing of the push button generate a falling edge or a rising edge? What change can you do in the top level design schematic so that the pressing of the push button generates the other edge?

4.4.3

Parallel-Load Register Design with Synchronous Reset Proceed to implement a 4-bit register design with parallel load, doing the appropriate wiring, and pin assignments. Upload your design to the DE0 demo board and demonstrate to the lab instructor.

4.4.4

(BONUS) Digital Lock Design with Hardcoded Password Proceed to implement a 4-bit digital lock design with hardcoded password, doing the appropriate wiring, and pin assignments. Upload your design to the DE0 demo board and demonstrate to the lab instructor.

REFERENCES: Fundamentals of Digital Logic with VHDL Design, 2nd Edition, Stephen Brown & Zvonko Vranesic, McGraw-Hill, 2005 Terasic DE0 User Manual

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EXPERIMENT #5 COMBINATIONAL AND SEQUENTIAL DESIGN USING STANDARD COMPONENTS

5.1 OBJECTIVE The objective of this experiment is to get hands-on experience with wiring/building combinational and sequential digital circuits using standard SSI (Small Scale Integrated Circuit) components. Altera tools and FPGAs will not be used. However, students are welcome to simulate their design using Altera tool suite while preparing for the lab to enhance their learning. 5.2 PRELIMINARY WORK 5.2.1 5.2.2 Read section 5.3, and understand the definition of the propagation delay. a) Derive combinational logic, using NAND gates only, for the function represented in the truth table with the following differing design targets. Hint: You should end up with a different solution for each design target. i) minimum input-to-output propagation delay, ii) minimum number of literals. b) What are tPLH and tPHL associated with your design solution in (i) and (ii), if you assume both tPLH and tPHL associated with a NAND gate is 1 ns?
a 0 1 1 1 1 1 b X 0 0 0 0 1 c X 0 1 1 1 X d X X 0 X 1 X e X X 0 1 0 X f 0 0 0 1 1 1

5.2.3

Design a three bit down counter with asynchronous clear using rising-edge triggered D-type flip-flops. The count should wrap around from 000 to 111. Do the same design in 5.2.3 using negative-edge triggered JK-type flip-flops with asynchronous active low clear. Research and find out how the 74LS190 up-down counter IC works. Explain it. Read through experimental section 5.4. Develop a wiring plan for each of the designs in 5.4.1, 5.4.2, and 5.4.3. In order to do this, first sketch the IC component package picture (in the APPENDIX) with clearly marked pin numbers (1-14) for each occurrence of the IC component. Then show the wiring between component pins by drawing pin-to-pin lines. Also show any pins that should be tied to GND (Low) or VCC (High).

5.2.4

5.2.5 5.2.6

5.3 Definition of Propagation Delay Propagation delay is the delay from a change at an input to a change at the output. tPHL is the propagation delay for an input change causing a HIGH to LOW transition at the output (this transition does NOT REFER to input change). tPLH is the propagation delay for an input change causing a LOW to HIGH transition at the output. The figures below illustrate tPHL and tPLH for inverting and non-inverting gates. Propagation delays are often measured between the 50% point of the input and output transitions as shown.

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Propagation Delay (inverting)

Propagation Delay (non-inverting)

5.4 EXPERIMENTAL WORK 5.4.1. Combinational propagation delay Construct the circuit you have designed in preliminary work part 5.2.2(a-ii) using up to three 74LS00 ICs. Connect the circuit inputs to CADET experimental setup switches, and output to an LED again on the CADET for functional testing. a) After making sure your circuit is functional, measure the propagation delays tPLH and tPHL from each of the two inputs d and e to the output f using the oscilloscope. You should connect the measured input to the low frequency square wave generator on the CADET and make sure the other inputs are biased with constant 0/1 so that output toggles with the measured input. You need input and output to periodically toggle together as depicted in the above figures in order to get a healthy measurement. You can use the input rising edge as the oscilloscope trigger. b) Use your measurements to estimate the average propagation delay of a NAND gate in 74LS00 family for your test conditions (you do not have to distinguish between tPLH and tPHL delay when you do your estimation i.e. assume they are the same.) Hint: Take the average NAND gate delay across all of your measurements in (a) by considering the number of NAND gates into account between a measured input and the output. METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 30

H Y L H L

c) Compare your estimation from (b) with the values provided in the datasheet? How close is your estimate to the expectation from the datasheet? Demonstrate the functionality of your circuit to the lab instructor, and show how you have done your NAND propagation delay estimation and comparison with the datasheet. 5.4.2 4-bit shift register

Construct the shift register given below by using two 74LS74 ICs. i. First use a switch in your CADET experimental setup for Serial Input, and a push-button for the clock (CP). Test the operation. ii. After you made sure the design (i) is functional, connect the active-low output (Serial Output or Q) of the last Flip-Flop in the chain to Serial Input. Preset one of the Flip-Flops and Clear the other three. Connect the clock to a very low frequency square wave output from your CADET setup. What do you see? Gradually increase the clock frequency? What is happening? Demonstrate to your lab instructor, explaining in detail the operation and observations.
LED LED LED LED

Serial SI D Input

Serial Output

CP

5.4.3. 3-Bit Down-Counter with Asynchronous Reset Construct the counter you designed in preliminary work part 5.2.4 using two 74LS73 JK Flip-Flop ICs, and up to two 74LS00 NAND ICs available in the lab. Demonstrate to your lab instructor using pushbutton as your clock input CP, and explain in detail how you initialize the starting count value, and how it works thereafter.

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APPENDIX:

74LS00 Quad (Four) NAND Gates, Dual Input:

Package:

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74LS74 D FF:

Package:

74LS76 JK Flip-Flop:

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EXPERIMENT #6 FSM DESIGN FOR CALCULATOR CONTROL

6.1 OBJECTIVE Altera toolset will be used in Experiments 6 & 7 to build a 4-bit calculator. Only the Finite State Machine (FSM) that forms the backbone of the calculator controller will be implemented in this experiment. The rest of the logic will be added in the final project (Experiment 7). 6.2 PRELIMINARY WORK 6.2.1 i) Complete the below state table output column, noting that the output is the state number decoded to be displayed on a 7-Segment LED Display (DP bit is not used). ii) Draw a state diagram that corresponds to the state table. Is this a Mealy machine?
Present State S0 S1 S2 S3 S4 Next State RUN S0 S0 S0 S0 S0 RUN S1 S2 S3 S4 S4 7-Segment Output A, B, C, D, E, F, G 0000001 1001111 0010010

6.2.2

Show the transition table corresponding to the state table using one-hot encoding for the state assignments. (Do not try to reduce the number of states.) How many D Flip-Flops would you need to store the state with this encoding scheme? A property of one-hot state assignment is the simplicity of the flip-flop input logic. Draw a logic schematic for the one-hot FSM using D Flip-Flops after deriving the input equations directly using the transition table from 6.2.2 (without using K-maps). Add the decoding logic to your schematic showing an implementation for the 7-Segment Output. Following the behavioral description example provided in Section 6.3, write up a VHDL code for the above FSM with one-hot state assignment. Do not forget to include the implementation of the 7-Segment Output decoding logic in the same code. Submit a printout of your VHDL code. Note: It is a good idea for you to bring along a USB flash memory containing your code, and also save all of your lab work to it. Your work from this lab will be useful in the final project.

6.2.3

6.2.4

6.3 FSM Description Using VHDL Behavioral constructs are often utilized in VHDL to describe a Finite State Machine. For the simple FSM described in the below table, a coding example follows with some explanation. Present State A B C METU Northern Cyprus Campus A A A Next State B C C EEE 248/CNG 232 Output z 0 0 1 Spring 2013 34

LIBRARY ieee; USE ieee.std.logic.1164.all; ENTITY simple IS PORT (Clock, Resetn, w : IN STD_LOGIC; z : OUT STD_LOGIC); END simple;

A ARCHITECTURE L Y H H L

Behavior OF simple Y IS SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0); CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := 00; CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := 01; CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := 11;

BEGIN PROCESS (w, y_present) BEGIN CASE y_present IS WHEN A => IF w=0 THEN y_next <= A; ELSE y_next <= B; END IF; WHEN B => IF w=0 THEN y_next <= A; ELSE y_next <= C; END IF; WHEN C => IF w=0 THEN y_next <= A; ELSE y_next <= C; END IF; WHEN OTHERS => y_next <= A; END CASE; END PROCESS; PROCESS (Clock, Resetn) BEGIN IF Resetn=0 THEN y_present <= A; ELSIF (ClockEVENT AND Clock=1) THEN y_present <= y_next; END IF; END PROCESS; z <= 1 WHEN y_present = C ELSE 0; END Behavior; There are many different ways to describe a FSM in VHDL. Above is just one example. The first part declares an ENTITY named simple with input ports Clock, Resetn, w, and output port z. The ARCHITECTURE with the name Behavior is described next. The y_present and y_next signal groups represent the outputs of the present and next state logic respectively. The CONSTANT declarations allow the binary state assignments to be specified. In alternate implementations, state assignments in the VHDL code can be skipped, in which case the assignments are automatically done as a synthesis step. Note that the syntax for assigning a value to a constant uses the := operator rather than the <= operator that is used for signals. Starting with the first PROCESS statement, the state table is defined as combinational logic using the CASE construct. The second PROCESS introduces flip-flops into the METU Northern Cyprus Campus EEE 248/CNG 232 Spring 2013 35

circuit. The present state (y_present) acquires the value of the next state (y_next) once the positive clock edge is detected. The active low Resetn, which is used to reset the value of the flip-flops, is implemented independent of the clock edge. Hence it is an asynchronous reset. 6.4 EXPERIMENTAL WORK: One-Hot FSM Implementation i) ii) Define a new project, and enter your VHDL code for the FSM from 6.2.4. After passing the syntax check and synthesis steps, carefully define input waveforms to fully verify the state transitions shown in the provided state table by checking the outputs. iii) Simulate your design. Demonstrate to the lab instructor by clearly explaining your simulation results, and comparing against the provided state table. iv) Once satisfied with the functionality of the FSM, assign your 7-Segment Outputs to the appropriate package pins. Map the package pin associated with any switch to your input. Map the clock input of your design to a push button. Remember the push button on DE0 board is active low (may need an inverter in your design if you would like to have the high pulse when you push). v) Implement: Translate, Map, Place & Route your design, and generate a programming file.

vi) Upload your programming file to the FPGA, and test by demonstrating that you are able to enter all of your available states by controlling the input properly. Demonstrate your test results to the lab instructor. vii) After you are done with above (vi), re-map the clock input to a free-running clock on DE0 board instead of the push button. Program your new design and test. Can you use the input switches to display the output of every state on the 7-Segment Display? Why or why not? Demonstrate your test results to the lab instructor. REFERENCES: Fundamentals of Digital Logic with VHDL Design, 2nd Edition, Stephen Brown & Zvonko Vranesic, McGraw-Hill, 2005 Terasic DE0 User Manual

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EXPERIMENT #7: FINAL PROJECT 4-BIT CALCULATOR DESIGN, SIMULATION, and IMPLEMENTATION
7.1 OBJECTIVE A datapath will be added to the calculator controller designed in Experiment 6. The FSM from the last experiment will be enhanced to deliver the control signals required by the datapath. Each lab group will thus deliver a complete 4-bit calculator design as a final project. Altera toolset will be used to enter, simulate, and implement the design. The final design will be demonstrated to the lab instructor during a reserved ~15 minute time slot by each student individually (not as a group). Each student will also generate a project report that contains the details of the design and simulation results. This report should be submitted at the time of your scheduled demonstration. 7.2 DATAPATH DESIGN Figure 7.1 depicts the datapath for the calculator to be designed in this experiment. The wires in the vertical direction represent the data, while the labeled horizontal wires coming from the sides, including the ALU Carry-In (Cin) signal, are the control signals from the FSM used to facilitate various operations through the calculator. Depending on the Input_Select signal, various externally and internally generated data signals can be fed to the datapath from the top: Bitwise inverted and noninverted input data (DIN), inverted and non-inverted register B (RB), arithmetic-right-shifted (ARS), logical-right-shifted (LRS), and logical-left-shifted (LLS), and non-shifted register A (RA). Both RA and RB are 4-bit wide. The 4-bit Arithmetic Logic Unit (ALU), ARS, LRS, LLS units are purely combinational, and do not contain any memory elements. The ALU unit in this calculator can only do one of eight operations based on the ALU_OP value, as shown in Table 7.1 below. Note the clock signal going to RA and RB are not shown in Figure 7.1.

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7.3 CALCULATOR MICRO-OPERATIONS Sixteen simple micro-operations will be implemented by your calculator, as described in Table 7.2. The calculator controller FSM will receive a 4-bit instruction, MOP(3:0), from the user, and activate the appropriate control signals to the datapath accordingly to execute the corresponding microoperation. Table 7.2 Calculator Micro-operations
Instruction Mnemonic NOP CLR LOADA LOADB BCOPYA ADD2 ADD21 ADD3 SUB BINVB BAND BOR BXOR BLSRA BLSLA BASRA Binary Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Micro-Operation -RA 0000;RB 0000 RA DIN RB DIN RB RA RB RA + RB RB RA + RB + 1 RB RA + RB + DIN RB RA - RB RB NOT RB RB RA AND RB RB RA OR RB RB RA XOR RB RB RA >> 1 RB 1 << RA RB RA >>> 1 Description Do Nothing Clear registers RA and RB Load RA with the value of DIN Load RB with the value of DIN Copy the value of RA to RB Add RA and RB, and store the result to RB Add RA, RB and 1 and store the result to RB Add RA, RB and Din and store to RB Subtract RB from RA and store to RB Bitwise invert RB and store back to RB Bitwise AND operation between RA and RB Bitwise OR operation between RA and RB Bitwise XOR operation between RA and RB Logical shift right RA by 1 (with 0 shift-in bit) and store to RB Logical shift left RA by 1 (with 0 shift-in bit) and store to RB Arithmetic shift right RA by 1 (with MSB shifted in) and store to RB

7.4 PRE-LAB WORK The following should be submitted in your report: 7.4.1 Complete Table 7.3 for each micro-operation in order to plan for the design modifications to the Calculator FSM from Experiment 6. Table 7.3 Calculator FSM Output Sequence Planning
Instruction Mnemonic
out_state <= "0000"; Input_Select <= "000"; Load_A <= '0'; Load_B <= '0'; Cin <= '0'; ALUop <= "000"; Reset <= '0'; out_state <= "0000"; Input_Select <= "000"; Load_A <= '0'; Load_B <= '0'; Cin <= '0'; ALUop <= "000"; Reset <= '0'; out_state <= "0001"; Input_Select <= "000"; Load_A <= '0'; Load_B <= '0'; Cin <= '0'; ALUop <= "000"; Reset <= '0'; out_state <= "0001"; Input_Select <= "100"; Load_A <= '0'; Load_B <= '1'; Cin <= '0'; ALUop <= "001"; Reset <= '0'; out_state <= "0010"; Input_Select <= "000"; Load_A <= '0'; Load_B <= '0'; Cin <= '0'; ALUop <= "000"; Reset <= '0'; out_state <= "0010"; Input_Select <= "100"; Load_A <= '1'; Load_B <= '0'; Cin <= '0'; ALUop <= "000"; Reset <= '0'; out_state <= "0011"; Input_Select <= "100"; Load_A <= '0'; Load_B <= '1'; Cin <= '1'; ALUop <= "001"; Reset <= '0'; out_state <= "0011"; Input_Select <= "110"; Load_A <= '0'; Load_B <= '1'; Cin <= '0'; ALUop <= "001"; Reset <= '0'; out_state <= "0100"; Input_Select <= "000"; Load_A <= '0'; Load_B <= '0'; Cin <= '0'; ALUop <= "000"; Reset <= '0'; out_state <= "0100"; Input_Select <= "000"; Load_A <= '0'; Load_B <= '0'; Cin <= '0'; ALUop <= "000"; Reset <= '0';

S0

S1

S2

S3

S4

ADD21

ADD3

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7.4.2

Modify the Calculator FSM VHDL code from Experiment 6 to add the new multi-bit input MOP(3:0), and the following outputs: Load_A, Load_B, Cin, ALUop(2:0), Input_Select(2:0), Reset, and out_state(3:0). out_state(3:0) is a new output from the FSM that contains the binary value of the present state for debug purposes. It replaces the 7-bit 7-segment output in Experiment 6. Verify functionality by simulating your modified FSM design with different MOP inputs. Submit the new VHDL code, and the simulation results in your report showing all inputs and outputs clearly as the FSM sequences through S0, S1, S2, S3, and S4 for an ADD21 followed by an ADD3 instruction. Design the Datapath in Figure 7.1. First enter the design for 4-bit ALU, 4-bit ARS, 4-bit LRS, 4bit LLS, 4-bit register, and the 4x 8-to-1 MUX in VHDL, and make sure all of these blocks work by themselves through functional simulations. Your ALU simulations should go through all the ALU operations with X=1010 and Y=0011. Include the VHDL code and simulation results for all of the functional blocks in your report. Then, connect the blocks together to build the Datapath in the schematic editor. Simulate the full Datapath by stimulating the inputs in the right sequence in the test bench waveform editor to execute an ADD3 instruction. Submit a printout of your datapath schematic and simulation results. Create a symbol for the FSM in 7.4.2 and the Datapath in 7.4.3. Create a new schematic called calculator_<your initials>, instantiate, and interconnect FSM and Datapath blocks. In addition create three more blocks in VHDL: A 4x 2-to-1 MUX, a 7-Segment decoder to display a hexadecimal digit on 7-Segment display, and a 1x 2-to-1 MUX to determine the value of the DP output on the 7-segment LED display. The 4-bit MUX will select between the DOUT(3:0) from the Datapath block and the out_state(3:0) from the FSM block based on a new 1-bit selector input called debug. The 1-bit MUX uses the same debug input to select between Cout and an inactive bit. A block diagram of the final design is shown in Figure 7.2. Run one full calculator simulation for each of the calculator instructions with appropriate data vectors (for a total of 16 simulations), and an additional simulation in debug mode to show correct state transitions.

7.4.3

7.4.4

Figure 7.2 4-Bit Calculator Block Diagram 7.4.5 Timing constraints: Altera place and route tools may not try hard to optimize the timing of your signals if you do not specify desire to do so. The compiler by default trades off design timing optimization and compilation time. This results in long propagation delays for some signals, and may even cause functional failures at low clock rates due to hold time or clock skew issues. If you see problems when testing on hardware even though your simulation works fine, try forcing the compiler to work harder on timing optimization by going to Fitter (Place & Route) Edit Settings and marking Optimize hold timing as All paths. In addition mark Fitter effort as EEE 248/CNG 232 Spring 2013 39

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Standard fit and change Desired worst case slack to 5 ns. You should not nominally have any path with higher delay than 20ns. You can check Fitter Timing analysis report after the compilation to make sure you do not have any timing violation (appears in red). If you have setup time problems, you can usually fix them by slowing down your system clock. For hold problems, or clock skew problems, the previous settings should help. 7.4.6 Include your name, course name, course code, date, an objective statement, and a conclusion in your report. Add short comments to briefly explain each VHDL code, schematic, and simulation that you submit. Once everything works well in simulations, check your timing analysis report to find out how fast your design is expected to work. Report this fmax in your report and append a printed copy of the timing analysis summary to your report. Bonus: When you are doing arithmetic operations such as addition or subtraction, does the state of Cout or the most significant bit of the calculation result (DP output on 7-segment LED) get displayed correctly by your calculator in the final state (S4) of the instruction execution? Explain why or why not? If Cout associated with the arithmetic operation you are doing is not correct, how can you fix the datapath to display the Cout associated with arithmetic instructions correctly in state S4? Implement your proposed fix and test your design again.

7.4.7

7.5 EXPERIMENTAL WORK: Calculator Implementation During your final demo you will be evaluated on your understanding of: o Combinational and sequential concepts, o Calculator design details, o VHDL and schematic based design entry, and o Simulation flows. You will program your final design onto an FPGA and demonstrate it. If something goes wrong with the hardware demo or does not seem to work consistently using a manual clock (from push-button) or free-running on-board clock, you should be ready to do a quick postroute simulation of your design to demonstrate the corresponding functionality in simulation. (You can only do this if you understand your simulations very well.) Prepare various test bench waveforms in advance to be able to do this. Remember you will have very limited time with the Teaching Assistant to demonstrate you have a working design, AND you fully understand your design. He/she will not do your debug for you. Start your lab early so you can resolve any problems ahead of time during office hours, and come to the final demo fully prepared!

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