Академический Документы
Профессиональный Документы
Культура Документы
Integrated Circuits
Module 1 Logic Families - DTL - TTL - ECL - I2L & CMOS. Comparison of circuits. Tristate logic Propagation delay - power dissipation - Noise margin window profile - comparison -Fan in Fan out
Diode Transistor Logic This is simple DTL Nand gate but this works only marginally
If all inputs are high,the diodes are reverse biased and so no current flows thru them current goes to transistor and the transistor saturates and VOUT goes low. If any input goes low, the base current is diverted out through the input diode. The transistor cuts off and VOUT goes high. This is a NAND gate. n The gate works marginally because VD = VBEA = 0.7V.
If all inputs are high, Vx = 2.2V and the transistor is saturated. If any input goes low (0.2V), Vx=0.9V, and the transistor cuts off.
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out The added resistor RD provides a discharge path for stored base charge in the BJT, to provide a reasonable tPLH.
ADVANTAGES DEMERITS Tight Vcc tolerance Relatively high power consumption Moderate packing density Generation of noise spikes Susceptible to power transients SUBFAMILIES:Std TTL ,High speed TTL ,low power TTL, Schottky TTL ,Low power Schottky TTL, Advanced Schottky TTL STD TTL CHARACTERISTICS Propagation delay=9 ns 5V 2V High 0 V to 0.8V=logic 0 2 V to 5 V=logic 1 Good speed Low manufacturing cost Wide range of circuits Availability in ssi and msi
0.8V
Low
Noise Margin=0.4 mv
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out Fan in=8, Fan out=10
TOTEMPOLE O/P
Q3 sits above Q4=TOTEMPOLE
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out At any time only one will be conducting.This is ensured by diode D Q4=ON..VBE OF Q4=0.7.Since Q4 gets base drive from Q2
ADVANTAGE OF TOTEMPOLE: Even though ckt can work with Q3 and D removed,by connecting R4 directly to collector of Q4,power dissipation increases. Inclusion of Q3 and D makes the current thru R4=0 in o/p low state.thus power dissipation decreases In o/p high state ,Q3 acts as an emitter follower with its associated low o/p impedance.The low o/p impedance provides a small time constant for charging up any capacitive load on the o/p Thus active pullup reduces current in LOW STATE and provides very fast rise time waveforms in HIGH state Current Sinking A TTL ckt acts as current sink in low state ie it receives current from i/p of the gate driving it.
Since Q4 is in on state a large current can flow thru it to ground .So it acts as a sink for input current of load gate Q4 is the current sinking transistor or pull down transistor coz it brings o/p to its low state.
CURRENT SOURCING: A TTL ckt acts as a current source in HIGH state in that it supplies current to the gate it is driving.Q3 is the current sourcing transistor or pull up transistor bcoz it pulls up the o/p voltage to its high state
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out
OPEN COLLECTOR
In open collector,the o/p is at Q4 with nothing connected to it( i.e.the pullup transistor Q3 and diode D are omitted)i.e the active pull up of totempole is not present.Instead only an external
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out
resistor R is connected to Vcc from collector of Q4.Since R is a passive element,this is called passive pull up.
Sometimes the o/p of a no of NAND gateshave to be AND ed.To achieve this we will need 2 more nand gates.Wheras the same thing can be performed by simply tying the o/ps of NAND gates 1,2,3 as shown in fig.This is called Wired AND operationbcoz the and is obtained by simply connecting o/p wires together With this,when any of the gate o/ps go to a low state.the common o/p point also goes LOW as a result of shorting to ground through ON transistor
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out
TRISTATE TTL:
It utilizes the advantage of high speed of totempole and wire ANDing of open collector configuration.It is called tristate TTL bcoz it allows three possible o/p states:HIGH, LOW,HIGH IMPEDANCE (Hi-Z) state. In hi-z state: both the transistors in totempole arrangement are turned off,so that o/p terminal is a high impedance to ground or Vcc. The o/p acts like an open or floating terminal which is neither a HIGH nor LOW It is not exactly an open ckt,but has a very resistance (in M range) w.r.t ground or Vcc
The circuit has two i/ps-A is the normal logic i/p and E is an enable i/p that can produce the Hi-Z state.There are 2 states for operation based on the E i/p 1. The Enabled state(E=1) Here the ckt works as a normal inverter bcoz the high voltage of E has no effect on Q1 or Q2 2. The Disabled State(E=0) When E=0,the circuit goes into its Hi-Z state regardless of the state of Logic i/p A. i.e in this state the changes in A does not affect the o/p.The Low at E forward biases the emitter base junction of Q1 and shunts current in R1 away from Q2
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out
I2L Inverter
Some discrete gates are not available in I2L.The opn of an I2L inverter can be explained using this fig which behaves in same way as an I2L inverter.The p-n-p transistor Q1 serves as a constant current
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out source that injects current into node X.The direction in which current flows after entering node X depends on i/p level. A low i/p is a current sink. When i/p =low,injected current flows into i/p,thus diverting currents from the base of Q2. Thus Q2 is off and o/p is HIGH. A HIGH i/p acts as a current source. The injected current flows into base of Q2turning it ON and making the o/p LOW
The o/p transistor has two collectors making it equivalent to two transistors with parallel base and emitters.Thus it produces two equal o/ps.Instead of a collector resistor,o/ps r connected directly to i/ps of other I2L gates.
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out If either i/p A or both A and B are LOW(current sinks),the injected current flows intop the i/ps and Q2 remains OFF(HIGH) If both the i/ps are HIGH,the injected current turns on Q2 making the o/p LOW This is how NAND operation is performed
I2L NOR
The I2L NOR is simply two inverters with their o/ps connected together. If either or both i/ps are HIGH,the corresponding o/p transistor is ON and o/p is acurrent sink i.e. o/p=LOW If both the i/ps are LOW,both the o/p transistors are OFF. i.e o/p= HIGH
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out 1. It is a non saturated logic i.e. transistors are not allowed to go into saturation.So storage time delays are eliminated and speed of operation increases 2. Currents are kept high and the o/p impedance is so low that circuit and stray capacitances can be quickly charged and discharged 3. Limited voltage swing. It is called Emitter coupled logic bcoz here the emitters of two BJTs are joined(coupled) at their emitters.Transistors are prevented from going into saturation when i/p changes from LOW to HIGH by choosing logic levels very close to each other DISADVANTAGES: 1.Difficult to achieve good noise immunity(low noise margin) 2. Power consumption increased since transistors are not saturated 3.High cost 4.Its negative supply voltage and logic levels are not compatible with other families 5.Problem of cooling the heat produced by high power dissipation ADVANTAGES: 1.Current drawn is steady 2.ECL gated dont experience large switching transients WORKING: Operates on the basis of current switching,where a fixed bias current less than Ic(sat) is switched from one transistors collector to another
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out 9. Susceptible to static charge damage Uses 1.In LSI,VLSI and ULSI for Large memories,calculator chips,large microprocessors due to its ease of fabrication and large packing density.It is slower than TTL so hardly used in MSI and SSI
CMOS
The CMOS family uses both P and N channel MOSFETS in the same ckt to realize several advantages over PMOS and NMOS. It is faster and consumes less power than other MOS families.There is always a high resistance b/w b/w VDD Terminal and ground,bcoz of MOSFET in current path. This results in very low power consumption it has increased complexity and lower packing density than NMOS and PMOS. It can be operated at higher voltage resulting in increased noise immunity: Noise margin is the same in both HIGH and LOW states .NM=30%VDD,indicating that noise margin increases with an increase in power supply.So in noisy environments,CMOS with large Vdd is preferred It draws almost zero current from driving gate.So fanout is very high Very small o/p resistance compared to NMOS Speed of CMOS decreases with increase in load.
CMOS Inverter
It consists of an NMOS transistor Qn and a PMOS transistor Qp.The i/p is connected to the gates of both the devices.The +ve supply voltage is connected to source of PMOS and source of NMOS is grounded When Vin =0 V(LOW), VGSn=-5 V and VGSp=0 V .So Qp is ON and Qn=OFF.Thus Vout=5 V When Vin=+5V(HIGH), VGSn=0 V and VGSp=+5 V.So Qp isOFF and Qn=ON.Thus Vout=0 V
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out
CMOS NAND
Here Q1 and Q2 are parallel connected PMOS transistors and Q3 and Q4 are series connected NMOS. When A=0 V and B=0 V,VGS1=VGS2=-5 V
Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out