Академический Документы
Профессиональный Документы
Культура Документы
Introduction
...........................................................................................................................
Architecture ...................................................................................................... Flexible Clock System ........................................................................................ Embedded Emulation ......................................................................................... Address Space .................................................................................................. MSP430x2xx Family Enhancements .....................................................................
Page
26 26 27 27 29
Introduction
25
Architecture
www.ti.com
1.1
Architecture
The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von-Neumann common memory address bus (MAB) and memory data bus (MDB) (see Figure 1-1). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x2xx family include: Ultralow-power architecture extends battery life 0.1 A RAM retention 0.8 A real-time clock mode 250 A/MIPS active High-performance analog ideal for precision measurement Comparator-gated timers for measuring resistive elements 16-bit RISC CPU enables new applications at a fraction of the code size. Large register file eliminates working file bottleneck Compact core design reduces power consumption and cost Optimized for modern high-level programming Only 27 core instructions and seven addressing modes Extensive vectored-interrupt capability In-system programmable Flash permits flexible code changes, field upgrades and data logging
Clock System
MCLK
ACLK SMCLK
Flash/ ROM
RAM
Peripheral
Peripheral
Peripheral
JTAG/Debug
MAB 16-Bit
MDB 16-Bit
Bus Conv.
MDB 8-Bit
JTAG
ACLK SMCLK
Watchdog
Peripheral
Peripheral
Peripheral
Peripheral
1.2
26
Introduction
www.ti.com
Embedded Emulation
1.3
Embedded Emulation
Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources. The benefits of embedded emulation include: Unobtrusive development and debug with full-speed execution, breakpoints, and single-steps in an application are supported. Development is in-system subject to the same characteristics as the final application. Mixed-signal integrity is preserved and not subject to cabling interference.
1.4
Address Space
The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1-2. See the device-specific data sheets for specific memory maps. Code access are always performed on even addresses. Data can be accessed as bytes or words. The addressable memory space is currently 128 KB.
Access 1FFFFh 10000h 0FFFFh 0FFE0h 0FFDFh Flash/ROM Word/Byte Interrupt Vector Table Word/Byte Flash/ROM Word/Byte
0200h 01FFh
RAM
Word/Byte
16-Bit Peripheral Modules 0100h 0FFh 010h 0Fh 0h 8-Bit Peripheral Modules Special Function Registers
Word
Byte
Byte
1.4.1 Flash/ROM
The start address of Flash/ROM depends on the amount of Flash/ROM present and varies by device. The end address for Flash/ROM is 0x0FFFF for devices with less that 60KB of Flash/ROM. Flash can be used for both code and data. Word or byte tables can be stored and used in Flash/ROM without the need to copy the tables to RAM before using them. The interrupt vector table is mapped into the upper 16 words of Flash/ROM address space, with the highest priority interrupt vector at the highest Flash/ROM word address (0x0FFFE).
Introduction
27
Address Space
www.ti.com
1.4.2 RAM
RAM starts at 0200h. The end address of RAM depends on the amount of RAM present and varies by device. RAM can be used for both code and data.
xxxAh 15 7 14 6 . . Bits . . . . Bits . . Byte Byte Word (High Byte) Word (Low Byte) 9 1 8 0 xxx9h xxx8h xxx7h xxx6h xxx5h xxx4h xxx3h
28
Introduction
www.ti.com
1.5
Watchdog Timer
Flash Memory
Digital I/O
All ports have integrated pullup/pulldown resistors. P2.6 and P2.7 functions have been added to 20- and 28- pin devices. These are shared functions with XIN and XOUT. Software must not clear the P2SELx bits for these pins if crystal operation is required. Comparator_A has expanded input capability with a new input multiplexer. Typical LPM3 current consumption has been reduced almost 50% at 3 V. DCO startup time has been significantly reduced. The maximum operating frequency is 16 MHz at 3.3 V. An incorrect password causes a mass erase. BSL entry sequence is more robust to prevent accidental entry and erasure.
Introduction
29