Hardware Implementation of AMBA based AHB2APB processor interface module on FPGA

Mahesh V Sonth 1 , NarendraKumar 2

1

PG Student, VLSI Design and Embedded System, RNSIT, Bangalore, India. Asst.Prof , Department of ECE, RNSIT, Bangalore, India. maheshsonth@gmail.com
2 1

Abstract- Designing an AMBA based interface between AHB and APB is the major work described in this paper.The interface between high-performance AMBA bus AHB and low performance AMBA bus APB. Then two target devices Register and Ram are connected to APB side to perform 32-bit read/write operation through the designed interface commanding from AHB side. The design is simulated using ModelSim SE PLUS 6.3f simulator. Timing and power analysis is performed using Xilinx ISE 12.2

Keywords- AMBA Protocol, Verilog, processor interface, FPGA. I. INTRODUCTION

APB: Advanced Peripheral Bus (APB): The AMBA APB is for low-power peripherals. APB is made perfect for minimum power consumption and reduced interface complexity to support peripheral functions. APB can be used in conjunction with any of the version of the system bus [1]. AHB2APB Bridge interfaces AHB and APB buses. It is required to bridge the communication gap between low bandwidth peripherals on APB with the high bandwidth ARM Processors and/or other high-speed devices on AHB. This is to ensure that there is no data loss between AHB to APB or APB to AHB data transfers. Source Master/ slave Global Global Master Master Master Master Decoder Slave Slave Slave Global Global Master Decoder Master Master Slave Master Input/ output Input Input Input Input Input Input Input Output inout Output Input Input Input Input Input Input Output Input

The Advanced Microcontroller Bus Architecture (AMBA) is on-chip bus architecture used to strengthen the reusability of IP core and widely used interconnection standard for SoC. The development of SoC and reusable IP cores are given high priority because of low cost and time to market. There are three distinct buses defined within the AMBA specification-Advanced High Performance bus (AHB), Advanced system Bus (ASB) & Advanced Peripheral Bus (APB). AHB: It is for high performance, high clock frequency system modules. The AHB works as the high performance system backbone bus. AHB supports the efficient connection of processors, on-chip memory and off-chip external memory interfaces with low power peripheral macrocell functions. AHB is also specified to ensure ease of use in an efficient design flow using synthesis and automated test techniques [1].

Signal HCLK HRESETn HADDR[31:0] HTRANS[1:0] HBURST[2:0] HWDATA[31:] HSELx HRDATA[31:0] HREADY HRESP[1:0] PCLK PRESETn PADDR[31:0] PSELx PENABLE PWRITE PRDATA[31:0] PWDATA[31:]

Description Global clock signal Global reset AHB address Transfer type Burst type Write data bus Slave select Read data bus Transfer done Transfer response signal Clock signal Reset signal APB address Slave select APB strobe Transfer direction Read data bus Write data bus

Table 1

AMBA Signal list [1]

II.
Figure 1 Typical AMBA based Microcontroller

RELATED WORK

The AHB2APB interfaces AHB and APB. It buffers address controls and data from the AHB, drives the APB peripherals and return data along with response signal to the AHB [4].

The AHB2APB interface is designed to operate when AHB and APB clocks have the any combination of frequency and phase TheAHB2APB performs transfer of data from AHB to APB for write cycle and APB to AHB for Read cycle. AMBA is a standard interface specification that makes sure of the compatibility between IP components provided by different design teams or vendors. The world wide reception of AMBA specifications all over the semiconductor industry has driven a comprehensive market in third party IP products and tools to support the development of AMBA based systems. III. INTERFACE TOP BLOCK DIAGRAM

D.

Address Decoder

This block the target device for the transfer. It compares the 4 most significant bits of HADDR and compares with some constants to determine whether RAM or register is intended for the transfer. E. APB Address and Control Generator

This section is responsible for generating all other outputs in the APB side including PADDR, PWRITE, and PENABLE. This section takes input from state machine, AHB master side & some internal signals. F. AHB Transfer Output Generator

This section is in the charge of generating transfer done output HREADYOUT and response output HRESP signals.

Figure 2

AHB2APB Processor interface

A.

State Machine

This is a very vital block for the interface. It determines when different output signals will come in effect. Two most significant signal of this block is nextstate and currentstate both of which are 3 bit signals. To generate nextstate some other signals are needed like HWRITE, registered version of HWRITE (rghwrite), accept and currentstate as well. Nextstate and currentstate will be used as internal input signals in other blocks. B. Write Output Generator

Figure 3

FSM for AMBA AHB

A DFF is used to implement this sub-block. It will take HCLK, HRESET and HWDATA as input and drive the output to PWDATA. Asynchronous reset is used here. C. Read Output Generator

Another DFF is used to implement it. It will take HCLK, HRESET and PRDATA as input and drive the output to HRDATA. It uses asynchronous reset.
Figure 4 FSM for AMBA APB

IV.

STRUCTURE OF AMBA AHB PROTOCOL

The Advanced high performance bus AHB busmatrix of ARM consist of the input stage, decoder, multiplexor, and arbiter and output stage. Fig.5 shows the overall structure of the AHB busmatrix. The input stage contains number of masters and output stage contains number of slaves to perform operation. The input stage is responsible for holding the address and control information. Before an AMBA AHB transfer can commence, the bus master must be granted access to the bus. This process is started by the master asserting a request signal to the arbiter. Then the arbiter indicates when the master will be granted use of the bus. A granted bus master starts an AMBA AHB transfer by driving the address and control signals.

control activities in the table 1.The size of the transfer are indicated by the 3-bit control signals HSIZE [2:0]. The size is used in conjunction with the HBURST [2:0] signals to determine the address boundary for wrapping bursts. B. Protection Control

The protection control signals, HPROT [3:0], provide additional information about a bus access and are primarily intended for use by any module that wishes to implement some level of protection. For bus masters with a memory management unit these signals also indicate whether the current access is cacheable or bufferable Not all bus masters will be capable of generating accurate protection information, therefore it is recommended that slaves do not use the HPROT signals unless strictly necessary [1]. HPROT[3:0] XXX0 XXX1 XX0X XX1X X0XX X1XX 0XXX 1XXX
Table 3

DESCRIPTION Opcode fetch Data access User access Privileged access Not bufferable Bufferable Not cacheable Cacheable
Protection signal encoding

VI.

SIMULATION ENVIRONMENT

Figure 5

AMBA AHB structure

V.

AMBA AHB CONTROL SIGNALS

AMBA AHB supports various control signals of different bus width. A. Transfer Size
Figure 6 Simulation environment

HSIZE[2:0 ] 000 001 010 011 100 101 110 111

SIZE 8 bits 16 bits 32 bits 64 bits 128 bits 256 bits 512 bits 1024 bits
Table 2

DESCRIPTION Byte Half word Word 4- Word line 8- Word line Size encoding

The AMBA processor interface is designed to interface between AMBA Advanced High performance Bus and Advanced Peripheral Bus. The entire design process involves the two master-slave communication. AMBA AHB slave-AMBA APB master AMBA APB master-AMBA APB slave Initially the AHB slave interface is simulated and next we have designed APB master and slave interfaces. The APB slave is connected to two slave devices such as RAM and Register. They are accessed through the PSELx signal.

The important control signals are listed along with their

VII.

SIMULATION RESULTS

Figure 7

Simulated waveform of AMBA AHB Slave module

Figure 8

Simulated waveform of AMBA APB Master module

Figure 9

Simulated waveform of AMBA APB Slave module

VIII.

SYNTHESIS REPORT OF THE DESIGN 3s400pq208-5 Spartan 3 XC3S400 PQ208 -5 215

[6] [1] [2] [3] [4]

REFERENCES
AMBA Specification (Rev 2.0). Samir Palnitkar, Verilog HDL A Guide to Digital Design and Synthesis. Second Edition Vani.R.M and M.Roopa Design of AMBA Based AHB2APB Bridge IJCSNS VOL.10 No.11, Nov. 2010. Rishabh Singh Kurmi, Shruti Bhargava, Ajay Somkuwar, Design of AHB protocol block for Advanced Microcontrollervol.32- No.8,Oct2011 Iqbalur Rahman Rokon, Toufiq Rahman, and Ahsanuzzaman, Hardware Implementation of AMBA Processor Interface Using Verilog and FPGA ICEECE`2011 Pattaya Dec 2011. AdvancedMicrocontrollerBusArchitecture (AMBA) http://en.wikipedia.org/wiki/Advanced_MicrocontrollerBus_Architect ure Rohit Hardia, Prof.Jai Karan Singh, Prof.Mukesh Tiwari, and DESIGN AND SIMULATION OF A TYPICAL HIGH PERFORMANCE AHB RECONFIGURABLE MASTER FOR ON CHIP BUS ARCHITECTURE USING VERILOG HDL (IJAER) 2011, Vol. No. 2, Issue No.V, November ISSN: 2231-5152. ARM. AMBA Open Specifications. http://www.arm.com/products/system-ip/amba/amba-open specifications.php

Device Utilization Family Device Package Speed Design Statistics IOs Cell Usage GND INV LUT 1 LUT 2 LUT 3 LUT 4 MULT_AND MUXCY MUXF5

[5]

1 5 50 12 20 124 15 73 21

VCC XORCY LATCHS FDC FDCE CLOCK BUFGP IBUF OBUF

1 76 94 5 89 1 1 42 132

[7]

[8]

Timing Summary Speed grade -5 Minimum period 7.059ns Maximum Frequency 141.66MHz Minimum input arrival time before clock 5.072ns Maximum output required time after clock 11.217ns Maximum combinational path delay 8.666ns
Table 4 Final Synthesis report

IX.

CONCLUSION AND FUTURE WORK

The Design of AMBA AHB interface module is simulated using Modelsim Simulator 6.3f tool .The major part of the design includes the State machine coding is done in Verilog HDL [2]. AMBA Protocol supports three different bus interconnection based on their performance we can interface slow speed and high speed peripherals by designing a processor interface module for different bus interconnection scheme [5]. Still, there is some room for improvement in this paper. To name a few: burst transfer between AHB and APB are not shown here. The size of the data bus of AHB and APB signals and the size of RAM and register memory are same (32 bits). In future we can develop the interface for burst transfers. Also, we want to use RAM and register with different memory size in comparison with AHB and APB data bus size.