Laborator 5 Counters and Frequency dividers

Necessary Hardware and Software Nexys2 Development Boards + USB-Mini Cable ISE 12.2 or newer software

Laboratory exercises
1. Four-bit counter. The initialization problem. a. Create a new project on C:\Temp targeting the FPGA device present on the development board you have. Name the project Cnt4bit_group_name, b. Create a top-level module with the name and ports shown below:

Figure 1. Top-level module for a simple four-bit counter NOTE: Set the mode of the output port Q to wire. Create an internal signal with the mode reg and name it Q_reg. Assign Q to Q_reg. The code of the module is similar to the code of a shift register: reg [3:0] Q_reg; assign Q = Q_reg; always @ (posedge CLK) Q_reg <= Q_reg+1; Create a testbench for the module. Name it Test_cnt4bit. The testbench will contain as stimulus only the clock signal, with a frequency of 25..50MHz. In order to create a clock signal look to Laboratory 4, point 1.b. Simulate the design using behavioral simulation. Note that the output will show unknown values (4bXXXX) only. However, if you simulate the design using post-translate or post-route simulation, the output will show a correct counter behavior, after 100ns.

Also, if you apply the ucf constraints (connect CLK to BTN0, Q to LED<3:0> and dont forget about the NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; constraint), the board will show correct counter behavior. Why is this happening? - When downloading a design to an FPGA, all of the internal registers are initialized to 0, if not otherwise specified. Therefore the counter will start from 0 and functions correctly - This is also the role of the glbl module found in Post-translate and Post-route simulations, to INITIALIZE the internal registers. Its effect takes 100 time units. This is also the reason for the #100; statement in the testbench template. Therefore, do not remove the #100; statement from the testbench code. Also write any stimulus after the #100; statement. However, in behavioral simulation the glbl module is not present and because the Q_reg signal is uninitialized, the behavioral simulator will consider that Q_reg has an unknown value. Obviously, unknown + 1 = unknown c. Change the code of the counter module to initialize Q_reg as shown below: reg [3:0] Q_reg= 4b0101; If the design is simulated using either Behavioral, Post-Translate or Post-Route simulation, the counter will start from 5 (4h5) and will work correctly. Also, if the design is downloaded to the board, the counter will start from 4h5. Note that ISE implementation tools take into account the initial values. However, counters often need to be initialized in runtime. This is usually done using Reset and/or Load signals. 2. Eight-bit reversible counter with synchronous Load and asynchronous Reset. a. Create a new project on C:\Temp targeting the FPGA device present on the development board you have. Name the project Cnt8bitUnD_RL_group_name. b. Create a top-level module with the name and ports shown below:

Figure 2. Top-level module for the 8-bit reversible counter with asynchronous reset and synchronous load Note: Und is the signal setting the count direction (Up not Down). The counter counts up when UnD = 1b1, otherwise counts down. Also use Q in wire mode and define an internal reg mode Q_reg signal. The code of the counter is very similar to the code of the eight-bit shift register with reset and load, only the operation on the output changes: always @ (posedge CLK or posedge Reset) if (Reset) Q_reg <= 8h00; else if (Load) Q_reg <= Din; else if (UnD) Q_reg <= Q_reg + 8h01; else Q_reg <= Q_reg 8h01; c. Create a testbench for the module with the stimulus shown below: Reuse the testbench code written at Lab 4, points 1.b) and 2.c)

Figure 3. Testbench for the cnt8UnD_RL module

Notes: - Reset and UnD have to be initialized to 1 instead of 0 - Wait until Q rolls over counting up means that the testbench has to wait until Q, counting up, becomes 8hFF then 8h00 (+ one more clock period, because the value of Q will be visible by other component only at the next positive clock edge). Consequently, Wait until Q rolls over counting down means that the testbench has to wait until q, counting down, becomes 8h00 then 8FF (+ one more clock period). This can be achieved in the testbench code by waiting for the values of Q, as shown below: //wait until Q rolls over @ (Q == 8hFF); @ (Q == 8h00); @ (posedge CLK); Similarly the code of the testbench for waiting until Q rolls over counting down can be written. Analyze the circuit versus the testbench stimulus in Figure 3 and describe its behavior by answering to the questions in the table below! Simulate then the design using behavioral (or post-translate) simulation, and check your answers versus the simulation results! Table 1. Eight-bit reversible counter analysis questions Answer after Question analyzing the circuit 1. What will be the value of Q after Clock Edge 4? 2. What will be the value of Q after Clock Edge 5? 3. What will be the value of Q after Clock edge 7? 4. What is the value of M, i.e. one clock period after Q rolls over (i.e. becomes 8h00), counting up? 5. What is the value of N, i.e. one clock period after Q rolls over (i.e. becomes 8h00), counting down?

Answer after simulating the circuit

Note: The easiest way to determine the value of M and N is to count the number of clock periods. This can be done in the testbench by using another variable and a separate initial statement in conjunction with a forever loop, as shown below:

//at the signal declaration area integer i; initial begin i = 0; @ (negedge Reset); forever @ (posedge CLK) i = i+1; end; Note that in a testbench all of the initial statements are executed simultaneously, only once Apply the ucf constraints for the board and try the functionality of the design on the board. Connect: CLK to btn0 Reset to btn1 Load to btn2 UnD to btn3 Din to the switches Q to LEDs 3. Decode and display the outputs of the eight-bit counter on the seven-segment display a. Create a new project on C:\Temp targeting the FPGA device present on the development board you have. Name the project Cnt8bit_ssg_group_name b. Create a top-level module and name it Cnt8bit_ssg. Connect the components according to the figure below. Reuse the cnt8UnD_RL counter from point 2 b_.The source file for the Ssg_decoder module can be found in the /Lab3 or /Lab5 folders:

Figure 4. Top-level module schematic diagram for the counter connected to the sevensegment decoder

c. Apply the ucf constraints to the design. Connect: - SW to the switches, AN to the anodes and SEG to the seven-segment signals - SYSCLK to the system clock of the board. Do not use the CLOCK_DEDICATED_ROUTE constraint for SYSCLK! - BTNCLK to BTN0. Use the CLOCK_DEDICATED_ROUTE constraint for BTNCLK! - Reset to BTN1, Load to BTN2 and UnD to BTN3 Try the functionality of the design on the board d. Change the code of the counter to count in BCD code i.e in decimal only! 4. Use a frequency divider to make the counter to run automatically The SYSCLK can be also sourced to the cnt8UnD_RL counter. However the SYSCLK frequency is 50MHz, so the counter value will not be visible on the seven-segment display. Therefore the frequency of the SYSCLK has to be divided to 1..10HZ. This can be achieved, for example, by using the Freq_Div_gated divider module. The source of the module can be also found in the /LAB5 folder. a. Create a new project on C:\Temp targeting the FPGA device present on the development board you have. Name the project Cnt8bit_div_gated_ssg_group_name

b. Create a top-level module and name it Top_Cnt8bit_div_gated. Connect the components according to the figure below.

Figure 5. Top-level module schematic diagram for the counter with divided clock c. Apply the ucf constraints to the design. Connect: - SW to the switches, AN to the anodes and SEG to the seven-segment signals - SYSCLK to the system clock of the board. Do not use the CLOCK_DEDICATED_ROUTE constraint for SYSCLK! - CLK_OUT to LED0 - Reset to BTN1, Load to BTN2 and UnD to BTN3 Try the functionality of the design on the board d. Override the OUT_FREQUENCY_HZ parameter for the Freq_Div_gated divider with some other value (for example, 2) and the REFRESH_RATE parameter for the Ssg_decoder module (for example, 100) and download the design to the board again. What changes in the functionality? Note that Place-and-Route returns a warning message: Route:455 - CLK Net:CLK_OUT_OBUF may have excessive skew because 4 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

This is due the fact that the CLK_OUT signal was internally generated i.e. divided from SYSCLK and no dedicated clocking components neither dedicated clock pins were used for CLK_OUT. If CLK_OUT was generated using combinational circuits, this is also referred as GATED CLOCK. It is not recommended to use gated clocks in the design because: - Combinational circuits can present hazard i.e. glitches that can lead to extra clock edges in the circuit - Gated clocks can not use the FPGA clocking resources; therefore the timing delay on the clock nets can be very large, exceeding the timing delays of other signals. Remember that digital circuit analysis for circuits with a single clock is based on the assumption that the clock signal arrives to every circuit at the same time i.e. faster than the other signals, assuming that the clock signal is not intentionally delayed between components The recommended design practice is to use the main clock (in our case: SYSCLK) for every component in the same clock domain. For components that run at lower frequency use a CLOCK ENABLE (CE) signal and enable component operation based on CE. 5. Eight-bit counter with clock enable a. Create a new project on C:\Temp targeting the FPGA device present on the development board you have. Name the project Cnt8bit_CE_ssg b. Create a new module and name it Cnt8bit_CE. Reuse the code from the cnt8UnD_RL module. Add the CE port as input and enable counting only if CE=1b1. The symbol of the Cnt8bit_CE module can be found in the figure below. c. Create a top-level module and name it Top_Cnt8bit_CE. Connect the components according to the figure below. The source for the Freq_Div module can be also found in the /Lab5 folder:

Figure 6. Top-level module schematic diagram for the counter clock enable d. Apply the ucf constraints to the design. Try the functionality of the design on the board e. Note that Led0 does not lights up anymore. What is the difference between the outputs of Freq_Div_gated and Freq_Div? Create a testbench and include both frequency dividers in the testbench. Use a small ration for CLK_FREQUENCY_HZ/OUT_FREQUENCY_HZ in order to avoid long simulations (for example, less than 100). Simulate the two frequency dividers in order to compare their outputs!