Low Noise Amplifier

Spring 2011: Radio Frequency Integrated Circuits (TSEK03) 1/18
Electrical Engineering Department (ISY), Linkping University

Tutorial-1
Low Noise Amplifier (LNA) Design

Objective:
Low noise amplifiers are one of the basic building blocks of any communication system.
The purpose of the LNA is to amplify the received signal to acceptable levels with
minimum self-generated additional noise. Gain, NF, non-linearity and impedance
matching are four most important parameters in LNA design.
The objective of this tutorial is to outline the basic tradeoffs between different amplifying
topologies with respect to the gain, NF and impedance matching. After this comparison it
is concluded that inductor degenerated common source topology gives the best
performance to meet the gain, NF, and impedance matching goals with minimum power
consumption in case of narrow band designs.
Goals:
After this tutorial, students should be able to
Calculate the gain, input impedance and NF of common gate, common source,
and shunt feedback amplifiers.
Understand the basic equations and tradeoff between different LNA topologies.
Perform the calculation for inductor-degenerated common source topology and
understand the tradeoff between the gain, NF, and impedance matching.
A supplement tutorial LNA lab is also part of this course which guides through
different analyses to design a practical LNA.
V
DD

R
L

V
GS

x(t)
NMOS
DC-bias

Problem-1.1 (Tutorial)
NMOS transistor is racing horse in LNA design arena due to its higher mobility compared to
PMOS transistors. Calculate the IP3 of NMOS CS amplifier shown below. Assume that NMOS
transistor is in saturation.

a) Consider simplified square law model. (HW)
2
( )
2
n
D GS T
K
I V V =
b) Consider the short channel effects as:
2
1
( )
2 1 ( )
,
0.2 0.1
n GS T
D
GS T
GS T
K V V
I
V V
Velocity Saturation Mobility Degradation
V V V and V

(
=
(
+

=
= =

Observe that this transistor is not a very short channel device as << 1.
c) What conclusion can be drawn from part b) about the bias current and transconductance
of the transistor for higher IP3?

Solution:

a). Homework answer:
= 3 IP

b).
) ( ) ( ) ( ) (
3
3
2
2 1 0
t x t x t x x y + + + =
--------------(1)
3
1
3 2 1
3
4
cos cos ) (
= + =
IP
A t A t A t x

( )
) ( 1 2
2
T GS
T GS n
D
V V
V V K
I
+

Here we assume a small signal x(t) around the bias (V
GS
V
T
), so

( ) [ ]
)) ( ( 1
) (
2
2
t x V V
t x V V K
I
T GS
T GS n
D
+ +
+
=

we define V V V
T GS
= --------------- Bias voltage
[ ]
1 ) ) ( (
) (
2
2
+ +
+
=
V t x
V t x K
I
n
D
--------------------------------------------------------------(2)
( )
( ) V t x
V t x R K
V R I V
L n
o L D o
+ +
+
= =
) ( 1
) (
2
2
and we put K
R K
L n
=
2

1 << so ( ) V t x + ) ( is also small
2
1
1
1
=
+
if is small
( )
( )
2
) (
1
) ( 1
1 V t x
V t x
+

+ +

( )
( )
|
\
|
+
+ =
2
) (
1 ) (
2
V t x
V t x K V
o

( ) ( )
2
) ( ) (
3 2
K
V t x V t x K V
o
+ + =
) (
2
) (
2
3
) (
2
3
2
2
3 2
2 3 2
t x
K
t x V
K
K
t x V
K
V K V
K
V K V
o

|
\
|
+
|
\
|
+ =
-----------------------------(3)

Comparing (1) & (3)
2
1
2
3
2 V
K
V K =

, V
K
K =
2
3
2
,
2
3
K
=
|
\
|

=

= =
2
2
3
1
3
3
2
3
8
2
2
3
2
3
4
3
4
V
V
K
V K v K
A
IP

V V
A
IP
=
3
16 2
3
8
3

As 1 << ,
2
3 V can be gnore.

( )

T GS
IP
V V V
A

=
=
3
16
3
16
3
-------------------------------(4)

Please, note that this formula only holds for small value of .

From equation (4), a large gate bias voltage (V
GS
V
T
), improves IP3.

Put
-1
V 0.1 V, 2 . 0 = = V

Volts A
IP
27 . 3
1 . 0
2 . 0
3
16
3
= =

|
|
|
|
\
|
=
mW
V
dBm IIP
rms
1
50
log 10 ) ( 3
2
where
2 2
3 IP
pp
rms
A
V
V = =
dBm mW dBm IIP 20 1
50
1
.
2
2
27 . 3
log 10 ) ( 3 =
|
|
\
|
(
(
\
|

c). From
( )
) ( 1 2
2
T GS
T GS n
D
V V
V V K
I
+
, the NMOS transconductance can be found as

( )
( )
2
2
) ( 1
) ( ) ( 1 ) ( 2
2
T GS
T GS T GS T GS n
GS
D
m
V V
V V V V V V K
V
I
g
+
+
=

By comparison of those two formulas we find

2 ) ( 2
) ( 1
) (
T GS
T GS
T GS
T GS
m
D
V V
V V
V V
V V
g
I
+
+
=
( is small)
and hence, (4) can be rewritten as
m
D
IP
g
I
A
3
32
3

As shown, IIP3 is decided by the ratio I
D
/g
m
which is constant for a given gate bias voltage.
Using e.g. a wider transistor does not change this ratio and only the power consumption
is increased.

g
m
V
gs

S
D
V
out

R
L

nd i
2

R
L
is noiseless
G
R
sh

sh
R n V ,
2

s
R n V ,
2

R
s

V
DD

R
L

R
sh

V
in

V
out

Z
in

R
s

(Biasing not shown)

It is preferred in current RF designs that the input of LNA be matched to 50 . The easiest way is
to shunt the gate with a resistor of 50 .
a) Calculate the gain, input impedance and NF in absence of gate noise. Assume that R
sh
=R
L

for NF derivation.
b) What are the disadvantages of shunt resistor with reference to gain and NF?

Solution:
a). (Please read assumption in the problem statement carefully)

source input to due noise Output
power noise output Total
F =
f kTR V
s
Rs n = 4 ,
2

L m
Gate
R g Gain =
f kTR V
sh
Rsh n = 4 ,
2

|
|
\
|
+
=
sh s
sh
L m
R R
R
R g A for R
sh
= R
s

f g kT i
m
nd = 4
2

2
L
m
R
g A =
Using superposition, only one noise source is considered at a time and other sources should be
shorted (voltage noise source) / open (current noise source).
2
2 2
,
2
,
2
|
|
\
|
+
=
sh s
sh
L
m Rs n Rs no
R R
R
R g V V
2
2 2
,
2
,
2
|
|
\
|
+
=
sh s
s
L
m R n R no
R R
R
R g V V
sh sh

L nd d no R i V
2 2
,
2
=
s
sh
s
sh
R no
d no R no
R no
d no R no Rs no
V
V V
V
V V V
F
,
2
,
2
,
2
,
2
,
2
,
2
,
2
1
+
+ =
+ +
=

( )
( ) ( )
2
2 2 2
2
2
2 2 2
2
2 2 2
4
4
4
4
1
sh s
s L m
s
L
m
sh s
s L m
s
sh s
sh L m
sh
R R
R R g
f kTR
R f g kT
R R
R R g
f kTR
R R
R R g
f kTR
F
+

+
+

+ =

In case of impedance match R
s
= R
sh

s m L m
s
m L
S
L S m
s
m L
R g R g
R
g R
R
R R g
R
g R
F
4
2
4
2
4
1 1
2 2
2
2
2 2 2
2
+ =
+ =
+ + =

b)
- Poor Noise Figure since R
sh
adds extra noise.
- Input signal attenuated by the voltage divider
- At high frequency, shunt L is needed to tune out C
gs

- Reduced gain.

Another approach to get 50 input impedance match is shunt feedback amplifier shown below.
g
m
V
gs

V
no,out

R
L

nd I
2

(Equivalent noise model ignoring gate noise), R
L
is noiseless
R
s

s
R n V ,
2

F
R n V ,
2

R
F

V
DD

R
L

V
out

Z
in

R
s

(Biasing not shown)
R
F

V
in

R
L

V
out

I
in

R
s

R
F

I
in

a) Calculate the gain, input impedance and NF neglecting the gate noise. The gate-drain,
gate-bulk, and gate-source capacitance can be neglected as well.
b) What are the disadvantage of shunt feedback amplifier with reference to gain and NF?

Solution:

f kTR V f g kT I
S
RS
m
nD = = 4 , 4
2 2

source input to due power noise Output
power noise output Total
V A
V
F
S
R n tot v
out no
= =
,
2
,
2
,
2

Here A
v,tot
= Gain from V
in
to V
out

Again using superposition theorem
S
F S
S
R n tot v
d no R no R no
R no
out no
V A
V V V
V
V
F
,
2
,
2
,
2
,
2
,
2
,
2
,
2
+ +
= =

Gain Calculation
( )
out F S in in
V R R i V + + =
( )
L gs m in out
R V g i V =
g
m
V
gs

V
out

R
L

R
s
R
F

V
gs

i
in

V
in

g
m
V
gs

F
R no V ,
2

R
L

R
s
R
F

V
gs

i
F
R n V ,
2

o F in gs
V R i V + =
( )
L S m L F S
F m L
in
out
tot v
R R g R R R
R g R
V
V
A
+ + +
= =
1
,

If R
F
>> R
S
& g
m
R
F
>>1
( )
( ) ( )
L m
F
S m L
L m
F
S m L
F
S
F m
F
L
tot v
R g
R
R g R
R g
R
R g R
R
R
R g
R
R
A
+
+
=
+
+ +
=
1
1
1
1
1
,

L m tot v
R g A
,

Also
L m
L F
in
R g
R R
Z
+
+
=
1

By ignoring C
gs,
we have considered real part only.

For source resistance
S S
R n tot v R no V A V ,
2
,
2
,
2
= -------------------- (1)

For feedback resistance

F F
R no R n F s gs
V V iR iR V
, ,
+ = =
( )
gs m L R no
V g i R V
F
=
,

( )
( )
S m
F
L
R n
s m L
F S
R n R no
R g
R
R
V
R g R
R R
V V
F F F
+
+
+
+
= 1
1
1
1
, , ,
Since R
F
is much larger than R
S
and R
L

( )
2
,
2
,
2
1
(
+ =
S m
F
L
R n R no R g
R
R
V V
F F
--------------------- (2)
g
m
V
gs

d no I ,
2

R
L

R
s
R
F

V
gs

i
d n I ,
2

Similarly

0
,
,
,
=
+
+ + +
F S
d no
gs m d n
L
d no
R R
V
V g I
R
V

F S
d no
S gs
R R
V
R V
+
=
,

L d no
F S
S m
F S L
d no
d no
R I
R R
R g
R R R
I
V
,
,
,
1 1

+
+
+
+
= Since R
F
>> R
S

So,
2
,
2
,
2
L
d no d no R I V = ------------------------------------------ (3)
Combining (1), (2) & (3)

s s
F
R n tot v
d n
L
R n tot v
R no
s m
F
L
V A
I R
V A
V R g
R
R
F
,
2
,
2
,
2 2
,
2
,
2
,
2
2
) 1 (
1 +
|
|
\
|
+
+ =

L m tot v
R g A =
,
, f kTR V
s
R n
S
= 4 ,
2
, f kTR V
F
R n
F
= 4 ,
2
& f g kT I
m
d n = 4 ,
2

s m s m F
s
R g R g R
R
F

+
|
|
\
|
+ + =
2
1
1 1

b)
NF g
m
R
S
& R
F
usually = 50
s
R
- Better performance than CS amplifier
- R
F
induces noise
- At higher f
a shunt inductor needed to tune out C

gs

- Broadband

Amp @ Lower frequency
- To make NF R
F
> R
S
and g
m
R
S
>> 1


Problem-1.4 (Homework)
Common gate amplifier also offers 50 input impedance match and solves the input matching
problem.

c) Calculate the gain, input impedance and NF in absence of gate noise. Neglect gate drain
and gate to bulk and gate to source capacitance.
a) What are the disadvantage of common gate amplifier with reference to gain and NF?

The disadvantages of the amplifiers discussed in Problem-2, 3 & 4 can be circumvented by using
the source degenerated LNA shown below.

a) Calculate the input impedance. This inductor source degenerated amplifier presents a
noiseless resistance for 50 for input power match. How we can cancel the imaginary
part of complex input impedance so that the LNA presents 50 real input resistance at
input port.
b) Calculate the NF in absence on gate noise. Neglect gate drain and gate to bulk and gate to
source capacitance.
c) C
gd
bridges the input and output ports. The reverse isolation of this LNA is very poor.
Why reverse isolation is important? Suggest the modification to improve reverse
isolation.

V
DD

R
L

V
S

V
out

R
s

(Biasing not shown)
L
s

L
g

V
S

R
s

L
s

L
g

i
in
V
out
i
o

g
m
V
gs

V
in

V
gs

Z
in

Reference:
For series RLC Circuit

R L
C V
C

V
in

RC R
L
C
L
R
Q
o
o
s
1 1
= = =
and
in S C
V Q V =
Solution:
a)

From model above we can write

( )
s o in s g in in
L j i
c j
i L j L j i V
+
|
|
\
|
+ + =
1
--------------- (1)
gs
in m gs m o
C j
i g V g i
1
= = -------------------------------------- (2)
Substituting (2) in (1)
( )
(
(
+ + + =
gs
s m
gs
s g in in
C
L g
C j
L L j i V
1

( )
gs
s m
gs
s g
in
in
in
C
L g
C j
L L j
i
V
Z + + + = =
1

For matching L
g
+ L
s
are canceled out by C
gs
. So at frequency of interest
( )
( )
gs s g
o
gs o
s g o
C L L C
L L
+
= = +
1 1
2

And
s
gs
m
S
L
C
g
R = = 50

Notes:
1) L
s
is typically small and may be realized by the bond wire for source.
2) L
g
can be implemented by spiral/external inductor.

b)
From part a)
( )
gs
s m
gs
s g in
C
L g
C j
L L j Z + + + =
1

V
in

R
s
L
g
+ L
s

gs
s
m
C
L
g
Z
in
V
gs

C
gs

R
L

V
in

V
out

R
s

L
s

L
g

Z
in

V
gs

The frequency of current gain equal 1

We can draw this circuit as:

Here
( ) ( )
S T S
s g o
gs
S m
S
s g o
in
L R
L L
C
L g
R
L L
Q

+
+
=
+
+
=

gs
m
T
C
g

gs
gs
S m
S o
in
C
C
L g
R
Q
|
|
\
|
+
=
1
, for match load
gs
S m
S
C
L g
R =
gs s o
in
C R
Q
2
1
=

Gain
in in gs
V Q V =
gs
out
m
V
I
g =

m in
in
m gs
in
out
m
g Q
V
g V
V
I
G = = =

m in m
g Q G =

so,
L m
in
out
R G
V
V
=
where
m in m
g Q G =

Noise Figure:
source input to due output at power noise
output at power noise Total
F =
For this calculation we ignore channel noise.
s s
s
R no
d no
R no
d no R no
V
V
V
V V
F
,
2
,
2
,
2
,
2
,
2
1+ =
+
=
L d n d no R i V
2
,
2
,
2
= f g kT i
m
d n = 4 ,
2

V
DD

R
L

V
S

V
out

R
s

L
s

L
g

V
DD

L
D

V
S

R
s

L
s

L
g

C
L

R
L
generates noise so replace
R
L
with L
D
so thats
L D
o
C L
1
=
Reverse Isolation
V
out

L
o

V
DD

L
D

R
s

L
s

L
g

C
L

V
b

(Final Design)
C
gd

L m R n R no R G V V
S S
2 2
,
2
,
2
= f kTR V
s
R n
S
= 4 ,
2
&
m in m
g Q G =
2 2 2 2
,
2 2
,
1
L m in R n
L d n
R g Q V
R i
F
S
+ =
f g kT i
m
d n = 4 ,
2
, f kTR V
s
R n
s
= 4 ,
2

2
1
in S m
Q R g
F

+ =

Notes:
- Very good NF value
- Narrow band matching
- NF with
2
Q
- The Q value is dependent upon L
g
+ L
s
, L
s
usually small so Q depends mainly upon L
g

c) Drawbacks:
i)

The C
L
can be considered the input capacitance of the following mixer or filter.

ii)

Reverse isolation depends upon capacitance between output and input.
To make it less the cascode architecture can be used.


Problem-1.6 (Homework)
Fill-in the Table below, use the data from Problem-1.2, 1.3, 1.4 and 1.5

Type of LNA Z
in
Noise Factor Gain NF (dB)
Shunt Resistor R
sh

4
2
m S
g R
+
2
m L
g R

Common Gate
Shunt Feedback
Source Degenerated

a) Calculate the NF for all above amplifiers. Assume =2, g
m
= 20mS, Rs = 50, R
F
=
500, and Q
in
= 2.
b) Which is the best topology for Narrow Band LNA design at high frequency?

Real Design: We will design the inductor-source-degenerated LNA shown in Fig below to meet
the specification outlined for IEEE802.11b standard. The first cut approximate values are
calculated as a starting point for simulation.

LNA Specification:
NF < 2.5 dB, Gain > 15dB, IIP3 > -5dBm, Centre Frequency = 2.4 GHz
Load Capacitance = 1pF
Technology Parameters for 0.35um CMOS:
2 2 2
0.35 , 170 , 4.6 , 58 , 2
eff n ox ox p ox
L m C A V C mF m C A V = = = = =
85 . 0 , 395 . 0 , 4 = = = C

Solution:
Technology 0.35m CMOS:
= = =
= =
m L m mF C
V A C V A C
eff ox
ox p ox o

35 . 0 , 2 , 6 . 4
, 58 , 170
2
2 2

85 . 0 , 395 . 0 , 4 = = = C
Design Parameters

NF < 2.5 dB, Gain > 15dB, IIP3 > -5dBm, f
0
= 2.4 GHz

Component Description
L
s
Matches input impedance
L
g
Sets the Resonant Frequency f
o
= 2.4 GHz
M
3
Biasing transistor which forms current mirror with M
1

L
d
Tuned output increases the gain and also work as band pass filter with C
L

L
D

R
REF

L
s

L
g

M
2

V
out

M
1

C
L
= 10pF
M
3

R
BIAS

R
S
C
B

V
in

V
DD

M
2
Isolates tuned input from output to increase reverse isolation, also reduces the effect of
Miller capacitance C
gd

C
B
BC blocking capacitor chosen to have negligible reactance at f
o
= 2.4 GHz
R
BIAS
Large enough so that its equivalent current noise is small enough to be ignored. (Dont
consider it as voltage noise source. Why??)

Design Procedure
Size of M1:
From the noisy two-port theory (see the course book or lecture notes) the optimal input matching
and minimum noise figure is given by:
( )
= =
50
1
1
5
2
C C G
gs opt
---------------------- (A)
( )
T T
C C F
3 . 2 1 1
5
2
1
2
min
+ = + =
------- (B)
From (A)
mm L C C W pF C
eff OX gs M gs
5 . 2 2 / 3 7 . 2
1

( not feasible huge size, huge
power ! )
Conclusion: We will not go for the global minimum noise figure. Instead, we will look into the
constraint power design approach.
Solution:
LNA NF will be optimized for given power which is higher than the global minimum NF.
In this case the optimum transistor width is given by:
S ox eff o
opt
R C L
W
3
1
=
while the minimum power-constraint NF :
T
p
T
p
F F
6 . 5 1 4 . 2 1
min, min,
+ = + = --------------- (C)
(B) is the global minimum noise figure.
(C) is the minimum NF for a given power consumption.
In practice the difference is usually 0.5dB to 1dB (no big deal for Lower Power)

Step - 1:
mA I I 5
2 1
= = (Limited Power consumption)
Step - 2:
S ox eff
M
R C L
W
0
1
3
1
=

o
M
m
W

=
50 6 . 4 35 . 0 3
1
1

= =
= =
= =
GHz f f
m L V A C
m mF C R
o o o
eff ox n
ox S
4 . 2 , 2
, 35 . 0 , 170
, 6 . 4 , 50
2

4
1
10 9 . 3

=
M
W
m W
M
390 10 9 . 3
4
1
= =

Step - 3:
ox eff M gs
C L W C
1 1
3
2
=
pF m C
gs
41 . 0 6 . 4 35 . 0 390
3
2
1
= =
1
1
1
2
DM
M
ox n m
I
L
W
C g |
\
|
=
or
T GS
DM
m
V V
I
g
=
1
1
2
(for short channel model)
V mA m g
m
43 5
35 . 0
390
170 2
1
=
|
\
|
=
Sec rad G
pF
V mA
C
g
gs
m
T
104
41 . 0
43
1
1
= =

Assuming 2 =
Now
T
o
F
6 . 5 1
min
+ =
dB
G
G
F 55 . 2
104
4 . 2 2
6 . 5 1
min
+ =

dB NF 55 . 2
This NF is very close to the specified value. If we increase I
D
then
T
should increase slightly as
well and hence, a lower NF value can be achieved at expense of more power.
Step - 4:
Source and gate inductance such that they cancel C
gs
and set 50 input impedance
Sec rad G f
o o
15 4 . 2 2 2 = = =
From previous problem
S T
gs
S m
d Transforme S
L
C
L g
R R = =

nH
G
R
L
T
S
S
5 . 0
100
50
= =

nH L
S
5 . 0 = can be implemented using the bond wire.
Now
1
2
0
1
gs
s g
C
L L
= +

( )
nH
pF G
L L
s g
81 . 10
41 . 0 15
1
2
=
= +
nH L
g
10
Step - 5:
pF C
C
L
L
L o
d
1
1
2
= =

( )
nH
pF G
L
d
4 . 4
1 15
1
2

=
nH L
d
4 . 4 =
Step - 6:
Size of M3 is chosen to minimize power consumption
mA I k R m W
REF M
6 . 0 2 , 70
3 3
= = =

= k R
BIAS
2
(Large enough so that its equivalent current noise can be neglected)
pF C
B
10 = ( 6 . 6
C
X so good value @ 2.4G = = 6 . 6
2
1
B o
B
C f
X
)
Step - 7:
Size M2 = M3
so that they can have shared drain area.
(Note: You will simulate same LNA circuit in LAB # 2)

Low Noise Amplifier

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Low Noise Amplifier

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Spring 2011: Radio Frequency Integrated Circuits (TSEK03) 1/18

Electrical Engineering Department (ISY), Linkping University

, the NMOS transconductance can be found as

a shunt inductor needed to tune out C

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