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S.-K.Chung Abstract: Analysis and design of a phase-locked loop (PLL) is presented for the power factor control of grid-connected three-phase power conversion systems. The dynamic characteristics of the closed loop PLL system with a second order are investigated in both continuous and discrete-time domains, and the optimisation method is discussed. In particular, the performance of the PLL in the threephase system is analysed under the distorted utility conditions such as the phase unbalancing, harmonics, and offset caused by nonlinear loads and measurement errors. The PLL technique for the three-phase system is implemented in software of a digital signal processor to verify the analytic results, and the experiments are carried out for various utility conditions. This technique is finally applied to the grid-connected photovoltaic power generation system with the current-controlled PWM inverter as a subpart for generating the current reference of the inverter. The experimental results demonstrate its phase tracking capability in the three-phase grid-connected operation.

Introduction

Grid-connected operation is often utilised to increase the usability of the local power generation systems using the photovoltaic or wind energy that cannot provide a constant power in time and region [l]. The power factor control is known as one of the most important techniques in connecting the utility grid because the unity power factor ensures perfect transmission of generated power without the circulating energy [l]. It is necessary for the power factor control to detect the accurate phase information of the utility voltages. Therefore, the phase-locked loop (PLL) can be considered to be an important part of grid-connected power generation systems. The PLL technique has been used as a common way of recovering the phase and frequency information in electrical systems [2, 31. In the area of power electronics, the PLL techmque has been adopted for the speed control of electric motors [4, 51. This is also available for generating the current references synchronised with the utility voltages in the power conversion system. A simple method of obtaining the phase mformation is to detect the zero crossing points of the utility voltages [2]. However, since the zero crossing points can be detected only at every half-cycle of the utility frequency (i.e. 120 times per second), the phase tracking action is impossible between the detecting points, and fast tracking performance cannot be achieved. Another method is the technique using the quadrature of the input waveform shifted by 90 degrees [2]. This technique is often used in the various applications for the detection of the phase or

0IEE, 2000 IEE Proceeukgs online no. 2oooO328 DOf 10.1049/ipepa:20000328 Paper fmt received 22nd July 1999 and in revisad form 20th January 2000 The author is with the Department of Control and Instrumentation Enginering, Research Institute of Industrial Technology, Gyeongsang National Univers i t y ,900 Gazwa-Dong, chinjy Kyungnam 660-701, Korea

IEE Proc-Electr. Power Appl., Vol. 147, No. 3, May 2000

angular position [6-81. In three-phase systems, the dq transform of the three-phase variables has the same properties with t h s technique, and the PLL can be implemented by using the 4 transform and proper design of the loop filter. This paper describes the characteristics of the PLL using the dq transform of the three-phase variables and discusses , the proper design method. In particular, the performance of the PLL is analysed and tracking errors are derived for the distorted utility conditions, such as the phase unbalancing, harmonics, and offset. In addition to analytical studies, the experimental verifications are carried out using the digital signal processor (DSP) system under various uthty conditions. The important considerations are thus provided for the design of the PLL in the three-phase grid-connected operation. Finally, the three-phase PLL technique is applied to the photovoltaic power generation system connected to the three-phase utility grid.

loop filter

VCO

1 1

utility j voltage;

Vas

'at id

t v~

I

I reference

System descriptions

Fig. 1 shows the current reference generator of the threephase inverter using the PLL, whch tracks the phase of the utility voltage. In t h s system, the utility voltage can be represented as:

213

Authorized licensed use limited to: THE LIBRARY OF CHINESE ACADEMY OF SCIENCES. Downloaded on April 10,2010 at 08:15:15 UTC from IEEE Xplore. Restrictions apply.

cos

(e + F)

where Kp and z denote the gains of the PI 1 closed loop transfer function is rewritten i form of the second-order loop as:

where vdcs = [vu vb, vJT. If the utility voltage is balanced, eqn. 1 can be expressed in a stationary reference frame as:

vap T s ' vabcs (2) where vap = [v, va]' and T, denotes the transform matrix given by:

where

Eqn. 3 can be rewritten in a synchronous reference frame as: where vgde matrix gven by:

'

loop filter

vco

Te(8) = (cos8

sin8

- sine

cos8

(5)

The voltage of interest is the d-axis component and derived as: V d e = E, sin S

=e (6) where E, = -V, and 6 = 8 - 8. The angular frequency can be represented as:

where K f denotes the gain of the loop filter. If it is assumed that the phase difference 6 is very small, eqn. 6 can be linearised as:

Since the PLL is implemented in a digital manner using a DSP, the discrete-time model is more useful than the continuous-time model. The discrete-time model is shown in Fig. 3. The block Kdz) is the z-transform of the loop fdter and the voltage-controlled oscillator (VCO). The closed loop transfer function can be represented as:

e E , S (8) Hence, the PLL output 6 can track the phase of the utility voltage by the proper design of the loop fdter. The current reference in phase the utility voltage can be produced as:

i:bcs

TF1 . TF1(8)

'

i:de

(9)

where For the second-order loop using the PI loop filter, Kdz) can be obtained as:

K~(z = ) Kp3

Closed loop system

z(z - a)

( z - 1)2

domain

Fig. 2 shows the linearised model of the system described in Fig. 1. The closed loop transfer function of t h s system can be represented as:

where c t = 1 - TIT and T denotes the sampling time. The transfer function of the discrete-time system can be derived by substituting eqn. 14 into eqn. 13 as:

H c ( z ) = Hc,

. z2 - az + b

a=

2 E,Kpa 1 EmKp

z(z -a)

where

Hcm

where O(s) and 6(s) denote the Laplace transform of 8 and 8, respectively. There are various methods to design the loop fdter. The second-order loop is commonly used as a good trade-off of the fdter performance and system stability [2]. The proportional-integral (PI) loop filter for the

214

EmKp 1 E, K p 1 b= 1 EmKp

=

+ +

Fig. 4 shows the root loci of the closed loop system. When T > 22, the closed loop system is unstable if the open loop zero a is located at the outside of the unit circle.

IEE Proc.-Electr. Power Appl.. Vol. 147, NO. 3, May 2000

Authorized licensed use limited to: THE LIBRARY OF CHINESE ACADEMY OF SCIENCES. Downloaded on April 10,2010 at 08:15:15 UTC from IEEE Xplore. Restrictions apply.

bandwidth. However, the use of hgher bandwidth does not provide better results in all conditions. In some practical cases such as the distorted utility, the traclung error increases as the bandwidth increases. Therefore, the selection of the bandwidth is a compromise between various factors, which will be discussed in the next Sections.

4 Error analysis for distorted utility

In practice, the utility voltage is not pure sinusoid but is distorted by the various factors such as the nonlinearities of the load and measurement devices and by the signal conversion errors, whch results in the phase unbalancing, harmonics, and offset. The distorted utility causes various types of the error in the PLL system.

4. I Phase unbalancing The utility voltage considering the unbalanced phase can be given as follows: U , , =v , cos 0 (18)

In the design of the loop filter, it is desirable that the dynamic performance should satisfy the fast tracking and good fdtering characteristics. However, both requirements cannot be satisfied simultaneously because the two conditions are inconsistent. Therefore, a trade-off is required in the design. One of the most widely used techniques is the Wiener method, which is known as the best optimisation method [2]. By using this method, the transfer function for the second-order loop is given as:

U,, =

Vm(l

+ y)cos (0 +) ; 2

(20)

where /3 and y are constants. The d-axis voltage after the 4 transform using eqns. 2-5 can be derived as:

+P+r (sinocosi + c o s o s i n o 6

^>

1

+ 6 = 26,

(22)

From eqn. 12, the damping ratio can be derived as 5 = 0.707. The closed loop bandwidth of the PLL can be determined by using the stochastic information of the signal and noise, and can be given in the Wiener method as:

Under the assumption of very small 6 and 8 eqn. 21 can be simply represented as: U& E EmS - EmEpu COS(~O where:

EPu=

where Acc, is the deviation of the frequency, P, is the power of the input signal, WOis the spectral density of the input noise, and A is the Lagrangian multiplier that determines the relative proportions of the noise and transient error.

Table 1: Steady-stateerrors for three types of input

Type of input

Step change of Steady-state error for second-order PLL Steady-state

/m

Since the d-axis voltage vde is controlled to zero by the PI type loop fdter, the resultant error caused by the phase unbalancing is given as:

~ ~ It is noted that the ~phase unbalancing produces~the error with 213 frequency component, where w is the frequency of the utility voltage as w = dO/dt. ~ ~

0

Aw/KAO),,,

0

0

A6IKf(0),,,+ AU/wn2

Ab/@?

4.2

Voltage harmonics

The steady-state performance of the PLL system is related to the shape of the input and the order of the loop fdter. In the second-order PLL, the errors for the three types of input are summarised in Table I, where A h denotes the deviations of the derivative of the frequency. It is shown in this table that the second-order PLL with the PI type loop fdter has the steady-state error for the step change of the derivative of the frequency in whch the frequency varies in time. This error can be reduced by choosing the higher natural frequency that gives the wider

IEE Proc-Electr. Power Appl.. Vol. 147, No. 3, May 2000

The source of the voltage harmonics is the nonlinearities of the measurement devices and load. The utility voltage with harmonics in the balanced condition can be represented as follows:

U,,

= Vi

COS 0

+ Vs COS 50 + V7 COS 70 + . . .

+... (0 - - 28

(24)

+v7cos7

(25)

215

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w,, = v, cos

+ v5cos5 (o + (e +):2

+v7cos7 8 + -

where V,, Vs, V7,... denote the magnitude of the harmonic components. The d-axis voltage is derived as:

'U&

3+ . . .

Y)

(27)

Experiments

5. I

= -VI

sin 6

sin68+(V11 - V I S ) sin E O + . . . (28) Therefore, the error caused by the utility harmonics can be represented as:

Ude E - V 1 S + ( V 5 - V 7 )

The proposed PLL technique is implemented using a software of DSP TMS320C31 with a clock frequency. of 40MHz [9, lo]. Fig. 5 shows the experimental set-up for testing the performance of the PLL. The utility voltages are generated by using the three-phase arbitrary voltage generator. The generated three-phase voltages are measured by the isolation transformer, and the measured signals are converted to digital values using the analogue-to-digital (AD) converters, with a resolution of 12 bits. The arbitrary voltage generator can produce various conditions of utility voltage such as phase unbalancing, harmonics, and offset.

* T ~

_ .

62

where:

Eh6

sin68

+ E h 1 2 sin 128 + . . .

(29)

host pc

7TMS320C31* L -

DSP

It is noted in eqn. 29 that the utility harmonics causes the error with the frequency components of 601, 1204 ..., which are the multiples of six times the utility frequency.

measurement display

4.3 Voltage offset The voltage offset is often produced in the measurement and data conversion processes. The utility voltage with the offset can be expressed as:

= Vm COS 8

+Vao

(30)

vde

"de

= -Vm sin b

+ V,,

sin 6 '

+ Vp, cos 8

(100 V/div)

(33)

where:

v,,

pa, +

1

vbo

- Vb,)

h

ude

Em6

+ Eo cos(@+

$0)

(34)

0 (2 rad/div)

where:

I I I I I I I I I I I

5 mddiv

Therefore, the error caused by the voltage offset can be shown as:

v,, = V,, cos 0, V,,, = 311V w, = 314 rads, 5 = 0.707

6

where:

E d , COS(8

-k

4,)

(35)

It is shown in this result that the error caused by the offset has the same frequency component as that of the utility voltage.

216

Figs. 6-8 show the transient responses of the PLL when the bandwidth are chosen as 50Hz, l O O H z , and 1kHz (i.e. U,, = 314, 628, and 6280 radls, respectively, where the damping ratio is chosen as f = 0.707 and V, = 31 1V). Under these conditions, the gains of the loop filter can be chosen as Kp = 1.43, 2.85, and 28.5, and z = 0.004506, 0.002247, and 0.0002251, respectively.

IEE Proc.-Electr. Power Appl., Vol. 147, No. 3, May 2000

that in the 1kHz bandwidth. This is the low pass filtering effect of the loop filter, and it is known that the lower bandwidth is more effective at reducing t h s type of the error.

de

(0.2

(100 V/div)

0

(2 radldiv)

2 msldiv

T

Fig.7 Responses of three-phme PLL system

v,=

w,, = 628 rads,

5 msldiv

V,cosB, V , = 3 1 1 V 5 = 0.707

(0.2

T

v, = V , cos 0, V,, = 311V w, = 628 rad/s, 5 = 0.707

2 ms/div

0 (2 rad/div)

I

I$

I

5 msldiv

U , J ,

Figs. 9-11 show the errors of the PLL under the phase unbalancing of the utility voltage. The magnitudes of the phase Figs. 10 and 11 voltages are given as 90% and 110% of the phase Fig. 9. As derived in eqn. 22, it is shown that the error that caused the phase unbalancing has a 2w frequency component. It can be also noted in this figure that the magmtude of the error is reduced as the bandwidth decreases. The error in 50Hz bandwidth is about 50% of

IEE Proc.-Electr. Power Appl.. Vol. 147, No. 3, May 2000

1

V ,

2 msldiv

=

w, = 6280 rads,

v,

COS

e, v,

5 = 0.707

= 3iiv

217

tively. These figures show the time responses and frequency spectrums. It is shown in Figs. 12-14 that the error has the frequency component of 6w as shown in eqn. 29. The low pass filtering effect can also be shown and the error caused by the harmonics decreases as the bandwidth decreases. Fig. 15 shows the frequency spectrums of the utility voltage and cos 8 . It is noted that the 5th and 7th harmonics are reduced as the bandwidth decreases. This means that the phase error caused by the 5th and 7th harmonics is reduced, and that the reproduced signal cos 8 is closer to the pure sinusoidal wave cos 8 as the bandwidth decreases.

20 dbm/div

va

2 msldiv

w, = 314 radis, 5 = 0.707

V,

20 dbmldiv

cos ii

wn=314 rad

20 dbmldiv

cos ii

w,=628 rad

2 msldiv 20 dbmldiv

Fig. 13 Errors of three-phase PLL.system under voltage harmonics V, = v,,, COS e, v , = 311v w, = 628 rads, 5 = 0.707

cos

D

I

m

wn=6280 rad

I I I I I I I I

100 Hz/div

moniesf i r variom d i i l h s

'I.

U, = 6280

2 msldiv

Fig. 16 shows the responses of the PLL under the voltage offset. The DC voltage, which is 10% of the peak utility voltage, is added to phase a. It is shown, in this figure, that the error has the same frequency component as that of the utility voltage as shown in eqn. 35. Since the frequency of the error is relatively low, the low pass filtering effect of the loop filter cannot be expected. The extremely low bandwidth can provide the filtering effect. However, this may degrade the dynamic performance.

V,=V,COSS, V , = ~ I I V radis, 5 = 0.707

The proposed PLL is applied to the grid-connected photovoltaic power generation system consisting of the PLL, the maximum power point tracking (MPPT) controller, and the current-controlled PWM inverter as shown in Fig. 17.

IEE Proc-Electr. Power Appl.. Vol. 147, No. 3, May 2000

The responses of the PLL under the voltage harmonics are shown in Figs. 12-15, where the 5th and 7th harmonics are given as 5% and 3% of the fundamental voltage, respec218

The gains of the PLL applied in this power generation system are chosen as Kp = 2.85 and z = 0.002247, which result in the closed loop bandwidth of 628 (rad/s). Fig. 18 illustrates the utility voltage, current reference, and actual current of the photovoltaic power generation system, respectively. It is shown in this figure that the current reference and actual current are in phase with the utility voltage, and it should be noted that the unity power factor operation is achieved in this system.

6

Conclusions

t

v, = V, cos 0, V,,, = 311V, w, = 314 rads,

2 msldiv

C = 0.707

F--k

array

I, I ,

control

~

The rated power of this system is 10.5 [kw].The PLL produces the current references of the current-controlled threephase PWM inverter. The phase currents of the PWM inverter are controlled to have the same phase as that of the utility voltages and flow to the AC line without circulating energies. The synchronous frame PI controller is used to control the phase current. More details on the MPPT and PWM current controllers are not presented in this paper because it is out of the main scope. The control algorithms including the PLL, MPIT, and current control are implemented in the DSP TMS320C31 system. The sampling frequency of the control system is 15kHz, which coincides with the switching frequency of the PWM inverter.

Vas

The analysis and design of the three-phase PLL system for the utility interface inverter have been presented in this paper. The dynamic modelling, characteristics and optimisation of the PLL system have been discussed. In particular, the errors caused by the distorted utility conditions have been analysed. From these studies, the design considerations of the PLL for the three-phase system have been provided. The PLL consists of two major parts, the phase detecting device and loop fdter. The phase detecting can be readily implemented by using the 4 transform in the three-phase system. The design parameters of the loop filter are the damping ratio and the natural frequency U,, which determine the dynamic characteristics.The damping ratio can be chosen by the Wiener method that has been generally accepted as the best optimisation. The bandwidth of the loop fdter is a trade-off between the filtering performance and response time. W e the higher bandwidth offers the faster dynamic responses, the traclung error is increased under the distorted utility conditions. The errors caused by the phase unbalancing and harmonics have the frequency components of 2 0 and multiples of 60, respectively, and can be considerably reduced by using the loop fdter with the low bandwidth. The error caused by the voltage offset is of the same frequency as that of the utility voltage. To reduce this error by the loop fdter, the extremely low bandwidth is required. However, this degrades the dynamic performance and is not acceptable. The presented PLL technique was finally applied to the photovoltaic power generation system with a power rate of 10.5kW. The experimental result well demonstrated the phase tracking action of the PLL in the three-phase system.

<

References

and testing of a 20-kW grid interactive photovoltaic power conditioning system in Western Australia, IEEE Trans., 1997, IA-33, (2), pp. 502-508 GARDNER, R M.: Phaselock techniques (John Wiley, 1979) RAZABI, B.: Monolithic phase-locked loop and clock recovery circuit (IEEE Press, 1996) BLASKO, V., MOREIRA, J.C., and LIPO, T.A.: A new field oriented controller utilizing spatial position measurement of rotor end ring current, IEEE PESC conference record, 1989, pp. 295-299 NOZARI, F., MEZS, P.A., JULIAN, A.L., SUN, C., and LIPO, T.A.: Sensorless synchronous motor drive for use on commercial transport airplanes, IEEE Trans., 1995, IA-31, (4), pp. 850-859 MOHAN, N., UNDELAND, T.M., and ROBBINS, W.P.: Power electronics - converters, applications, and design (John Wiley, 1995) BOYES, G.: Synchro and resolver conversion (Analog Devices Inc., 1980) HANSELMAN, D.C.: Resolver signal requirements for high accuracy resolver-to-digital conversion, ZEEE Trans., 1990, E-37, (6), pp. 556561 TMS32OC3x users guide. (Texas Instruments, 1992) SITTON, G.: A collection of functions for the TMS320C30 (Texas Instruments, 1997)

100 Vldiv

2 3 4

/.

T

5

I

I

6

7

8

5 msldiv

utwn system

9 10

219

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