08 - Delta Sigma PDF

11/25/2012
1
ECE615 Lecture 8
Mohamed Dessouky
Integrated Circuits Laboratory
Ain Shams University
Cairo, Egypt
Mohamed.Dessouky@eng.asu.edu.eg
Design of Analog Integrated
Systems (ECE 615)

Lecture 8
Delta-Sigma A/D Converters
ECE615 Lecture 8
Outline
Introduction
Oversampling
AE A/D Converters
Implementation
Converter Non-Idealities

M. Dessouky - ASU - ICL
2
11/25/2012
2
ECE615 Lecture 8
Introduction
How to obtain an ENOB of 20 bits using a 1-bit ADC!!

VLSI offers high speed devices and high density.
Such trend is also accompanied with reduced accuracy for
analog components and reduced supply, or signal range, which
causes reduced dynamic range.

Oversampling converters exchange digital complexity and time
resolution (speed) for signal amplitude resolution.
It uses what the advanced technologies offer in favor of ADCs.
3
ECE615 Lecture 8
Nyquist Rate A/D Converter
f
X
d

t
t
t
t
t
t
x
in

x
lpf

x
s

x
sh

x
q

x
d

f
X
lpf

f
X
s

f
X
in

f
o
f
s
2f
s
3f
s
4f
s

f
X
sh

Anti-Aliasing
Filter
Sample
& Hold
Quantizer
Encoder
x
in

x
lpf

x
s

x
sh

x
q

x
db

x
d

0010110
f
X
q

f
o
f
s
2f
s
3f
s
4f
s

4
11/25/2012
3
ECE615 Lecture 8
Oversampling
t
t
t
t
x
s

x
sh

x
q

x
d

f
X
d

f
X
s

f
o
f
s
f
s
/2
x
d

Sample
& Hold
Quantizer
Down-
Sampling
x
s

x
sh

x
q

x
d

Encoder
x
db

x
d

0010110
Digital LPF
f
X
q

f
s
/2
f
X
d

f
o

f
X
sh

oversampling
x
lpf

Total noise power N is spread f
S
/2 < f < f
S
/2
In-band noise power decreases
5
ECE615 Lecture 8
Oversampling In-band Noise
For sampled noise, since the total noise power N is
concentrated between f
S
/2 < f < f
S
/2, therefore the noise PSD is

The signal in-band noise is therefore

where is defined as the oversampling ratio.

Increasing the OSR by a factor of 4 will decrease the noise by
6dB, thus increasing the DR by the same amount and
increasing the effective number of bits ENOB by 1 bit!
OSR
N
f
f
N
df
f
N
N
Q
o
s
Q
f
f s
Q
o
o
= =
|
|
.
|
\
|
=
}
2
o
s
f
f
OSR
2
=
s
Q
n
f
N
S =
6
11/25/2012
4
ECE615 Lecture 8
Oversampling Antialiasing Filter
Relaxed transition band requirements for analog antialiasing
(and reconstruction) filters.
Input
Nyquist Sampling
f
S
= f
S
(minimum) = 2f
B

Oversampling
f
S
> 2f
B

7
ECE615 Lecture 8
Outline
Introduction
Oversampling
AE A/D Converters
Implementation

8
11/25/2012
5
ECE615 Lecture 8
Oversampling & Noise Shaping
D
e
c
i
m
a
t
i
o
n

t
t
t
t
x
lpf

x
sh

x
ds

x
d

f
X
d

f
X
lpf

f
o
f
s
f
s
/2
x
d

Sample
& Hold
AE
Modulator
Digital LPF
Down-
Sampling
x
lpf

x
sh

x
ds

x
d
x
d

Encoder
x
d

f
X
ds

0010110
f
X
d

f
X
sh

Oversampling
Noise is moved to high frequencis, then filtered.
9
ECE615 Lecture 8
Analog input f
in

t
x
in

x
d

Low Frequency (2f
in
)
High Resolution
High Frequency Large Noise
x
q
AE A/D Converters Time Domain
Digital LPF (averager)
Accumulates the difference between the input x
in
, and the quantized signal x
q
.
E
A/D
+

D/A
Decimation x
in

x
q

x
d

f
samp
}
Negative feedback subtracts an
analog version of the output from
the input signal.
+ Down-sampling
The integrator output is bounded only if its input (x
in
- x
q
) average is zero
D/A output tracks
the input
10
11/25/2012
6
ECE615 Lecture 8
AE A/D Converters Time Domain
Assume 1-bit A/D: 1V, i.e. =2.
For an average zero, the output
should keep switching between
1V. Duty cycle=(/2)/=1/2.
For an average of 0.6V, i.e. 0.4V
from the lower limit=(0.4/2) , the
output will be in average 4 times 1V
and 16 times 1V each 20 cycles.
Duty cycle=(4/20) /=1/5
Interpolation between 1V.
The modulator virtually adds extra
steps in the A/D.
The higher the frequency, the
higher the resolution of such
interpolation.

DAC levels
Effective modulator
levels
eff

11
ECE615 Lecture 8
AE Modulators Frequency Domain
E
H(s)
Loop filter Quantizer
x y
+

General Modulator
E
H(s)
Loop filter
x y
+

E
e
+
+
Linear Model
E
s H
X
s H
s H
Y
) ( 1
1
) ( 1
) (
: ion superposit Using
+
+
+
=
1 (STF) Function Transfer Signal ) (
) ( 1
) (
~
+
s H
s H
s H
x
) (
1
(NTF) Function Transfer Noise ) (
) ( 1
1
s H
s H
s H
e
~
+
12
Assuming non-correlated white noise e. More valid for higher number
of quantizer bits.
11/25/2012
7
ECE615 Lecture 8
AE Modulators In-Band Noise
For an n-th order integrator

or

Output Noise PSD

In-band Noise Power

n
s
s
f
s H
|
.
|
\
|
= ) (
n
s
f j
f
j H |
.
|
\
|
=
t
e
2
) (
n
s s
Q
N N yN
f
f
f
N
f H
S NTF S S
2 2
2 2
) (
1
|
|
.
|
\
|
|
|
.
|
\
|
= = =
t
( )
( ) 1 2
2
2
1
1 2
2
+

+
=
|
|
.
|
\
|
|
|
.
|
\
|
= =
} }
n
n
Q
f
f
n
s s
Q
f
f
yN
OSR
n
N
df
f
f
f
N
df S N
o
o
o
o
t
t
13
ECE615 Lecture 8
Dynamic Range

Thus, for an n
th
order modulator,
every doubling of OSR results in
an increase in DR of 6n+3 dB,
ENOB by n+0.5 bits.

At high OSRs, every increase of
filter order results in a large
increase in DR.
Increasing quantizer by 1 bit
reduces N
Q
by 6dB (1 extra
ENOB) as in a normal ADC.

( )
( )
( ) ( ) OSR n
n
N dB N
n
Q
log 1 2 10
1 2
log 10 log 10 ) (
2
+
|
|
.
|
\
|
+
+ =
t
Slight noise increase
at very low OSR
Dominant at high OSR
Oversampling Noise shaping
14
11/25/2012
8
ECE615 Lecture 8
Loop Filter: First-Order AE Modulators
E
Integrator
u v
+

E
+
+
E
+
+
1
z
e
e z u z v ) 1 (
1 1
+ =
1
1
1
) (

=
z
z
z H
1
1 ) (

= z z NTF
|
|
.
|
\
|
= =

s
fT j
f
f
e f NTF
s
t
t
sin 2 1 ) (
2
s
f
f
f NTF
t 2
) ( =
E
Integrator
u v
+

E
+
+
E
+
+
e
1
z
1
z
e z u v ) 1 (
1
+ =
1
1
1
) (

=
z
z H
causality
delay
In both cases:

In the frequency domain:

At f << f
s
:

same as obtained before!!
15
ECE615 Lecture 8
First-Order AE Modulators: NTF
Noise transfer function

First-order noise shaping
Note, during spectral analysis, the spectrum is plotted only till f
s
/2.
|
|
.
|
\
|
= =

s
fT j
f
f
e f NTF
s
t
t
sin 2 1 ) (
2
16
11/25/2012
9
ECE615 Lecture 8
Second-Order AE Modulators
e
E
Integrator 1
u v
+

E
+
+
E
+
+
1
z
Integrator 2
E
+
+
1
z E
+

e z u z e z z u z v
2 1 1 2 1 1
) 1 ( ) 2 1 (

+ = + =
|
|
.
|
\
|
= =

s
fT j
f
f
e f NTF
s
t
t 2
2
2
sin 4 1 ) (
17
ECE615 Lecture 8
First order
Output Power Spectral Density (PSD)
-20dB/decade
n
s s
Q
N N yN
f
f
f
N
f H
S NTF S S
2 2
2 2
) (
1
|
|
.
|
\
|
|
|
.
|
\
|
= = =
t
|
|
.
|
\
|
+
|
|
.
|
\
|
=
s
Q
s
yN
f
N
f
f
n S log 10
2
log 10 2 ) dB (
t
Second order
-40dB/decade
Third order
-60dB/decade
18
11/25/2012
10
ECE615 Lecture 8
Outline
Introduction
Oversampling
AE A/D Converters
Implementation

19
ECE615 Lecture 8
Linear Analysis ??
White noise assumption is only
valid for high number of
quantizer bits.
Otherwise, the model becomes
dependent on the input signal
statistics!!
Noise statistical analysis has
been done for 1
st
and 2
nd
order.
Higher order analysis is very
complicated!!
Design is based on simulation
of the non-linear model.
Simulations reveal stability
problems non-predictable with
linear analysis.
E
H(s)
Loop filter
u v
+

E
e
+
+
Linear Model
E
H(s)
Loop filter Quantizer
u v
+

Non-linear Model
!!
20
11/25/2012
11
ECE615 Lecture 8
Practical
Max. SQNR
SQNR increases with OSR and Modulator order n (noise
shaping).
Practical SQNR is less than the theoritical one.
n = AE noise-shaping order
Theoritical
21
ECE615 Lecture 8
Implementation
To reduce output noise power
Reduce quantizer step: A/D and D/A with more bits.
Increase loop filter order: Larger circuit. Stability issues.
Increase the OSR: More speed
Each of the above leads to more complex design and more
power consumption
System-level compromise depends on the application to
minimize power consumption
E
H(s) A/D
Loop filter
x y
+

D/A
( )
( ) 1 2
2 2
1
1 2 12
+
+
|
|
.
|
\
|
A
=
n
n
y
OSR
n
N
t
22
11/25/2012
12
ECE615 Lecture 8
Loop Filter
Discrete-time implementation
More popular
Design experience
Inherent sampling errors
sC
G
V
V
m
i
o
=
E
H(s) A/D
Loop filter
x y
+

D/A
E
H(z)
x
+

E
H(s)
x
+

Continuous-time implementation
No sampling errors
Less power
Clock jitter
23
ECE615 Lecture 8
SC Integrator: Inverting
( ) ( ) ( ) z V C z V C z z V C
i o o 1 2
1
2
=

( )
1
1
1
2
1
1
2
1
|
|
.
|
\
|
=
|
|
.
|
\
|
=

z
z
C
C
z
C
C
z H
( ) ( ) ( ) n V C n V C n V C
i o o 1 2 2
1 =
Same as the inverting amplifier,
but C
2
is not discharged each
cycle.
C
2
accumulates a negative
charge each |
1
such that

which gives in the z-domain

The transfer function becomes
24
11/25/2012
13
ECE615 Lecture 8
SC Integrator: Non-Inverting
( ) ( ) ( ) z V C z z V C z z V C
i o o 1
1
2
1
2

+ =
( )
1
1
1 2
1
1
1
2
1
|
|
.
|
\
|
=
|
|
.
|
\
|
=

z C
C
z
z
C
C
z H
( ) ( ) ( ) 1 1
1 2 2
+ = n V C n V C n V C
i o o
Same circuit but with different
phase control.
During |
1
, C
1
is charged.
During |
2
, C
1
is discharged in
C
2
such that

which gives in the z-domain

The transfer function becomes
25
ECE615 Lecture 8
Feedback DAC
Uses an input switched-capacitor branch to subtract the reference
voltage from the input.
If the feedback coefficient equals to the input coefficient we can
use only one sampling capacitor.
inverting
SC branch
inverting
amplifier
non-inverting
integrator
26
11/25/2012
14
ECE615 Lecture 8
Outline
Introduction
Oversampling
AE A/D Converters
Implementation

27
ECE615 Lecture 8
ADC Errors
ADC quantization error is shaped by the modulator loop.
If ADC errors (offset, gain and nonlinearity) are smaller than the
quantization error, they will affect the modulator performance.
Since the ADC already has a large quantization step (small
number of bits), usually other errors have a big margin.
Another explanation: ADC errors when referred to the input, are
divided by a large loop filter gain in the signal band. Errors are
greatly attenuated.

28
11/25/2012
15
ECE615 Lecture 8
DAC Errors
DAC errors are directly injected at
the input of the modulator together
with the input signal.
Gain and offset errors are translated
to gain and offset errors for the
modulator. Easily removed.
Modulator interpolating levels will
join consecutive DAC big steps.
DAC linearity errors (c
d
) should be of the same accuracy as the
complete ADC, i.e. <
eff
/2
Therefore, modulation greatly reduces the number of
required DAC levels but not their accuracy requirement.
Since targets large number of bits, special DAC
linearization techniques should be used.
DAC levels
with errors
Effective modulator
levels
eff

29
ECE615 Lecture 8
1-Bit Quantization
A line that connects two points is certainly
a straight line.
A 1-bit DAC (2 levels) is perfectly linear by
construction, even if level errors occur, in
such cases they are seen as gain errors.
Often used
Disadvantages:
Must use a high OSR
Modeling the quantization noise as
white noise is only valid with large
number of quantization steps. Might
generate tones in the signal band.

30
11/25/2012
16
ECE615 Lecture 8
Integrator Errors
Offset of the first integrator
contributes to an ADC offset.
Offset of following integrators are
divided by a high dc gain of
previous integrators.
Finite opamp gain, bandwidth and
slew-rate cause modifications to
the STF and NTF by adding extra
poles and zeros.
31
Such modifications cause an increase in the noise in the signal
band.
The effect of such errors are often studied using system-level
simulations.
ECE615 Lecture 8
Signal Levels
The reference voltage is the maximum obtainable voltage.
All signals are normalized to the reference voltage.
For the modulator to be realizable on the circuit level, all
normalized internal signals must be confined to 1.
E
H(s) A/D
Loop filter
x y
+

D/A
V
REF

32
11/25/2012
17
ECE615 Lecture 8
Example: Second-Order Modulator
e
E
Integrator 1
u v
+

E
+
+
E
+
+
1
z
Integrator 2
E
+
+
1
z E
+

E
Integrator 1
u v
+

E
+
+
+
e
Integrator 2
E
+
+
1
z E
+

1/2 1/2
E
+
1
z
Second
integrator
output
histogram
First
integrator
output
histogram
33
Modified architecture with smaller signal ranges at integrator outputs
ECE615 Lecture 8
Error Simulation
E
Integrator 1
u v
+

E
+
+
+
e
Integrator 2
E
+
+
1
z E
+

E
+
1
z
1/z SLEW
psf
pinf
gsf
ginf
x
y
Integrator model
Block
Non-Ideality
Modeling
34
11/25/2012
18
ECE615 Lecture 8
Building Block Specifications
Using non-ideal block models, simulate the Sub-System
Study the effect of each non-ideality on the overall performance
Deduce the block specifications

DC gain GBW/fs SR/(Vref/Ts)
35
ECE615 Lecture 8
SC Second-Order Modulator
E
Integrator 1
u v
+

E
+
+
+
e
Integrator 2
E
+
+
1
z E
+

1/2 1/2
E
+
1
z
Architecture with smaller signal ranges at integrator outputs
2
1
2
1
=
C
C
36
11/25/2012
19
ECE615 Lecture 8
SC Second-Order Modulator
Sample inputs
(integrator)
Compare outputs
Enable feedback
(inverting amplifier)
Integrate
Reset comparator
2
1
2
1
=
C
C
37
ECE615 Lecture 8
Total Noise
Circuit noise is reduced with more power consumtion.
Quantization noise is usually designed less than circuit noise (by
~3 dB).
Noise
Quantization
Noise
Circuit
Noise
Switching
Noise (kT/C)
Opamp
1/f Noise
Thermal
Noise
Opamp
Noise
38
11/25/2012
20
ECE615 Lecture 8
References
Steven R. Norsworthy, Richard Schreier, and Gabor C. Temes
(editors), Delta-Sigma Data Converters Theory, Design, and
Simulation, IEEE Press, 1997.
Franco Maloberti, Data Converters, Springer, 2008.
Bruce Wooley & Katelijn Vleugels, EE315: VLSI Data Conversion
Circuits Handouts , Department of Electrical Engineering,
Stanford University, http://www.stanford.edu/class/ee315/
David Johns & Ken Martin, Analog Integrated Circuit Design , John
Wiley & Sons, Inc., 1997.
Behzad Razavi, Design of Analog CMOS Integrated Circuits ,
McGraw-Hill, 2001.
Error Simulation: P. Malcovati et.al., Behavioral Modeling of
Switched-Capacitor Sigma-Delta Modulators, IEEE Trans. Circuits and
Systems-I: Fundamental Theory and Applications, Vol. 50, No. 3,
March 2003
39

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