Microprocessor Based Design

Assignment 1 Submitted By:NS Usman Shahid (262) DE-32(CE), Syn A

ARM Families
ARM has designed a number of processors that are grouped into different families according to the core they use. The families are based on ARM7, ARM9, ARM10 and ARM11 cores. The postfix numbers 7, 9, 10 and 11 indicate different core designs. The ascending number equates to increase in performance and sophistication. Within each ARM family, theres a number of variations of memory management, cache and TCM processor extensions. The number of families and different variations continue to expand. Following are the families of ARM.

ARM7
Based on a core of Von Neumann architecture, data and instructions use the same bus. The core is based on three stage pipeline and executes ARMv4T instruction set. ARMv4T has the implementation of ARM7TDMI and ARM9T. The most distinguishing feature of this instruction set it is Thumb Instruction set. The rest of the features include JTAG Debug, fast multiplier, EmbeddedICE macroshell. The ISA provides a very good performance-to-power ratio. A variation of ARM7TDMI is ARM7TDMI-S which is also synthesizable. ARM720T is the most flexible member of ARM7 family because it includes a Memory Management Unit which makes it to handle the Linux and Microsoft embedded platform operating systems. The processor also includes a unified 8k cache. The vector table can be relocated by setting a coprocessor 15 register. Another variation of ARM7 is ARM7EJ-S, a synthesizable, 5 stage pipeline processor which provides both java acceleration and enhanced instruction without memory protection.

ARM9
Based on a core of Harvard Architecture, ARM9 separates data and instruction busses. The core is based on a five-stage pipeline which allows it to perform at higher clock frequencies than ARM7. The first processor in ARM9 family was ARM920T which includes separate caches for data and instructions and a Memory Management Unit thereby providing the feature of virtual memory support. ARM922Tis a variation of ARM920T with half data and instruction cache size. ARM940T includes a smaller data and instruction cache and a Memory Protection Unit. This processor is designed for real-time operating systems. Both ARM920T and ARM940T execute the above mentioned v4T instruction set. ARM9E-S from this family is synthesizable with enhanced instructions, JTAG Debug, fast Multiplier, Thumb instruction set and EmbeddedICE macroshell.

Two variations ARM946E-S and ARM966E-S execute v5TE instruction set which is a superset of v4T and includes Extra instructions for changing state between ARM and Thumb, enhanced multiply instructions, extra DSP instructions, a Faster Multiply-Accumulate Unit and support to optional embedded trace macrocell, which allows the developer to trace instruction and data execution in real-time on processor. This is important when debugging applications with time-critical segments. ARM946-E includes Tightly Coupled Memory, cache and MPU. The sizes of TCM and caches are configurable. This processor is designed for use in embedded control applications that require deterministic real-time response. In contrast ARM966E doesnt have an MPU and the cache extensions but does have configurable TCMs. The latest core in this family is ARM926EJ-S which is a synthesizable processor core with Jazelle support. This processor is mostly used in 3G phones and PDAs. It also features an MMU, Configurable TCMs, and data and instruction caches with zero or non-zero wait state memories.

ARM10
ARM10 is based on Harvard architecture and extends ARM9 pipeline to six stages and supports an optional vector floating-point unit which adds a seventh stage to ARM10 pipeline. The VFP, originally complaint with IEEE 754.1085 floating-point standard, significantly increases the floating point performance. The 1st processor in this family is ARM1020E which includes enhanced E instructions, separate 32k data and instructions cache, optional vector floating-point unit and a memory management unit. It also has a dual 64-bit bus interface for increased performance.ARM1026EJ-S is very similar to ARM926EJ-S but with both MPU and MMU.

ARM11
The ARM1136J-S, designed for high performance and power efficiency was the first processor to execute ARMv6 instruction set which includes improved multiprocessor instructions, unaligned and mixed endian data handling and new multimedia instructions. The family features an eight stage pipeline with separate load-store and arithmetic pipelines. Included in v6 instruction set are single instructions multiple data extensions for media processing, which is specifically designed to increase video processing performance. ARM1136JF-S is and ARM1136J-S with addition of vector floating-point unit for fast floating-point operations.

Specialized Processors
StrongARM, originally co-developed by Digital Semiconductor and now exclusively licensed by Intel is popular for PDAs and applications that require performance with low power consumption. Based on Harvard Architecture, it features separate data and instruction caches, a five stage pipeline and support for Thumb Instruction Set. Intels XScale is a follow-on product to StrongARM and offers dramatic increase in performance. Being able to operate at 1GHz, it executes V5TE instruction set. It also includes an MMU.