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Flip-Flops & Latches
Digital Electronics

This presentation will
Review sequential logic and the flip-flop. Introduce the D flip-flop and provide an excitation table and a sample timing analysis. Introduce the J/K flip-flop and provide an excitation table and a sample timing analysis.
Review flip-flop clock parameters.

Introduce the transparent D-latch.
Discuss flip-flop asynchronous inputs.

2
Sequential Logic & The Flip-Flop
Inputs
. .
Combinational Logic Gates
. .
Outputs
Clock
Memory Elements (Flip-Flops)
D Flip-Flop: Excitation Table
D
D Q
CLK

Q
0 1
Q
1 0
0 1
CLK
Q
: Rising Edge of Clock
D Flip-Flop: Example Timing

Q=D=1 Q=D=0 Q=D=0
No Change
Q=D=1
Q=D=1
No Change
Q=D=0
Q=D=0
No Change
Q D CLK
J/K Flip-Flop: Excitation Table
J
J
CLK K Q
K 0 1
CLK

Q
Q0
No Change Clear
1
1
0
1
1
Q0
Set
Toggle

Q : Complementof Q
J/K Flip-Flop: Example Timing

SET TOGGLE TOGGLE CLEAR NO CHANGE SET NO CHANGE
J
K CLK
Clock Edges
Positive Edge Transition
1 0
1 0
Negative Edge Transition

8
POS & NEG Edge Triggered D

Positive Edge Trigger
D
D Q
CLK
Q
0
1
Q
1
0
0
1
CLK
Q
Negative Edge Trigger

D
D Q
CLK

Q
0 1
Q
1 0
9
0 1
CLK
Q
: Falling Edge of Clock
POS & NEG Edge Triggered J/K

Positive Edge Trigger
J
J CLK K Q
K 0 1 0
CLK

Q
Q0
0 0 1
0 1
Q0
Negative Edge Trigger

J
J CLK K Q
K 0
CLK
Q
Q0
1
0 1
0
1
Q0
10
1 1
Flip-Flop Timing
Data Input (D,J, or K) 1
tS
Setup Time
Positive Edge Clock 1 0
tH
Hold Time
Setup Time (tS): The time interval before the active transition of the clock signal during which the data input (D, J, or K) must be maintained.
Hold Time (tH): The time interval after the active transition of the clock signal during which the data input (D, J, or K) must be maintained.
11
Asynchronous Inputs
Asynchronous inputs (Preset & Clear) are used to override the clock/data inputs and force the outputs to a predefined state. The Preset (PR) input forces the output to:
D
PR
Q 1 & Q 0
The Clear (CLR) input forces the output to:
CLK CLR
Q 0 & Q 1
PR
PRESET
CLR
CLEAR
CLK
CLOCK
D
DATA
Q
0
1 1 0 1
Q
1
0 0 1 1 Asynchronous Preset Asynchronous Clear ILLEGAL CONDITION
12
1
1 0 1 0
1
1 1 0 0
X X X
0
1 X X X
D Flip-Flop: PR & CLR Timing

Q=D=1
Clocked
Q=D=0
Clocked
Q=D=0
Clocked
Q=D=1
Clocked
Q=D=1
Clocked
Q=D=0
Clocked
Q
Q=1
Preset
Q=1
Preset
PR CLR D CLK
Q=0
Clear
13
Transparent D-Latch
EN
D Q
D X 0 1
Q
Q0
Q
Q0
0 1
0 1
1 0
EN
EN: Enable
14
Transparent D-Latch: Example Timing

Latched Q=0
Transparent Q=D Latched Q=1 Transparent Q=D
Latched Q=0
Transparent Q=D
Q D EN
15
Flip-Flop Vs. Latch

The primary difference between a D flip-flop and D latch is the EN/CLOCK input. The flip-flops CLOCK input is edge sensitive, meaning the flip-flops output changes on the edge (rising or falling) of the CLOCK input. The latchs EN input is level sensitive, meaning the latchs output changes on the level (high or low) of the EN input.
16

74LS74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs
74LS76 Dual Negative-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 74LS75 Quad Latch
17
74LS74: D Flip-Flop
18
74LS76: J/K Flip-Flop
19
74LS75: D Latch
20

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Flip-Flops & Latches

Flip-Flops & Latches

Review flip-flop clock parameters.

Discuss flip-flop asynchronous inputs.

Sequential Logic & The Flip-Flop

Combinational Logic Gates

Memory Elements (Flip-Flops)

D Flip-Flop: Excitation Table

D Flip-Flop: Example Timing

J/K Flip-Flop: Excitation Table

: Rising Edge of Clock

J/K Flip-Flop: Example Timing

Negative Edge Transition

POS & NEG Edge Triggered D

Negative Edge Trigger

POS & NEG Edge Triggered J/K

: Rising Edge of Clock

Negative Edge Trigger

: Rising Edge of Clock

D Flip-Flop: PR & CLR Timing

Transparent D-Latch: Example Timing

Flip-Flop Vs. Latch

Flip-Flops & Latches

74LS76: J/K Flip-Flop

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