Intruction Cycle (F (Fetch (Fetchh-Execute E Cycle) C l )

The sequence of actions that a CPU performs to execute each machine code instruction in a program. p g The Instruction Fetch Execute Cycle can g steps: p be broken down into the following
1. Fetch Cycle 2. Decode Cycle 3. Execute Cycle 4. Interrupt Cycle

Intruction Cycle (F (Fetch (Fetchh-Execute E Cycle) C l )

START Fetch next instruction
Decode

instruction Execute instruction Interrupt ? END

Fetch Cycle
The fetch cycle begins with retrieving the address stored in the Program Counter (PC). (PC) This is the memory address of the instruction to be executed. The Th CPU fetches f t h the th instruction i t ti stored t d at t this thi address from the memory and transferring this instruction to Instruction Register (IR). The program counter is incremented to point to the next address from which the new instruction is to be fetched.

Decode Cycle
From the instruction register, the data forming the instruction is decoded by the instruction decoder. The Opcode of the instruction are being determined. determined The operands are retrieved from the addresses dd as needed d db by th the O Opcode. d

Execute Cycle
The decoded information is used by Control Unit to perform the operation required by the instruction instruction. Ex: reading values from registers, passing values to the ALU ALU, adding valus etc etc. The result generated by the operation is stored t di in th the main i memory, registers, i t or sent to an output device.

Interrupt Cycle
An interrupt can occur any time during the program execution. Wh Whenever i it i is caused, d a series i of f events take k place l so that h the h instruction fetch execute cycle can again resume after the interrupt. Therefore, when an interrupt occurs, the following steps are p performed: 1. Suspend the execution of current instruction. 2. Push the address of current instruction on the Stack Pointer (SP). 3 Loading 3. L di th the PC with ith th the address dd of f th the interrupt i t t handler. h dl 4. Perform the interrupt routine. 5. Once the execution of the interrupt handler complete, the address of the next instruction to be executed is obtained from popping the value of the address in the Stack Pointer. 6. Resume the suspended instruction execution. This cycle of fetching a new instruction, decoding it and finally executing ti it continues ti until til th the computer t i is t turned d off. ff

Instruction Cycle / Machine Cycle

Instruction Cycle: The time required to execute an instruction. When the 8085 processor executes an instruction, instruction it will execute some of the machine cycles in a specific order. Machine Cycle: The time required to access the memory or input/output devices devices. The 8085 microprocessor has 5 basic machine cycles:
1.Opcode fetch cycle (4T) 2 Memory read cycle (3T) 2.Memory 3.Memory write cycle (3T) 4.I/O read cycle (3T) 5 I/O write cycle (3T) 5.I/O

T-State: The time taken by the processor to execute a machine cycle is expressed in T-states. 1 T-state T state = 1/ operating frequency of 8085 Microprocessor
For example operating frequency = 2MHz, then time required to execute 1 T-state = 0.5 uSec

Example: Calculate time required to execute instruction MOV C, A

sol: This instruction has one machine cycle i.e. opcode fetch (In any instruction 1st cycle is always opcode fetch and opcode fetch consists i t 4t to 6 T state t t depend d d on the th operation ti of f particular ti l instruction) So to execute MOV C, A required 4T states so time required to execute this instruction is 4*0.5usec = 2usec

Example:Calculate the time required to execute LXI H,2000H

sol: Here we have to draw opcode fetch and two memory reads as two bytes 00H and 20H have to be read from memory. i.e, , opcode p fetch+Memory y reads *2(bytes ( y address) ) =4+3+3 So to execute LXI H,2000H,the required T-states is 10T and time is 10*0.5usec=5usec

Timing Diagram
Timing Diagram is a graphical representation which represents the execution time taken by each instruction in a graphical format. The timing diagram of an instruction are obtained by drawing the timing diagrams of the machine cycles of that instruction, one by one in the order of execution. The execution time is represented in T-states T-states. The T-state starts at the falling edge of a clock.

Timing diagram for MVI B, 43H.

Opcode fetch cycle (4T) M Memory read d cycle (3T) Status signals: write IO/M(bar) Memory : cycle y 1(I/O) 0 (Memory) (3T) S1 | S0 | I/O read cycle 0 | 0 | Halt (3T) 0 | 1 | Write I/O write 1 | 0 | Read cycle 1 | 1 | Opcode(3T) fetch

Fetching the Opcode 06H from the memory 2000H. (OF machine cycle) R d( Read (move) ) th the d data t 43H f from memory 2001H 2001H. ( (memory read) d) ALE - Address Latch Enable. This signal helps to capture the lower order address presented on the multiplexed address / data bus.

Timing diagram for STA 526AH

STA means Store Accumulator -The contents of the accumulator is stored in the specified address (526A). The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH Then the lower order memory y address is read(6A). ( ) - Memory y Read Machine Cycle y Read the higher order memory address (52).- Memory Read Machine Cycle The combination of both the addresses are considered and the content from accumulator is written in 526A. - Memory Write Machine Cycle Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A.

Opcode fetch cycle (4T) Memory read cycle (3T) Status signals: write IO/M(bar) Memory : cycle 1(I/O) 0 (Memory) (3T) S1 | S0 | I/O read cycle 0 | 0 | Halt (3T) 0 | 1 | Write I/O write rite 1 | 0 | Read cycle 1 | 1 | Opcode(3T) fetch

ALE - Address Latch Enable. This signal helps to capture the lower order address presented on the multiplexed address / data bus.