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Silicon on insulator - Wikipedia, the free encyclopedia

Silicon on insulator
From Wikipedia, the free encyclopedia

(Redirected from Silicon on Insulator) Silicon on insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance.[1] SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for highperformance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short channel effects in microelectronics devices.[2] The insulating layer and topmost silicon layer also vary widely with application.[3] The first industrial implementation of SOI was announced by IBM in August 1998.[4]

Contents
1 Industry need 2 Manufacture of SOI wafers 3 Use in the microelectronics industry 4 Use in high-performance Radio-Frequency (RF) applications 5 Use in photonics 6 See also 7 References 8 External links
SIMOX process

Industry need
The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronic devices, colloquially referred to as extending Moore's Law. Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include:[5] Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance.
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Resistance to latchup due to complete isolation of the n- and p-well structures. From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 1015% increase to total manufacturing costs.[6]

Manufacture of SOI wafers

SiO2-based SOI wafers can be produced by several methods: SIMOX - Separation by IM plantation of OXygen uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.[7][8][9] Wafer bonding[10][11] the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer. One prominent example of a wafer bonding process is the Smart Cut method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer. NanoCleave is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and silicon-germanium alloy.[12] ELTRAN is a technology developed by Canon which is based on porous silicon and water cut.[13] Seed methods[14] - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.

Smart Cut process

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An exhaustive review of these various manufacturing processes may be found in reference [1]

Use in the microelectronics industry

IBM began to use SOI in the high-end RS64-IV "Istar" PowerPC-AS microprocessor in 2000. Other examples of microprocessors built on SOI technology include AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors since 2001.[15] Freescale adopted SOI in their PowerPC 7455 CPU in late 2001, currently Freescale is shipping SOI products in 180 nm, 130 nm, 90 nm and 45 nm lines.[16] The 90 nm Power Architecture based processors used in the Xbox 360, PlayStation 3 and Wii use SOI technology as well. Competitive offerings from Intel, however, such as the 65 nm Core 2 and Core 2 Duo microprocessors, are built using conventional bulk CMOS technology. Intel's new 45 nm process will continue to use conventional technology. In January, 2005 Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.[17] In November 2010, several news sources indicated that Intel may switch to SOI for the 22 nm node.[18] More recently, Intel announced it will not go to SOI at 22 nm due to costs, and instead has used FinFET technology in Ivy Bridge. On the foundry side, July 2006 TSMC claimed no customer wanted SOI,[19] but Chartered Semiconductor devoted a whole fab to SOI.[20]

Use in high-performance Radio-Frequency (RF) applications

In 1990, Peregrine Semiconductor began development of an SOI process technology utilizing a standard 0.5 um CMOS node and an enhanced sapphire substrate. Its patented silicon on sapphire (SOS) process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge (ESD) tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios.[21]

Use in photonics
SOI wafers are widely used in silicon photonics.[22] The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other passive optical devices for integrated optics. The crystalline silicon layer is sandwiched between the buried insulator (Silicon oxide, Sapphire etc.) and top cladding of air (or Silicon oxide or any other low refractive index material). This enables propagation of electromagnetic waves in the waveguides on the basis of total internal reflection.

See also
Intel TeraHertz - similar technology from Intel. Wafer (electronics) Wafer bonding Silicon on sapphire

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References
1. ^ a b Celler, G. K.; Cristoloveanu, S. (2003). "Frontiers of silicon-on-insulator". J Appl Phys 93 (9): 4955. doi:10.1063/1.1558223 (http://dx.doi.org/10.1063%2F1.1558223). 2. ^ Marshall, Andrew; Natarajan, Sreedhar (2002). SOI design: analog, memory and digital techniques. Boston: Kluwer. ISBN 0792376404. 3. ^ Colinge, Jean-Pierre (1991). Silicon-on-Insulator Technology: Materials to VLSI. Berlin: Springer Verlag. ISBN 978-0-7923-9150-0. 4. ^ IBM Advances Chip Technology With Breakthrough For Making Faster, More Efficient Semiconductors (http://www-03.ibm.com/press/us/en/pressrelease/2521.wss) 5. ^ Silicon-on-insulator - SOI technology and ecosystem - Emerging SOI applications (http://www.soiconsortium.org/pdf/Consortium_9april09_final.pdf) by Horacio Mendez, Executive Director of the SOI Industry Consortium, April 9, 2009 6. ^ IBM touts chipmaking technology (http://news.com.com/IBM+touts+chipmaking+technology/2100-1001_3254983.html) 7. ^ U.S. Patent 5,888,297 (http://www.google.com/patents?vid=5888297) Method of fabricating SOI substrate Atsushi Ogura, Issue date: Mar 30, 1999 8. ^ U.S. Patent 5,061,642 (http://www.google.com/patents?vid=5061642) Method of manufacturing semiconductor on insulator Hiroshi Fujioka, Issue date: Oct 29, 1991 9. ^ SIMOX-SOI Technology: Ibis Technology (http://www.ibis.com/simox.htm) 10. ^ "SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gsele, Wiley-Interscience, 1998, ISBN 978-0-471-57481-1 11. ^ U.S. Patent 4,771,016 (http://www.google.com/patents?vid=4771016) Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor, George Bajor et al., Issue date: Sep 13, 1988 12. ^ http://www.sigen.com/ 13. ^ ELTRAN - Novel SOI Wafer Technology (http://www.jsapi.jsap.or.jp/Pdf/Number04/CuttingEdge2.pdf), JSAPI vol.4 14. ^ U.S. Patent 5,417,180 (http://www.google.com/patents?vid=5417180) 15. ^ Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed (http://chiparchitect.com/news/2000_11_07_process_130_nm.html) 16. ^ Process Technology (http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=0121000303#soi) 17. ^ Liu, Ansheng; Jones, Richard; Cohen, Oded; Hak, Dani, Nicolaescu, Remus; Fang, Alexander; Paniccia, Mario (01 2005). "Letters to Nature - An all-silicon Raman laser" (http://techresearch.intel.com/spaw2/uploads/files/R817nature03273.pdf). Nature 433: 292294. doi:10.1038/nature03723 (http://dx.doi.org/10.1038%2Fnature03723). 18. ^ http://www.eetimes.com/electronics-news/4210354/Analyst--Intel-to-endorse-SOI-at-22-nm-semiconductor 19. ^ TSMC has no customer demand for SOI technology - Fabtech - The online information source for semiconductor professionals (http://www.fabtech.org/content/view/1698/74/) 20. ^ Chartered expands foundry market access to IBM's 90nm SOI technology (http://www.charteredsemi.com/media/corp/2006n/20060420_IBM_SOI.asp) 21. ^ Madden, Joe. "Handset RFFEs: MMPAs, Envelope Tracking, Antenna Tuning, FEMs, and MIMO" (http://mobile-experts.net/manuals/mexp-rffe-12%20toc.pdf). Mobile Experts. Retrieved 2 May 2012. 22. ^ "Silicon photonics: an introduction" by Graham T. Reed, Andrew P. Knights. WIley. Page 111 (http://books.google.be/books? id=6lsVVvFCBeAC&lpg=PA57&ots=XmqaiUFliA&dq=SOI%20Wafers%20in%20Photonics&hl=en&pg=PA111#v =onepage&q=SOI%20&f=false)

External links
SOI Industry Consortium (http://www.soiconsortium.org/) - a site with extensive information and education
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for SOI technology SOI IP portal (http://www.chipestimate.com/SOI) - A search engine for SOI IP AMDboard (http://www.amdboard.com/soispecial.html) - a site with extensive information regarding SOI technology Advanced Substrate News (http://www.advancedsubstratenews.com/) - a newsletter about the SOI industry, produced by Soitec. MIGAS '04 (http://www.migas.inpg.fr/2004/index.htm) - The 7th session of MIGAS International Summer School on Advanced Microelectronics, devoted to SOI technology and devices. MIGAS '09 (http://www.migas.inpg.fr/) - 12th session of the International Summer School on Advanced Microelectronics: "Silicon on Insulator (SOI) Nanodevices" Retrieved from "http://en.wikipedia.org/w/index.php?title=Silicon_on_insulator&oldid=542576581" Categories: Semiconductor structures Semiconductor technology Microtechnology This page was last modified on 7 March 2013 at 12:50. Text is available under the Creative Commons Attribution-ShareAlike License; additional terms may apply. By using this site, you agree to the Terms of Use and Privacy Policy. Wikipedia is a registered trademark of the Wikimedia Foundation, Inc., a non-profit organization.

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