EE290C Spring 2011

Lecture 15: Support: Supply Regulation I

Elad Alon Dept. of EECS

Link Surroundings
Links integrated onto 1V, 100A processors
Required |Zsupply| < 1 m for ~100mV supply noise

Link supply (ground) often shared

90nm Itanium
I/O Processor Core

Measured Supply Noise

I/O Processor Core

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On-Chip Regulation

ref Clk

up PFD down

Vcp

Vdd + Regulator Vreg Clk

Many links regulate supplies of critical blocks

Good/bad regulator design can make or break the link
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Regulator Types
Switching vs. linear
(Easy vs. Not easy to integrate)

Linear: series vs. shunt

(Isolation vs. impedance)

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Series Regulator Requirements

Low drop-out voltage

Efficiency Vreg/Vdd Need to budget for Vdd droops too

High PSRR across a broad range of frequencies

Intrinsic supply rejection of load (e.g., ring oscillator) may be very low
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Typical Low-Dropout Regulator

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Compensation Techniques
Miller Compensation RC Compensation

How do these two techniques achieve stability? What are the implications of that on PSRR?
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Dominant Pole: Amplifier vs. Output

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Optimizing Regulator PSRR

For fixed amplifier GBW, find best PSRR by trading between gain and bandwidth

Define PSRR as inverse of max. sensitivity Similar results if minimize Vreg/Vdd with white noise on Vdd
(j )/V (j )|| ||V
dd

-20

-25

-30

reg

-35

10MHz

100MHz Frequency

1GHz

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Small Signal Model for Supply Noise

Vref + Vbp Mout Vreg Cdecap Load

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Small Signal Model for Supply Noise

Vref + Vbp Mout Vreg Cdecap Load

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Optimal Amplifier Design

For clarity, normalize amplifier gain and bandwidth:
Amplifier bandwidth relative to output pole: a = o Normalized gain-bandwidth: GBW = Aa

If open loop gain (AaAo)1, optimal allocation is:

3 2

A o GBW

Aa =

2 3

GBW Ao

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What This Really Means

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Implications
-10

With optimal allocation:

Supply Sensitivity (dB)

-15 -20 -25 -30 -35 -40 -45 Frequency

||Vreg(j )/V dd(j)||

RC Filter

PSRR

1 2

AoGBW

To improve PSRR by 2x, both amplifier gain and bandwidth increase by 2x

2x 2x

In other words, required gain-bandwidth scales with PSRR2

Tradeoff steep any way to improve?
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Towards an Improved Solution

With o = 2100MHz and Ao = 3 GBW 1 (100MHz) 10 (1GHz) 100 (10GHz) a
2212MHz 2670MHz 22.1GHz

Aa 0.47 1.49 4.71

Amplifier in many cases is just acting like a (highbandwidth) wire

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Source-Follower-Based Regulator

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PSRR Comparison

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Practical Issue #1

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Practical Issue #2

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Common-Source Has Issues Too

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Typical Design

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Local Negative Feedback

Vin + + k Vreg Verr + Aa(s) Vbp Wp

Cdecap

Load

Local feedback efficiently trades gain for bandwidth Next lecture: use local f/b to drastically improve PSRR
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