EINSTEIN

COLLEGE OF ENGINEERING
Sir.C.V.Raman Nagar, Tirunelveli-12

Department of Electronics and Communication Engineering

Subject Code: CS37
Digital Lab

Name Reg No Branch Year & Semester

: : : :

Sub Code: CS37

LIST OF EXPERIMENTS

INDEX
Exp. No. 1 2 PAGE NO. STAFF INITIAL

DATE

TITLE OF EXPERIMENT

MARKS

10

11

12

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

EXPT. NO. : 1 DATE :

STUDY OF LOGIC GATES

AIM: To study about logic gates and verify their truth tables. APPARATUS REQUIRED:

SL No.
1. 2. 3. 4. 5. 6. 7. 8. 9.

COMPONENT
AND GATE OR GATE NOT GATE NAND GATE 2 I/P NOR GATE X-OR GATE NAND GATE 3 I/P IC TRAINER KIT PATCH CORD

SPECIFICATION
IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 IC 7410 -

QTY
1 1 1 1 1 1 1 1 As per Required

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates. Basic gates form these gates.

AND GATE:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

The AND gate performs a logical multiplication commonly known as AND function. The output is high when both the inputs are high. The output is low level when any one of the inputs is low.

OR GATE: The OR gate performs a logical addition commonly known as OR function. The output is high when any one of the inputs is high. The output is low level when both the inputs are low. NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND GATE: The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The output is low when one or both inputs are high.

X-OR GATE: The output is high when any one of the inputs is high. The output is low when both the inputs are low and both the inputs are high.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

AND GATE: SYMBOL: PIN DIAGRAM:

OR GATE:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

NOT GATE: SYMBOL: PIN DIAGRAM:

X-OR GATE : SYMBOL : PIN DIAGRAM :

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

NOR GATE:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROCEDURE:
(i) Connections are given as per circuit diagram. (i) Logical inputs are given as per circuit diagram. (iii)Observe the output and verify the truth table.

RESULT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

EXPT. NO. DATE

: 2 : VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES

AIM :
To verify the Boolean Theorems using logic gates.

APPARATUS REQUIRED: SL No.

1. 2. 3. 4. 5.

COMPONENT
AND GATE OR GATE NOT GATE IC TRAINER KIT CONNECTING WIRES

SPECIFICATION
IC 7408 IC 7432 IC 7404 -

QTY
1 1 1 1 As per Required

BOOLEAN THEOREM: Theorem : 1. x + x = x ; 2. x + 1 = 1 ; 3. (x) = x x.x = x x.0 = 0 ( Involution )

4. Associative x + (y + z) = (x + y) + z

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

x . (y . z) = (x . y) . z 5. De Morgans (x + y) = x . y (x . y) = x + y 6. Absorption x + x.y = x x . (x + y) = x

CIRCUIT DIAGRAM: THEOREM : 1

3 2 IC 7432 Truth Table: X 0 1 X 0 1 Y = X+X 0 1 X 0 1 X 0 1 Y = X.X 0 1 Y = X+X = X 2 IC 7408

3 Y = X.X = X

THEOREM: 2
X 1 3 X 1 3

+Vcc

Y = X+1 = X IC 7432

0V

2 Y = X.0 = 0 IC 7408

Truth Table:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

1 1 1

Y=X+1=1

0 1

1 1

0 0 1 0 0

Y=X.0=0

0 0

THEOREM: 3 (INVOLUTION THEOREM)

Truth Table: IC 7404 X 1 IC 7404 X Y = (X) 2 3 4

X

X
Y = (X)

0 1

1 0

0 1

THEOREM:4 (ASSOCIATIVE) X 0 0 1 1

(1)
X 1

IC 7432 3 2 5

IC 7432 4 A =(X+Y)+Z 6

Truth Table: Y Z X+Y 0 0 0 1 0 1 0 1 1 1 1 1

A 0 1 1 1

Y Z

Truth Table:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

X Y Z IC 7432 1 2 3

IC 7432 4 6 5 A=X+(Y+Z)

X 0 0 1 1

Y 0 1 0 1

Z 0 0 1 1

Y+Z 0 1 1 1

A 0 1 1 1

(2) (X.Y).Z =X.(Y.Z) IC 7408 X Y Z 1 2 3 4 A =(X.Y).Z 6 IC 7408 X 0 0 1 1

Truth Table: Y 0 1 0 1 Z 0 0 1 1 X.Y 0 0 0 1 A 0 0 0 1

X Y Z IC 7408 1 2 3 IC 7408

IC 7408 4 6 5 A=X.(Y.Z)

X 0 0 1 1

Y 0 1 0 1

Z 0 0 1 1

Y.Z 0 0 0 1

A 0 0 0 1

THEOREM: 5

DE-MORGANS LAW: (i) X . Y = (X+Y))

Truth Table:
Einstein College of Engineering Page 47 of 108

Sub Code: CS37

IC 7404 X 1 2 Y 3 4

IC 7408 1 3 A=X.Y 2

X Y X 0 0 1 0 1 1 1 0 0 1 1 0

Y 1 0 1 0

A=X . Y 1 0 0 0

IC 7404

X Y

IC 7432 IC 7404) 1 3 1 2 A= (X+Y) 2 X 0 0 1 1

Truth Table: Y 0 1 0 1 X+Y A=(X+Y) 0 1 1 0 1 0 1 0

Truth Table: (ii) ( X . Y) = (X + Y ) X IC 7408 IC 7404 3 1 2 1 A= (X . Y) X Y 0 0 0 1 1 0 1 1 X.Y 0 0 0 1 A=(X.Y) 1 1 1 0

Y 2

Truth Table:
Einstein College of Engineering Page 47 of 108

Sub Code: CS37

IC 7404 X1 2

Y 3

IC 7432 1 3 2 A=X + Y

X Y X 0 0 1 1 0 1 0 1 1 1 0 0

Y
A=X + Y

1 0 1 0

1 1 1 0

THEOREM: 6

(ABSORPTION) 1 3 IC 7432 Y = X + X.Y Truth Table: X 0 0 1 1 Y X+Y Y = X + X.Y 0 0 0 1 0 0 0 0 1 1 1 1 X 0 0 1 1

X Y

1 3 2 X.Y IC 7408

1 X Y 1 3 2 X+Y IC 7432 2

3 Y = X . (X + Y) Truth Table: IC 7408 X 0 0 1 1 Y X+Y Y = X.(X+Y) 0 0 0 1 0 0 0 0 1 1 1 1 X 0 0 1 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROCEDURE:
1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

RESULT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

EXPT. NO. DATE

: 3 : DESIGN OF ADDER AND SUBTRACTOR

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor circuits and verify the truth table using logic gates.

APPARATUS REQUIRED: Sl.No.

1 2 3 4 5 6

COMPONENT
AND GATE X-OR GATE NOT GATE OR GATE IC TRAINER KIT PATCH CORD

SPECIFICATION
IC 7408 IC 7486 IC 7404 IC 7432 -

QTY.
1 1 1 1 1 As per

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

Required

THEORY:
HALF ADDER: A half adder has two inputs for the two bits to be added and two outputs one from the sum S and other from the carry c into the higher adder position. Above circuit is called as a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate.

FULL ADDER: A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate. HALF SUBTRACTOR: The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter. FULL SUBTRACTOR: The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic circuit should have three inputs and two outputs. The two half subtractor put together gives a full subtractor .The first half subtractor will be C and A B. The output will be difference

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

output of full subtractor. The expression AB assembles the borrow output of the half subtractor and the second term is the inverted difference output of first X-OR.

LOGIC DIAGRAM:
HALF ADDER

TRUTH TABLE: A B CARRY SUM

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

0 0 1 1

0 1 0 1

0 0 0 1

0 1 1 0

K-Map for SUM:

K-Map for CARRY:

SUM = AB + AB

CARRY = AB

LOGIC DIAGRAM:
FULL ADDER USING TWO HALF ADDER:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

CARRY 0 0 0 1 0 1 1 1

SUM 0 1 1 0 1 0 0 1

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC K-Map for CARRY:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

CARRY = AB + BC + AC

LOGIC DIAGRAM:

HALF SUBTRACTOR

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:

A 0 0 1 1

B 0 1 0 1

BORROW 0 1 0 0

DIFFERENCE 0 1 1 0

K-Map for DIFFERENCE:

DIFFERENCE = AB + AB

K-Map for BORROW:

BORROW = AB

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM:
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 BORROW 0 1 1 1 0 0 0 1 DIFFERENCE 0 1 1 0 1 0 0 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

K-Map for Difference:

DIFFERENCE = ABC + ABC + ABC + ABC

K-Map for Borrow:

BORROW = AB + BC + AC

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROCEDURE:
(i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

EXPT. NO. DATE

:4 :

DESIGN AND IMPLEMENTATION OF CODE CONVERTER AIM:

To design and implement 4-bit (i) (ii) (iii) Binary to gray code converter Gray to binary code converter BCD to excess-3 code converter Einstein College of Engineering Page 47 of 108

Sub Code: CS37

(iv)

Excess-3 to BCD code converter

APPARATUS REQUIRED: Sl.No.

1. 2. 3. 4. 5. 6.

COMPONENT
X-OR GATE AND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS

SPECIFICATION
IC 7486 IC 7408 IC 7432 IC 7404 -

QTY.
1 1 1 1 1 As per Required

THEORY:
The availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0 and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

A code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as specified by code and the output lines generate the corresponding bit combination of code. Each one of the four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is C+D has been used to implement partially each of three outputs.

LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE: |
B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary input B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

|
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Gray code output G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

K-Map for G3:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

G3 = B3
K-Map for G2:

K-Map for G1:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

K-Map for G0:

LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE: |
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Gray Code G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

|
B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Binary Code B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

K-Map for B 3:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

B3 = G3
K-Map for B 2:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

K-Map for B 1:

K-Map for B 0:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR

TRUTH TABLE: |
B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BCD input B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

|
G3 0 0 0 0 0 1 1 1 1 1 x x x x x x

Excess 3 output G2 0 1 1 1 1 0 0 0 0 1 x x x x x x G1 1 0 0 1 1 0 0 1 1 0 x x x x x x

|
G0 1 0 1 0 1 0 1 0 1 0 x x x x x x

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

K-Map for E 3:

E3 = B3 + B2 (B0 + B1)
K-Map for E 2:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

K-Map for E 1:

K-Map for E 0:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE: |
B3 0 0 0 0 0 1 1 1 1 1 Excess 3 Input B2 0 1 1 1 1 0 0 0 0 1 B1 1 0 0 1 1 0 0 1 1 0 B0 1 0 1 0 1 0 1 0 1 0

|
G3 0 0 0 0 0 0 0 0 1 1

BCD Output G2 0 0 0 0 1 1 1 1 0 0 G1 0 0 1 1 0 0 1 1 0 0

|
G0 0 1 0 1 0 1 0 1 0 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

K-Map for A:

A = X1 X2 + X3 X4 X1

K-Map for B:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

K-Map for C:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

K-Map for D:

PROCEDURE:
(i) (ii) (iii) Connections were given as per circuit diagram. Logical inputs were given as per truth table Observe the logical output and verify with the truth tables.

RESULT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

EXPT. NO. DATE

:5 :

DESIGN OF 4-BIT BINARY ADDER AND SUBTRACTOR AIM:

To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. 1. 2. 3. 3. 4. COMPONENT IC EX-OR GATE NOT GATE IC TRAINER KIT PATCH CORD SPECIFICATION IC 7483 IC 7486 IC 7404 QTY. 1 1 1 1 As per Required

THEORY:
4 BIT BINARY ADDERS: A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of next full adder in chain. The augends bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The carries are connected in chain through the full adder. The input carry to the adder is C0 and it ripples through the full adder to the output carry C4.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

4-BIT BINARY SUBTRACTOR: The circuit for subtracting A-B consists of an adder with inverters, placed between each data input B and the corresponding input of full adder. The input carry C0 must be equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR: The addition and subtraction operation can be combined into one circuit with one common binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDERS: Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns. ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
4-BIT BINARY ADDER

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTHTABLE:
Input Data A Input Data B C 0 1 0 0 1 1 Addition S4 S3 S2 S1 1 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 B 1 1 0 0 0 0 Subtraction D4 D3 D2 D1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1

A4 A3 A2 A1 B4 B3 B2 B1 1 1 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROCEDURE:
(i) (ii) (iii) Connections were given as per circuit diagram. Logical inputs were given as per truth table Observe the logical output and verify with the truth tables.

RESULT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

EXPT NO. DATE :

:6

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

AIM:
To design and implement (i) (ii) 2 bit magnitude comparator using basic gates. 8 bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

Sl.No. 1. 2. 3. 4. 5. 6. 7.

COMPONENT AND GATE X-OR GATE OR GATE NOT GATE 4-BIT MAGNITUDE COMPARATOR IC TRAINER KIT PATCH CORD

SPECIFICATION IC 7408 IC 7486 IC 7432 IC 7404 IC 7485 -

QTY. 2 1 1 1 2 1 As per Required

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

THEORY:
The comparison of two numbers is operators that determine one number is greater than, less than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by three binary variables that indicate whether A>B, A=B (or) A<B.

A = A3 A2 A1 A0 B = B3 B2 B1 B0

The equality of the two numbers and B is displayed in a combinational circuit designated by the symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits starting from most significant position. A is 0 and that of B is 0.

We have A<B, the sequential comparison can be expanded as A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01 A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0 The same circuit can be used to compare the relative magnitude of two BCD digits. Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0) x3 x2 x1 x0

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM:
2-BIT MAGNITUDE COMPARATOR

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE
A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PIN DIAGRAM FOR IC 7485:

K MAP

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM:
8-BIT MAGNITUDE COMPARATOR

TRUTH TABLE:
A 0000 0000 0001 0001 0000 0000 B 0000 0000 0000 0000 0001 0001 A>B 0 1 0 A=B 1 0 0 A<B 0 0 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROCEDURE:
(i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37 EXPT. NO. DATE :7 :

DESIGN

AND

IMPLEMENTATION

OF

PARITY

GENERATOR / CHECKER USING BASIC GATES AND MSI DEVICES AIM:

To design and implement odd/even parity checker generator using logic gates and IC 74180.

APPARATUS REQUIRED:

Sl.No. 1 2 3 4.

COMPONENT NOT GATE PARITY GENERATOR /CHECKER IC IC TRAINER KIT PATCH CORD

SPECIFICATION IC 7404 IC 74180 -

QTY. 1 2 1 As per Required

THEORY:
A parity bit is used for detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number is either even or odd. The message including the parity bit is transmitted and then checked at the receiver ends for errors. An error is detected if the checked parity bit doesnt correspond to the one transmitted. The circuit that generates the parity bit Einstein College of Engineering Page 47 of 108

Sub Code: CS37 in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In even parity, the added parity bit will make the total number is even amount. In odd parity, the added parity bit will make the total number is odd amount. The parity checker circuit checks for possible errors in the transmission. If the information is passed in even parity, then the bits required must have an even number of 1s. An error occur during transmission, if the received bits have an odd number of 1s indicating that one bit has changed in value during transmission.

PARITY CHECKER /GENERATOR USING LOGIC GATES: TRUTHTABLE: PARITY GENERATOR

INPUT A 0 0 0 0 1 1 1 B 0 0 1 1 0 1 1 C 0 1 0 1 0 0 1 OUTPUT P.G 0 1 1 0 1 0 1

LOGIC DIAGRAM:
A

A B

3 7486

6 7486

PG

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTHTABLE: PARITY CHECKER

INPUT C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OUTPUT P.C 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

LOGIC DIAGRAM:

A B
7486

PC
7486

C D
7486

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PARITY CHECKER /GENERATOR USING MSI DEVICE:

PIN DIAGRAM FOR IC 74180:

FUNCTION TABLE:
INPUTS Number of High Data Inputs (I0 I7) EVEN ODD EVEN ODD X X PE 1 1 0 0 1 0 PO 0 0 1 1 1 0 OUTPUTS O E 1 0 0 1 0 1 0 1 1 0 0 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY CHECKER

TRUTH TABLE:

I7 I6 I5 I4 I3 I2 I1 I0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

I7 I6 I5 I4 I3 I2 I1 I0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

Active 1 0 0

E 1 0 1

O 0 1 0

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROCEDURE:
(i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

EXPT. NO. DATE

:8 :

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER AIM:

To design and implement multiplexer and demultiplexer using logic gates

APPARATUS REQUIRED:

Sl.No. 1. 2. 3. 4. 5.

COMPONENT 3 I/P AND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORD

SPECIFICATION IC 7411 IC 7432 IC 7404 -

QTY. 2 1 1 1 As per Required

THEORY:
MULTIPLEXER: Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input line and n selection lines whose bit combination determine which input is selected.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

DEMULTIPLEXER: The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 0 0 1 1

S0 0 1 0 1

INPUTS Y D0 D0 S1 S0 D1 D1 S1 S0 D2 D2 S1 S0 D3 D3 S1 S0

Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:
S1 0 0 1 1 S0 0 1 0 1 Y = OUTPUT D0 D1 D2 D3

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 0 0 1 1

S0 0 1 0 1

INPUT X D0 = X S1 S0 X D1 = X S1 S0 X D2 = X S1 S0 X D3 = X S1 S0

Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM FOR DEMULTIPLEXER:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:

INPUT S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 I/P 0 1 0 1 0 1 0 1 D0 0 1 0 0 0 0 0 0 D1 0 0 0 1 0 0 0 0

OUTPUT D2 0 0 0 0 0 1 0 0 D3 0 0 0 0 0 0 0 1

PROCEDURE:
(i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

EXPT. NO. DATE

:9 :

DESIGN AND IMPLEMENTATION OF SYNCHRONOUS AND ASYNCHRONOUS COUNTERS AIM:

To design and verify Synchronous and Asynchronous counter

APPARATUS REQUIRED:
Sl.No. 1. 2. 3. 4. COMPONENT JK FLIP FLOP NAND GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7476 IC 7408 QTY. 2 1 1 As per Required

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. A specified sequence of states appears as counter output. This is the main difference between a register and a counter. There are two types of counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage. Because of inherent propagation delay time all flip flops are not activated at same time which results in asynchronous operation.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PIN DIAGRAM FOR IC 7476:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM:

SYNCHRONOUS COUNTER
IC7408
1 3 2

PRESET
2 7

IC7476
Q 15 9 6 Q 14 12 J

IC7476
Q 11 4 1 Q 10 16 J

2 PR E 3 C LR

IC7476
Q 15

PR E

DATA IN

4 1 16

CLK
C LR

CLK
C LR

PR E

CLK K Q 14

CLOCK CLEAR

A2

A1

A0

TRUTH TABLE:

CLK 0 1 2 3 4 5 6 7

QA 0 0 0 0 1 1 1 1

QB 0 0 1 1 0 0 1 1

QC 0 1 0 1 0 1 0 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM FOR 4 BIT ASYNCHRONOUS COUNTER:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:

CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROCEDURE:
(i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

EXPT. NO. DATE

: 10 :

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER AIM:

To design and implement (i) Serial in serial out (ii) Serial in parallel out (iii) Parallel in serial out (iv) Parallel in parallel out

APPARATUS REQUIRED:
Sl.No. 1. 2. 3. 4. COMPONENT D FLIP FLOP OR GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7474 IC 7432 QTY. 2 1 1 As per Required

THEORY:
A register is capable of shifting its binary information in one or both directions is known as shift register. The logical configuration of shift register consist of a DFlip flop cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop. The output

Einstein College of Engineering Page 47 of 108

Sub Code: CS37 of a given flip flop is connected to the input of next flip flop of the register. Each clock pulse shifts the content of register one bit position to right.

PIN DIAGRAM:

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:

CLK 1 2 3 4 5 6 7

Serial in 1 0 0 1 X X X

Serial out 0 0 0 1 0 0 1

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:

CLK 1 2 3 4

DATA 1 0 0 1

OUTPUT QA 1 0 0 1 QB 0 1 0 0 QC 0 0 1 0 QD 0 0 0 1

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:

CLK 0 1 2 3

Q3 1 0 0 0

Q2 0 0 0 0

Q1 0 0 0 0

Q0 1 0 0 0

O/P 1 0 0 1

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:

CLK 1 2

DATA INPUT DA 1 1 DB 0 0 DC 0 1 DD 1 0 QA 1 1

OUTPUT QB 0 0 QC 0 1 QD 1 0

PROCEDURE:
(i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

EXPT. NO. : 11 DATE :

DESIGN OF ADDER AND SUBTRACTOR USING VERILOG HARDWARE DESCRIPTION LANGUAGE AIM:
To write the HDL program for designing adder and subtractor circuit and simulate it.

SOFTWARE USED:
XILINK ISE Simulator

THEORY:
HALF ADDER: From the verbal explanation of a half adder, we find that this circuit needs two binary inputs and two binary outputs. The input variables designate the augends and addend bits; the output variables produce the sum and carry. We assign symbol a and b to the inputs and S (for sum) and C (for carry) to the outputs. The truth table for the half adder is listed in table. The C output is 1 only when both inputs are 1. The S output represents the least significant bit of the sum. The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The simplified sums of products expressions are S= ab + ab C= ab The logic diagram of the half adder implemented in sum of products is shown in figure. It can be also implemented with an exclusive-OR and an AND gate as Einstein College of Engineering Page 47 of 108

Sub Code: CS37 shown in figure. This from is used to show that two half adders can be used to construct a full adder.

FULL ADDER: A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and two outputs. Two of the input variables, denoted by a and b, represent the two significant bits to be added. The third input c represents the carry from the previous lower significant position. Two outputs are necessary because the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary 2 or 3 needs two digits. The two outputs are designated by the symbols S for sum and D for carry. The binary variable S gives the value of the least significant bit of the sum. The binary variable D gives the output carry. The truth table of the full adder is listed in table. The eight rows under the input variables designate all possible combinations of the variables. The output variables are determined from the arithmetic sum of the input bits. When all input bits are 0, the output is 0. The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The D output has a carry of 1 if two or three inputs are equal to 1.

The input and output bits of the combinational circuit different interpretations at various stages of the problem. Physically, the binary signals of the inputs are considered binary digits to be added arithmetically to form a two-digit sum at the output. On the other hand, the same binary values are considered as variables of Boolean functions when expressed in the truth table or when the circuit is implemented with logic gates. The maps for the output of the full adder are shown in below.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

HALF ADDER:
LOGIC DIAGRAM:

TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 CARRY 0 0 0 1 SUM 0 1 1 0

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROGRAM FOR HALF ADDER: module halfadder (a,b,sum,carry); input a,b; output sum,carry; xor(sum,a,b); and(carry,a,b); endmodule

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

FULL ADDER:
LOGIC DIAGRAM: FULL ADDER USING TWO HALF ADDER:

TRUTH TABLE: A 0 0 0 0 1 B 0 0 1 1 0 C 0 1 0 1 0 CARRY 0 0 0 1 0 SUM 0 1 1 0 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1

PROGRAM FOR FULL ADDER: module fulladder(a,b,cin,s,cout); input a,b,cin; output s,cout; wire p,q,r; xor(s,a,b,cin); and(p,a,b); and(q, b,cin); and(r,a,cin); or(cout,p,q,r); endmodule

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

HALF SUBTRACTOR:

LOGIC DIAGRAM:

TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 BORROW 0 1 0 0 DIFFERENCE 0 1 1 0

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROGRAM FOR HALF SUBTRACTOR: module halfsubtractor(a,b,diff,borrow); input a,b; output diff,borrow; xor(diff,a,b); not(a1,a) and(borrow,a1,b); endmodule

FULL SUBTRACTOR:
LOGIC DIAGRAM: FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:
A B C BORROW DIFFERENCE

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 1 1 0 0 0 1

0 1 1 0 1 0 0 1

PROGRAM FOR FULL SUBTRACTOR: module fullsubtractor(a,b,cin,diff,bout); input a,b,cin; output diff,bout; wire p,q,r; xor(s,a,b,cin); not (a1,a) and(p,a1,b); and(q,b,cin); and(r,a,cin); or(cout,p,q,r); endmodule

PROCEDURE:
i) ii) iii) iv) v) vi) vii) viii) Open project navigator. Go to the file and click the new project Type the project name as synthesis The property wizard is open to check all properties such as product, categories, family, device etc. then click next Create new source wizard appears then click next Project summary is displayed then click next Go to the project and click new source Then type the full name half adder as well as select verilog module then click next

Einstein College of Engineering Page 47 of 108

Sub Code: CS37 ix) x) xi) xii) xiii) xiv) Define module window here we assign the input and output of half adder, clicks next and click finish Type the program and save it Make sure that the source is in BEHAVIOUR Then click the ISE simulator and view the signal window Force the input data corresponding circuit Simulate the program using ISE simulator

RESULT:

EXPT. NO. : 12 DATE :

DESIGN OF MULTIPLEXER AND DE-MULTIPLEXER USING VERILOG HARDWARE DESCRIPTION LANGUAGE AIM:
To write the HDL program for designing multiplexer and de-multiplexer circuit and simulate it.

SOFTWARE USED:
XILINK ISE Simulator

THEORY:
MULTIPLEXER: A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2^n inputs lines and n selection lines whose bit combinations determine which input is selected. In a 4 to 1 line multiplexer, the four input lines, I0 to I3 is applied to one input of an AND gate. Selection lines S1 and S0 are decoded to select a particular AND Einstein College of Engineering Page 47 of 108

Sub Code: CS37 gate. A multiplexer is also called a data selector, since it selects one of many inputs and steers the binary information to the output line.

DEMULTIPLEXER: The demultiplexer does the reverse operation of a multiplexer. It can be used to separate the multiplexed signal into individual signals, The select input code determines to which output the data input will be transmitted. The number of output lines is n and the number of select lines is m, where n=2^m. The input data is transmitted to one of the output di by means of select signals a,b. The 4-bit adder adds the input a & b and produces the 4-bit sum as the output.

LOGIC DIAGRAM FOR MULTIPLEXER:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:
S1 0 0 1 1 S0 0 1 0 1 Y = OUTPUT D0 D1 D2 D3

PROGRAM FOR MULTIPLEXER: module mux(d0,d1,d2,d3,s0,s1,f); input d0,d1,d2,d3,s0,s1; output f; wire ns1,ns0,p,q,r,s; not (ns1,s1); not(ns0,s0); and(p,ns0,ns1,i0); and(q,s0,ns1,i1); and(r,ns0, s1,i2); and(s,s0, s1,i3); or(f,p,q,r,s); endmodule

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

LOGIC DIAGRAM FOR DEMULTIPLEXER:

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

TRUTH TABLE:

INPUT S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 I/P 0 1 0 1 0 1 0 1 D0 0 1 0 0 0 0 0 0 D1 0 0 0 1 0 0 0 0

OUTPUT D2 0 0 0 0 0 1 0 0 D3 0 0 0 0 0 0 0 1

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

PROGRAM FOR DE-MULTIPLEXER: module demux(a,b,s,do,d1,d2,d3); input a,b,s; output d0,d1,d2,d3; wire a1,b1; not (a1,a); not(b1,b); and(d0,b1,a1,s); and(d1,b,a1,s); and(d2,b1,a,s); and(d3,b,a,s); endmodule

PROCEDURE:
i) ii) iii) iv) v) vi) vii) viii) Open project navigator. Go to the file and click the new project Type the project name as synthesis The property wizard is open to check all properties such as product, categories, family, device etc. then click next Create new source wizard appears then click next Project summary is displayed then click next Go to the project and click new source Then type the full name half adder as well as select verilog module then click next Einstein College of Engineering Page 47 of 108

Sub Code: CS37 ix) x) xi) xii) xiii) xiv) Define module window here we assign the input and output of half adder, clicks next and click finish Type the program and save it Make sure that the source is in BEHAVIOUR Then click the ISE simulator and view the signal window Force the input data corresponding circuit Simulate the program using ISE simulator

RESULT:

VIVA QUESTIONS
1. Define Digital systems?

2. What are the advantages of digital system?

3. Define i) Nibble ii) Byte

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

4. What are the applications of octal number system?

5. What are the basic digital logic gates?

6. What is a Logic gate?

7. Define Inverter.

8. Which gates are called as the universal gates?

9. Which gate is equal to AND-invert Gate?

10. Which gate is equal to OR-invert Gate?

11. Bubbled OR gate is equal to _______________

12. Bubbled AND gate is equal to _______________

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

13. What is the application of EXNOR gate?

14. Define codes.

15. What are the steps involved in Excess-3 addition.

16. Show that the Excess-3 code is self complementing.

17. What is gray code?

18. Classify the five groups of codes.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

19. What are the steps involved for converting binary number from gray code.

20. What are the steps involved for converting Gray code from binary number.

21. What is meant by minterm and maxterm?

22. Why are Demorgans theorems used?

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

23. What is K-map?

24. List the six steps in simplifying a Boolean expression using a Karnaugh map.

25. How to convert minterm-to-maxterm or maxterm-to-minterm?

26. What are dont care conditions?

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

27. What is a Combinational logic circuit? What are their important features?

28. What is half adder?

29. What is full adder?

Einstein College of Engineering Page 47 of 108

Sub Code: CS37 30. What is an Encoder?

31. What is Decoder?

32. Define Code converter and give some example.

33. How does LED operate?

34. What is a multiplexer?

35. What are the advantages of using multiplexer?

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

36. What are the design procedures available for using the multiplexer as a logic element?

37. Give few examples of data selector or multiplexer applications.

38. What is a demultiplexer?

39. What is a comparator?

40. What is a sequential circuit?

41. What is a flip-flop?

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

42. What are the characteristics of a clocked R-S flip flop?

43. Give some applications of clocked RS flip flop.

44. Define D-flip flop.

45. Give some applications of D-flip flop.

46. Define J-K flip flop.

47. Define propagation delay time.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

48. What is a counter?

49. What is a ripple counter?

50. Compare Synchronous and Asynchronous counter.

Asynchronous counter

Synchronous counter

51. Define up-down binary counter.

Einstein College of Engineering Page 47 of 108

Sub Code: CS37 52. What are the uses of counters?

53. What are the two types of shift-register counters?

54. What is shift register?

55. Give the classifications of shift registers.

56. Define unidirectional shift register.

57. Define bidirectional shift register.

58. Define universal shift register

Einstein College of Engineering Page 47 of 108

Sub Code: CS37

59. What are the applications of shift register?

60. How the shift register used for time delay?

Verilog HDL: 61. Give the different arithmetic operators?

62. Give the different bitwise operators.

Name the types of ports in Verilog.

Einstein College of Engineering Page 47 of 108