2L3L INVERTER

E. C. dos Santos Jr. and J. H. G. Muniz and E. R. C. da Silva

Electrical Engineering Department Federal University of Campina Grande 58109-970 Campina Grande - PB - Brazil e-mail: euzeli@dee.ufcg.edu.br

Abstract- This paper proposes a single-phase inverter with four levels at the output converter side. The proposed inverter can be considered as an intermediate conguration between the 3-level 4-switch H-bridge and 5-level 8-switch H-bridge topologies. It is called as 2L3L inverter, since it is composed of one two-level leg and one threelevel leg. The most important characteristics of the proposed conguration are: reduced number of semiconductor devices, the same blocking voltage for all switching devices, and no low frequency current circulating in dc-link capacitors. Details regarding the operation of the conguration and modulation strategy is presented, as well as the comparison between the proposed H-bridge inverter and the conventional NPC four-level inverter. Simulated and experimental results are presented to validate the theoretical expectations. I. Introduction Multi-level converters were rst conceived for highvoltage and high-power applications beginning with the NPC inverter proposed by [1]. Since then, many congurations have been proposed [2, 3] to establish the highly desirable characteristics for high-power applications, such as reduced waveform distortion and low blocking voltage by switching devices [4] . The three principal congurations are diode-clamped (or NPC), ying capacitor and cascade multi-level inverters [5, 6]. More recently, the multi-level converters has found acceptance in low power applications, especially in photovoltaic applications, since it is possible to generate high-quality voltage waveforms with power semiconductor switches operating at a frequency near the fundamental [7] and the number of the input dc-sources, for this application, is not longer restricted [8]. Even considering just one dc voltage source available, it is possible to employ multi-level converters with dierent dc-link voltages using additional circuitry [9]. Dc-ac multi-level converters for single-phase output voltage has been also explored in the technical literature due to its importance in low power applications [1015]. In [16] was proposed a single-phase multilevel converter for application in electried railway, while in [17] was proposed a family of single-phase multi-level inverters without clamping diodes and ying capacitors. The single978-1-4577-1646-1/11/$26.00 2011 IEEE

phase converter in [18] uses two asymmetrical 4-level converters to generate the proposed hybrid cascade converter. Four-level inverters conceived for single-phase applications were explored in [6, 1921]. This paper proposes a single-phase inverter with fourlevels at the output converter side. The proposed Hbridge topology is depicted in Fig. 1. Such conguration needs three dc sources, which can be obtained through a set of PV arrays, as in [22], or from a unique PV array and with additional circuitry, as in [6]. The proposed inverter can be considered as an intermediate conguration between the 3-level 4-switch H-bridge topology, as observed in Fig. 2(a) and the 5-level 8-switch H-bridge topology, as observed in Fig. 2(b). Then, following this nomenclature, the proposed 2L3L inverter is a 4-level 6-switch H-Bridge topology. The most important characteristics of the proposed circuit is: reduced number of semiconductor devices, specifically of the diodes, the same blocking voltage for all switching devices, and no low frequency current circulating in dc-link capacitors. Details regarding the conguration model, operation and modulation strategy is presented, as well as the comparison between the proposed inverter and the conventional single-phase four-level NPC inverter, as observed in Fig. 3. This topology was considered in the comparison, since it has the same number of switches and generates the same number of levels. Simulated and experimental results are presented to validate

Fig. 1. : 2L3L inverter topology.

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(a)

(b)

Fig. 2. : Conventional conguration and its output voltage waveform. (a) 3-level 4-switch H-bridge topology. (b) 5-level 8-switch H-bridge topology. the theoretical expectations. II. Operation of the 2L3L Inverter The proposed H-bridge is constituted by six controlled switches (S1 , S 1 , S2 , S 2 , S3 , S 3 ), two clamping diodes, three dc sources, and four dc-link capacitors. The switches S1 , S 1 , S2 and S 2 are used to compose the threelevel leg (3L), while the switches S3 and S 3 are used to compose the two-level leg (2L), the switches S1 , S2 , S3 are complementary to the switches S 1 , S 2 , S 3 , respectively. To guarantee a symmetrical output voltage, it is necessary to make V1 = V3 = 0.5V2 = V . As observed in Fig. 1, the single-phase load is connected to the points a and b, then vl = va0 vb0 where va0 va0 va0 = = = 2V if {s1 =s2 =1} 0 if {s1 =s2 =1} 2V if {s1 =s2 =0} (1) TABLE I: Output voltage considering all switching states available. State {S1 S2 S3 } vl 1 {0 0 0} V 2 {0 0 1} 3V 3 {0 1 0} V 4 {0 1 1} V 5 {1 1 0} 3V 6 {1 1 1} V and vb0 vb0 = = V if {s3 =1} V if {s3 =0}

with sj (j = 1, 2, 3) representing the conduction states of the switches Sj (j = 1, 2, 3), with sj = 1 for the turned-on switch and sj = 0 for the turned-o switch (sj = 1 sj ). Considering all possibilities of switching states available, the output voltage is determined by Table I. From this table is possible to observe that there are four levels for vl . Considering dc sources with dierent values, it is possible to increase the number of levels at the output side of the proposed H-bridge. However, this is not considered in this paper since the voltage ratings of the switches will be dierent, implying in an irregular distribution of the stress in the switches. III. Modulation Strategy The modulation strategy employed for the 2L3L inverter topology is a combination of the two-level and three-level PWM approaches, which means that, for the two-level leg (2L) it will be employed just one triangular carrier signal, while for the three-level leg (3L) it will be employed two triangular carrier signals, as observed in Fig. 4. From (1) is possible to write the following relations for the reference pole voltage
va 0 = vl /2

(2) (3)
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Fig. 3. : Conventional four-level NPC conguration.

vb 0 = vl /2.

(a)

(b)

(c)

Fig. 4. : Sine-triangle modulation waveforms for: (a) vl > 0. (b) vl = 0. (c) vl < 0.

The switching states of the power switches are obtained by comparing the reference pole voltage with the trian gular waveforms, i.e., the voltage va 0 will be compared to vt1 and vt2 to dene the switching states of S1 and S2 , respectively; while the voltage vb 0 will be compared to vt3 to dene the switching state of S3 . Fig. 4 shows, from top to bottom, the reference pole voltage (va 0 and vb0 ), state of the switches (S1 , S2 and S3 ), pole voltages (va0 and vb0 ) and load voltage (vl ). Figs. 4(a), 4(b) and 4(c) show these variables for vl > 0, vl = 0 and vl < 0, respectively. From this gure is possible to observe the generation of the four levels. IV. Capacitor Voltage balance The capacitor voltage balance of the capacitors C2 and C3 is obtained naturally with the modulation strategy used in Fig. 4. Such natural balance can be explained by the capacitor current, which guarantees capacitor charging and discharging, as observed in Fig. 5. This gure shows the capacitor current path considering all switching states. Figs. 5(a)-(d) highlight the capacitor current for il > 0, while Figs. 5(e)-(h) highlight the capacitor current for il < 0. Notice that, after a sinusoidal period, the charging and discharging of the capacitors C2 and C3 are guaranteed by il . As far as the capacitors C1 and

C4 are connected directly to individual dc sources (V1 and V3 , respectively) their balance strategy is no longer necessary. V. General Comparison In this section will be presented a comparison between the proposed conguration (see Fig. 1) and the conventional one (see Fig. 3). Three aspects will be considered in this comparison, i.e., the number of semiconductor devices, the WTHD (Weighted Total Harmonic Distortion) of the load voltage, and the capacitor current in the dclink capacitors. A. Number of devices By a direct comparison, the proposed conguration presents a reduced number of components, with a reduction of two diodes. Furthermore, the dc-link mid-point connection of the proposed conguration is conceived just to guarantee the zero voltage in the three-level leg, which means no low frequency current owing through the capacitors. On the other hand, the dc-link mid-point connection in the conventional congurational is conceived to guarantee the load connection, which means that a low frequency current (il ) owing through the capacitors C2 and C3 .
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S1 - on S2 - on S3 - on
S1 S3 S2

S1 - on S2 - on S3 - on
S1

il

S3

S2

il

S3

S1 S2

S3

S1 S2

(a)
S1 - on S2 - on S3 - on
S1 S3 S2

(b)
S1 - on S2 - on S3 - on
S1

il

S3

S2

il

Fig. 6. : WTHD of the load voltage as a function of the modulation index obtained by simulation. B. Harmonic Distortion of the load voltage

S3

S1 S2

S3

S1 S2

The WTHD (Weighted Total Harmonic Distortion) has been computed by using W T HD(p) = 100 a1
p i=2

(c)

(d)

S1 - on S2 - on S3 - on
S1 S3 S2

S1 - on S2 - on S3 - on
S1

ai i

(4)

il

S3

S2

il

S3

S1 S2

S3

S1 S2

(e)

(f)

S1 - on S2 - on S3 - on
S1 S3 S2

S1 - on S2 - on S3 - on
S1

where a1 is the amplitude of the fundamental voltage, ai is the amplitude of ith harmonic and p is the number of harmonics taken into consideration. Fig. 6 shows the WTHD of load voltage (vl ) of the conventional and proposed congurations as a function of the modulation index. As expected, the harmonic distortion reduces as far as the index modulation increases for both proposed and conventional converters. For all modulation indexes considered, the proposed converter presents always lower values of WTHD compared with the conventional ones, which can be explained by lower oscillation in the dc-link capacitor voltages for the proposed circuit. C. Capacitor Currents The RMS (Root Mean Square) current observed in the capacitors of the extremities (C1 and C4 ) are almost the same for both 2L3L inverter and conventional NPC topology, while the current of the interior capacitors (C2 and C3 ) present a reduction of 36% in the proposed topology, which could be explained through the connection of the load directly to those capacitors in the NPC conguration. VI. Simulated and Experimental Results To verify the validity of the proposed H-bridge conguration with four levels, experimental set-up was implemented by IGBTs from SEMIKRON controlled by DSP TMS320F28335. The single-phase RL load was connected
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il

S3

S2

il

S3

S1 S2

S3

S1 S2

(g)

(h)

Fig. 5. : Capacitor current path considering all switching states: (a)-(d) for il > 0 and (e)-(h) for il < 0.

to the output converter with R=65 and L=7mH . Three dc sources with 75V each have been also employed. The dc-link capacitors were of C = 2200F each. Fig. 7(a) shows the simulated results for the proposed H-bridge conguration. The waveforms presented in this gure are, from top to bottom: pole voltage in the twolevel leg (vb0 ); pole voltage in the three-level leg (va0 ); load voltage (vl ) and load current (il ). The same set of waveforms are shown in Fig. 8(a) for the experimental results. Figs. 7(b) and 8(b) show simulated and experimental results indicating the load voltage (vl ), capacitor voltages (vc2 and vc3 ) and load current (il ). From Figs. 7 and 8 it is evident the agreement between simulated and experimental results. It is worth to mention that the dc-link capacitor voltages of C2 and C3 are balanced without any special technique. As discussed in the theoretical analysis, the capacitor balancing is naturally achieved with the modulation strategy employed.

(a)

(b)

(a)

Fig. 8. : Experimental results. (a) (From top to bottom) pole voltage in the two-level leg, pole voltage in the threelevel leg, load voltage and load current. (b) (From top to bottom) load voltage, capacitor voltages vc2 and vc3 and load current. VII. Conclusion A single-phase inverter with four levels at the output converter side is proposed in this paper, it is called as 2L3L inverter. The proposed inverter is constituted by one two-level leg and three-level leg presenting the same blocking voltage for all switching devices. A comparison between the proposed conguration and the conventional four-level inverter is presented, where three advantages are observed for the 2L3L inverter, i.e., the number of semiconductor devices, the WTHD of the load voltage and the capacitor current in the dc-link capacitors. Simulated and experimental results demonstrate the feasibility of the proposed converter. REFERENCES [1] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped pwm inverter, Industry Applications, IEEE Transactions on, vol. IA-17, pp. 518 523, Sept. 1981.
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(b)

Fig. 7. : Simulated results. (a) (From top to bottom) pole voltage in the two-level leg, pole voltage in the threelevel leg, load voltage and load current. (b) (From top to bottom) load voltage, capacitor voltages vc2 and vc3 and load current.

[2] S. Mariethoz and A. Rufer, New congurations for the three-phase asymmetrical multilevel inverter, in Industry Applications Conference, 2004. 39th IAS Annual Meeting. Conference Record of the 2004 IEEE, vol. 2, pp. 828 835 vol.2, Oct. 2004. [3] H. Weng, K. Chen, J. Zhang, R. Datta, X. Huang, L. Garces, R. Wagoner, A. Ritter, and P. Rotondo, A four-level converter with optimized switching patterns for high-speed electric drives, in Power Electronics Specialists Conference, 2007. PESC 2007. IEEE, pp. 1585 1591, June 2007. [4] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. Franquelo, B. Wu, J. Rodriguez, M. Pe andrez, and J. Leon, Recent advances and industrial applications of multilevel converters, Industrial Electronics, IEEE Transactions on, vol. 57, pp. 2553 2580, Aug. 2010. [5] P. Chan, H.-H. Chung, and S. Hui, A generalized theory of boundary control for a single-phase multilevel inverter using second-order switching surface, Power Electronics, IEEE Transactions on, vol. 24, pp. 2298 2313, Oct. 2009. [6] A. Boora, A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, Voltage-sharing converter to supply single-phase asymmetrical four-level diode-clamped inverter with high power factor loads, Power Electronics, IEEE Transactions on, vol. 25, pp. 2507 2520, Oct. 2010. [7] E. Villanueva, P. Correa, J. Rodriguez, and M. Pacas, Control of a single-phase cascaded hbridge multilevel inverter for grid-connected photovoltaic systems, Industrial Electronics, IEEE Transactions on, vol. 56, pp. 4399 4406, Nov. 2009. [8] E. Ozdemir, S. Ozdemir, and L. Tolbert, Fundamental-frequency-modulated six-level diodeclamped multilevel inverter for three-phase standalone photovoltaic system, Industrial Electronics, IEEE Transactions on, vol. 56, pp. 4407 4415, Nov. 2009. [9] A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, A hybrid cascade converter topology with seriesconnected symmetrical and asymmetrical diodeclamped h-bridge cells, Power Electronics, IEEE Transactions on, vol. 26, pp. 51 65, Jan. 2011. [10] S. Daher, J. Schmid, and F. Antunes, Multilevel inverter topologies for stand-alone pv systems, Industrial Electronics, IEEE Transactions on, vol. 55, pp. 2703 2712, july 2008. [11] R. Gonzalez, E. Gubia, J. Lopez, and L. Marroyo, Transformerless single-phase multilevel-based photovoltaic inverter, Industrial Electronics, IEEE Transactions on, vol. 55, pp. 2694 2702, July 2008. [12] E. Babaei, A cascade multilevel converter topology with reduced number of switches, Power Electronics, IEEE Transactions on, vol. 23, pp. 2657 2664, Nov. 2008. [13] B. Lin and C. Huang, Single-phase switching-mode rectier with capacitor-clamped topology, Electric

[14]

[15]

[16]

[17]

[18]

[19]

[20]

[21]

[22]

Power Applications, IEE Proceedings -, vol. 152, pp. 9 16, Jan. 2005. H. Radermacher, B. Schmidt, and R. De Doncker, Determination and comparison of losses of single phase multi-level inverters with symmetric supply, in Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35th Annual, vol. 6, pp. 4428 4433 Vol.6, June 2004. R. Li, N. Froleke, and J. Bocker, Analysis and design of a novel three-level llcc inverter supplying an airborne piezoelectric brake actuator, in Power Electronics Specialists Conference, 2007. PESC 2007. IEEE, pp. 2155 2161, June 2007. S. Rahmani and K. Al-Haddad, A single phase multilevel hybrid power lter for electried railway applications, in Industrial Electronics, 2006 IEEE International Symposium on, vol. 2, pp. 925 930, July 2006. A. Chen, C. Zhang, H. Ma, and Y. Deng, A novel multilevel inverter topology with no clamping diodes and ying capacitors, in Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE, pp. 3184 3187, Nov. 2008. T. Tang, J. Han, L. Zhou, P. Yao, and X. Tan, Novel hybrid cascade asymmetrical converter based on asymmetrical converter, in Industrial Electronics, 2007. ISIE 2007. IEEE International Symposium on, pp. 1004 1008, June 2007. A. Ruderman, B. Reznikov, and S. Thielemans, Four-level h-bridge ying capacitor converter voltage balance dynamics analysis, in Industrial Electronics, 2009. IECON 09. 35th Annual Conference of IEEE, pp. 498 503, Nov. 2009. B. Reznikov and A. Ruderman, Four-level singleleg ying capacitor converter voltage balance dynamics analysis, in Power Electronics and Applications, 2009. EPE 09. 13th European Conference on, pp. 1 10, Sept. 2009. A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, A hybrid cascade converter topology with seriesconnected symmetrical and asymmetrical diodeclamped h-bridge cells, Power Electronics, IEEE Transactions on, vol. 26, pp. 51 65, Jan. 2011. R. Stala, Individual mppt of photovoltaic arrays with use of single-phase three-level diode-clamped inverter, in Industrial Electronics (ISIE), 2010 IEEE International Symposium on, pp. 3456 3462, July 2010.

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