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by Agung Wibowo, Dr. Eng.

Noise is unwanted voltage that is induced in electrical circuits and present a threat to the proper operation of the circuit. The noise immunity is the ability to tolerate a certain amount of unwanted voltage fluctuation on its inputs without changing its output state.
Example :
If noise voltage causes the input of a 5 V CMOS gate to drop below 3.5 V in HIGH state, the input is in the unacceptable region and operation is unpredictable . Thus, the gate may interpret the fluctuation below 3.5 V as a LOW level. Similarly, if noise causes a gate input to go above 1.5 V in the LOW state , uncertain condition is created.

A measure of a circuits noise immunity is called the noise margin, which is expressed in volt.

There are two value of noise margin specified for a given logic circuit : The HIGH-level noise margin (VNH) The LOW-level noise margin (VNL)
VNH is the difference between the lowest possible HIGH output from a driving gate (VOH(min)) and the lowest possible HIGH input that the load gate can tolerate (VIH(min)). VNH = VOH(min) VIH(min)

VNL is the difference between the maximum possible LOW input that a gate can tolerate (VIL(max)) and the maximum possible LOW output of driving gate (VOL(max)) VNL = VIL(max) VOL(max)

VNH = ? VNL = ?

1.1 v


0.4 v


VNL = VIL(max) VOL(max)

2.4 v


0.75 v


VNH = VOH(min) VIH(min)

A logic gate draws current from the dc voltage source. When the gate is in HIGH output state, an amount of current designated by ICCH is drawn, In LOW output state, a different amount of current, ICCL, is drawn. The power dissipation in a static (non changing) HIGH output state is : PD = VCC x ICCH The power dissipation when the gate is pulsed, its output switch back and forth between HIGH and LOW, the amount of supply current varies between ICCH and ICCL. The average power dissipation depend on the duty cycle and usually specified for a duty of 50%. For 50% duty cycle : ICC = (ICCH + ICCL)/2 The average power dissipation is : PD = VCC x ICC

When signal passes (propagates) through a logic gate, it always experiences a time delay. There are two propagation delay time specified for logic gates : tPHL , the time between a designated point on input pulse and the corresponding on the output pulse when the output is changing from HIGH to LOW. tPLH, the time between a designated point on input pulse and the corresponding on the output pulse when the output is changing from LOW to HIGH.

When the output of a logic is connected to one or more inputs of other gates, a load on the driving gate is created. There is a limit to the number of load gate inputs that a given gate can drive. This limit is called the fan-out of the gate.

Metal-oxide semiconductor field effect transistor (MOSFETs) are active switching elements in CMOS circuits This devices differ greatly in construction and internal operation from bipolar junctions transistor used in bipolar (TTL) circuits, but switching action is basically the same : they function ideally as open and closed switches depending on the inputs. When the gate voltage of an n-channel MOSFET is more positive than the source, the MOSFET is ON (saturation). When the gateto- source voltage is zero, the MOSFET is off (cutoff). The p-channel MOSFET operates with opposite voltage polarities.

Complementary MOS (CMOS) logic uses the MOSFET in complementary pairs as its basic element. When a HIGH is applied to the input, the p-channel MOSFET Q1 is OFF and the n-channel MOSFET Q2 is ON This condition connect the output to ground through the on resistance of Q2, resulting in a LOW output. When a LOW is applied to the input, Q1 is ON and Q2 is OFF This condition connect the output to + VDD (dc supply voltage) through the on resistance of Q1, resulting in a HIGH output.

The bipolar junction transistor (BJT) is the active switching element used in all TTL circuit.

The basic switching operation is as follows: When the base is approximation. 0.7 V more positive than the emitter and when sufficient current is provided into base, the transistor turn on and goes into saturation. In saturation, the transistor ideally act like a closed switch between collector and the emitter. When the base less than 0.7 V more positive than the emitter, the transistor turns off and become an open switch between the collector and the emitter. Summarize : a HIGH on the base turns the transistor ON and make it a closed switch . A LOW on the base turns the transistor OFF and make it an open switch.

In TTL some BJTs have multiple emitter.

Transistor Q1 is the input coupling transistor, and D1 is the input clamp diode. Transistor Q2 is called a phase splitter and combination of Q3 and Q4 forms the output circuit often referred to as a totem-pole arrangement.

When the input is HIGH, the base-emitter junction of Q1 is reverse-biased, and the base collector junction is forward-biased. This condition permits current through R1 and the basecollector junction of Q1into the base Q2, thus driving Q2 into saturation (on). Q3 is turn on by Q2, and its collector voltage, which is the output, is near ground potential. Therefore the output is LOW. At the same time, the collector of Q2 is at a sufficiently low voltage level to keep Q4 off. When the input is LOW, the base-emitter junction of Q1 is forward-biased, and the baseemitter junction is the reverse-biased. There is current through R1 and base-emitter junction of Q1 to the LOW input. A LOW provide a path to ground for the current. There is no current into the base of Q2, so it is off. The collector of Q2 is HIGH, thus turning the Q4 on. A saturated Q4 provides a low-resistance path from VCC to the output. Therefore the output become HIGH for a LOW on the input. At the same time, the emitter of Q2 is at ground potential, keeping the Q3 off.

Basically, it is the same as the inverter circuit except for the additional input emitter of Q1.

In TTL technology, multiple emitter transistor are used for the input devices.
These multiple-emitter transistor can be compared to diode arrangement. A LOW on either input A or input B forward-biases the corresponding diode and reverse-biases D3 (Q1 vase-collector junction) . This action keeps Q2 off and results in a HIGH output A LOW on both inputs will do the same thing. A HIGH on both inputs reverse-biases both input diodes and forward-biases D3 (Q1 base-collector junction). This action turns Q2 on and results in a LOW output.