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4, ISSN: 1837-7823
1. Introduction
Our surrounding world is analog in nature. Digital systems require an analog to digital conversion at the front of the system and digital to analog conversion at its end. Analog computation and signal processing make it simpler and faster [1]. Analog signal processing represents the signals as physical quantities like e.g. charge, current, voltage or frequency. These signals are continuous in time. One of the essential components in analog circuit design is the analog multiplier. In electronics, an analog multiplier is a device, which takes two analog signals as input and produces an output, which is proportional to their product. An Analog multiplier is an important sub circuit for many applications such as adaptive filters and frequency modulators [2]. They are widely used in contemporary VLSI chips for modulation/demodulation, other non-linear operations including division, square rooting as well as frequency conversion. In most of the mentioned applications, the required features of the multiplier are good isolation between input and output ports (especially for RF systems), wide input dynamic range, wide bandwidth, symmetric input to output delay in communication systems, low power dissipation and low supply voltage [3]. Most of the analog multipliers are based on the MOSFET square law approximation of the drain current either in saturation region or triode region [4] or Gilbert cell. To implement the multipliers in IC technologies, the Gilbert cell is a popular and the oldest structure in IC technologies due to wide dynamic range and high frequency performance [5]. The Gilbert cell uses the cascaded differential pair to expand the input voltage range for 4-quadrant multiplications [6].
1.2 Type Of Multiplication 1.2.1 On the Basis of Polarity of One or the Both Inputs
a) b) c) Single quadrant multiplier Two quadrant multiplier Four quadrant multiplier
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International Journal of Computational Intelligence and Information Security, April 2013, Vol. 4 No. 4, ISSN: 1837-7823 If a particular multiplier circuit is designed to accept only one polarity of input on each of its inputs i.e. both inputs must be positive, then its operation will be limited to single quadrant & it will call one quadrant or a single quadrant multiplier. Single quadrant multiplier is shown in Fig. 1 where VX & VY both are the input voltages.
1.2.2
a) Voltage Multiplier
When output current is proportional to the product of the two input voltages then multiplier is known as voltage multiplier [7].
b) Current Multiplier
When output current is proportional to the product of the two input currents then multiplier is known as current multiplier. The current-mode operation of the multiplier circuits has the important advantage of 35
International Journal of Computational Intelligence and Information Security, April 2013, Vol. 4 No. 4, ISSN: 1837-7823 increasing the frequency response of the designed structures [7]. .
2. Existing 12 T Multiplier
For providing the load, use of resistors may require external resistors, which occupy a large chip area to implement in IC form and also cause of the multiplier frequency degradation [8] .
In this circuit, transistor MP1, MP2 and MP3 act as a current mirror. The current mirror used to provide the active load. Transistor M1, M2, M3, M4, M5 and M6 from the Gilbert cell architecture. M7 and M8 are the bias transistors, used to provide the constant current [9]. Outp and Outn are the positive and negative terminals respectively, of output VOUT as shown in Fig. 4.
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International Journal of Computational Intelligence and Information Security, April 2013, Vol. 4 No. 4, ISSN: 1837-7823 Outp and Outn are the positive and negative terminals respectively, of output VOUT. The threshold voltage of improved multiplier is reduced as compared to the Existing 12T multiplier because of the all body terminal of nMOS transistors are connected to the ground. So that the power consumption, delay, power delay product and output swings are less than the Existing 12T multiplier in pre layout simulations. Layout Design of improved multiplier is shown in Fig. 6. The property of the Gilbert cell is that the gain of the differential amplifier can be controlled by the tail current [11]. The drain current is a function of both the gate source and body source voltages. The gate source voltage controls the vertical electric fields, which controls the channel conductivity and therefore drain current. On the other hand, body source voltage changes the threshold voltage, which changes the drain current when the gate source voltage is fixed. This effect stems from the influence of the substrate acting as the second gate and is called the body effect [12]. In analog circuit designs, body effect is an important parameter
2 F
Where is Vtn the threshold voltage with zero VSB (i.e. source to substrate voltage).
2qN A si C OX
The factor is called the body-effect constant and has unit of V . Body-effect constant ( ) is proportional to the substrate doping density ( N A ), so the body effect is larger for the transistors in the well where typically doping is higher than the substrate of the microcircuit [13].
International Journal of Computational Intelligence and Information Security, April 2013, Vol. 4 No. 4, ISSN: 1837-7823 transistor at the output terminal as shown in Fig. 7.
Figure 7: Proposed Low pass filter The advantage with this approach over conventional active-filter configurations is that the overall characteristic cutoff frequency, 0, will be directly proportional to a multiplying input voltage. This permits the construction of filters in which the capacitors are adjustable (directly or inversely) by a control voltage. Hence, the frequency scale of a filter can be manipulated by means of a single voltage without affecting any other parameters.
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International Journal of Computational Intelligence and Information Security, April 2013, Vol. 4 No. 4, ISSN: 1837-7823
4. Simulation Result
All simulations have been performed on Tanner EDA tool at 45 nm technolgy with the aspect ratio of all transistor is taken 1.
Fig. 9 shows the post layout transient response of improved multiplier.. In Post simulations of Existing multiplier there will be one extra layer as compare to improved multiplier because all the nMOS transistors have not same body biasing so that power consumption, delay, power-delay product and output swings will be more in existing 12T multiplier. Fig. 10 and Fig. 11 depicts the output of low pass filter and high pass filter respectively. The cutoff frequency for the low pass filter is 4MHz, which means above that frequency it will block all higher frequency components. The cutoff frequency of the high pass filter is 1.07MHz, which means below that frequency it will block all lower frequency components. The order of these filters can be changed by changing the input voltage.
Table 1: Power Consumption, Delay, Power-Delay Product and Output Swings of multiplier layout
V1 (mv)
Delay (sec)
10 20 30 40 50
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International Journal of Computational Intelligence and Information Security, April 2013, Vol. 4 No. 4, ISSN: 1837-7823
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International Journal of Computational Intelligence and Information Security, April 2013, Vol. 4 No. 4, ISSN: 1837-7823
References
[1] [2] [3] Bogdan M. Wilamowski, (1998), VLSI Analog Multiplier/divider Circuit, International Symposium on Industrial Electronics, pp. 493-496. Chunhong Chen, and Zheng Li A Low-Power CMOS Analog Multiplier, (2006), IEEE Transactions on Circuits And SystemsIi: Express Briefs, VOL. 53, NO. 2. Witold Machowski, Stanisaw Kuta, Jacek Jasielski and Wojciech Koodziejski, (2010), Broadband quarter-square 4Q analog multiplier based on CMOS inverters International Conference on Signals and Electronic Systems (ICSES), pp. 237 240. M. Dei, N. Nizza, G. M. Lazzerini, P. Bruschi and M. Piotto (2009)A Four Quadrant Analog Multiplier Based on a Novel CMOS Linear Current Divider Research in Microelectronics and Electronics, pp. 128131. Amir H. Miremadi, Ahmad Ayatollahi, Adib Abrishamifar, (2011), A Low Voltage Low Power CMOS Analog Multiplier, NORCHIP,pp. 001-004. Yani LI, Yintang YANG, Zhangrning ZHU, and Wei Qiang , (2011),A Novel Low THD 4-Quadrant Analog Multiplier Using Feedforward Compensation for PFCASIC (ASICON), IEEE 9th International Conference, pp.878-881. Cosmin Radhu Popa, (2011), Synthesis of Computational Structures for Analog Signal Processing, Springer New York Dordrecht Heidelberg London. Alireza Mallahzadeh, Milad Kaboli,Amin Javadi nasab and Behzad Ghanavati, (2010), A Low Voltage High Frequency Four Quadrant Analoge Multiplier, International Conference on Mechanical and Electrical Technology (ICMET 2010), pp. 492 - 495. Chander Shekhar, Low Voltage Low Power Gilbert Cell Based Multiplier, (2011), International Journal of Engineering Research and Applications (IJERA), Vol. 1, Issue 1, pp. 011-014. Komal Mehna and B. P. Singh, (2012), Low Voltage Low Power High Speed Analog Multiplier, International Conference on Technical and Executive Innovation in Computing and Communication (TEICC), pp. 301-304. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill, Edition 2002 Paul R. Gray, Paul J. Hurst, Stephen H. Lewis and Robert G. Meyer Analysis and Design of Analog Integrated Circuits, John Wiley & Sons Pvt. Ltd, Fourth Edition. David A. Johns and Ken Martin Analog Integrated Circuit Design, John Wiley & Sons Pvt. Ltd, Edition 2005. Sanjit K. Mitra, Digital Signal Processing- A Computer Based Approch Tata McGraw-Hill, Second Edition.
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