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Proceedings of the 2n

d
International Conference on Information Technolog, ICIT 2010 28-30 June 2010, Gdansk, Poland.
Flexible Embedded Control System Architecture
for Power Electronics Applications
LOszOkOObOWsk
The Electrotechnical Institute
The Gdansk Branch
Gdansk, Poland
leszek.debowski@iel.gda.pl
Abstract -The paper presents a new fexible architecture of an
embedded control system for power electronics applications. The
hardware part of the system is divided between a CPU module
and a baseboard dedicated for target system arrangement,
depending on application requirements. Flexibility of the
confgration was achieved by using DSP/ARM/CPLD/FPGA
components. The development line of unifed CPUs and a
baseboard family for various power converter topologies and
applications is introduced. Some research, educational and
industrial applications are briefy presented and discussed.
Keywords: power converters, control systems, DSP, FPGA
1. INTRODUCTION
Embedded control systems based on microprocessors and
programmable logic devices are ofen applied in the branch of
industrial electronics, especially in power electronics. Standard
application areas of modem power electronics are continuously
extending in volume and quality, e.g. variable speed drives,
active flters, power conditioners and power supplies. New
emerging product groups are curently under development:
electric vehicles and railways [I], fast battery chargers, power
supplies, photovoltaic and wind energy conversion systems.
A control system is one of the major parts of any power
converter. A controller must support power converter hardware
topology and provide an adequate computing power necessary
for real-time algorithm implementation. The design process of
reliable control systems for advanced power converters is time
consuming and must follow the technology progress in
microlelectronics.
A fexible architecture of a digital control system is
proposed for rapid prototyping and a target application support
in power conversion and intelligent motion control areas. The
system is based on an extended set of integrated circuits
dedicated for signal processing and digital logic function or
peripherial blocks arrangement: digital signal processors
(DSP), ARM microcontrollers and programmable logic devices
(CPLD, FPGA). During last decade DSPs were standard
solutions for real-time control. Currently ARM-based
microcontrollers and feld programmable gate arrays achieve a
competitive technology grade.
II. FLEXIBLE ARCHITECTURE OF CONTROL SYSTEM,
CPU MODULES
The new approach is based on a fexible confguration
which consists of a versatile central processing unit (CPU) and
baseboard suited for target application requirements.
Scalable computational power and I/O blocks of the CPUs
can meet various requirements of power conversion and motion
control algorithms. A suitable CPU module can be specifed
depending on user's programming experiences and application.
It must be also equipped with a dedicated interface for
downloading, executing and debugging user programs in a
target system using specialized development and code
generation tools.
The frst member of a new CPU family is based on a high
speed TMS320F2812/R2812 digital signal processor (Fig. 1,2).
The interal structure of the TMS320F2812 processor includes
the following major blocks: a 128Kx16-bit FLASH memory,
18Kxl6-bit interal RAM, boot ROM with selectable sofware
boot modes and standard math tables, 16 PWM channels with
dead-time generators, 2 incremental encoder interfaces, 12-bit
AID converter with 2x8-channel input multiplexer and 2 S/H
units. The TMS320R2812 has no an interal FLASH memory
and has a 20Kxl6-bit RAM only. In stand-alone operation the
processor must boot the user program fom an exteral
EEPROM.
Figure 1. High-speed 32-bit fxed-point CPU module DLHF2812
189
Figure 2. High-speed 32-bit fxed-point CPU module DLHF2812
The main exteral signals of a plug-in CPU are arranged
into two connectors with standarized pinout topologies: analog
inputs for I/U transducers, control (PWM) and diagnostic
(ERROR) signals and data transmission signal/power supplies.
Sophisticated power electronics applications, especially
new R&D projects, require increased speed and computing
power of the control system. The CPU family must follow the
technological trends. Continuous development and
improvement are required. New CPU concepts are focused on
advanced foating-point DSPs (TMS320F2833x, Delfno,
Sharc) and ARM processors. High-speed FPGAs (Cyclone,
Stratix, Spartan, Vitex, Fusion) can be also used as a mam
processor with parallel processing capabilities (Fig. 3).
Figure 3. Mixed-signal FPGA-based reconfgurable CPU module
III. FLEXIBLE BASEBOARDS FOR POWER ELECTRONICS
The fexible baseboard family was designed to be easily
applied for a wide range of power converter topologies. The
interal architecture of a fexible baseboard consists of the
following major blocks: a programmable logic unit based on a
high-speed CPLD with the capacity of 57011270 logical blocks
and in-system programming capability, 2 fexible interfaces for
power inverter control and diagnostic (6 PWM outputs and 4
diagnostic inputs), 12 analog inputs for voltage/current
transducers, 2/4 analog oututs (811 0112-bit, 073V), 2
incremental encoder inputs (A, B, INDEX signals), 2 relay
outputs (250V
A
cl8A), USB and CAN interfaces,
16/32/641128kB serial EEPROM or FLASH memory, real-time
clock (R TC) with battery backup, power supply and system
supervising unit (Fig. 4, 5).
190
IIUSBI
I lB
Figure 4. Flexible baseboard for power electronics applications - block
diagram of standad version
Figure 5. Efexible baseboard for power electronics - standad version
All exteral digital I/O signal of the baseboard are equipped
with galvanical isolation based on high-speed optocouplers
(l0115MHz). A higher switching speed (up to 150MHz) can be
supported by new generation of isolators with magnetic or
capacitive coupling.
Flexibility of the baseboard family is achieved using a
CPLD chip. Almost all digital I/O signals can be routed to/fom
selected pin of the main processor by a user-defned switching
matrix. Advanced pre-/post-processig of processor signals is
also available inside the CPLD structure. Each PWM signal can
be supplied fom a PWM line of the main processor or sourced
fom a CPLD pin on the baseboard depending on the user
selection (Fig. 6).
Figure 6. Flexible PWM signal generation block
Simple/complex PWM signal correction/generation can be
arranged inside the CPLD (Fig. 7, 8, 9).
ALLK/LLK

AFWM
+ l
Hada
Dca0-Itmc
_
PW
_
|WMX
AFWM_
gmKr
..
..
nmon
t
bKKK _ Da0Ic +
.
r
0I0ck
I^1
..
..
Figure 7. Simple digital block for PWM signal correction
.
LKOK _ @00 N!
..
..
bl0k
..
A,LKCLK
APWMy
+
Pgmle D-mc
APWMy
mm

0wKbl0k
..
1 8 .
I
-
I
U1
; "

.
S
="
CO
'
,
t
Figure 8. Complex digital block for PWM signal generation with paallel bus
LKKLK
AWMy
AWMy
L8@0800
blok
U-m0
I^
ALLKLLK
Figure 9. Complex digital block for PWM signal generation with serial bus
IV. ApPLlCA nONS
An architecture of the fexible control system can be
confgured for many power converter structures. It can be
successflly applied in the research, educational and industrial
areas.
A. Research Applications
Supercapacitors (supercaps) give new possibilities for electric
energy storage and power conditioning. Industrial system faults
have been ofen caused by short-term network voltage
disturbances. It makes possible to replace traditional batter
based UPSs by power conditioners with supercaps. The new
equipment can provide fast response ad recovery time with
optional active fltering. Maitenance costs can be signifcantly
reduced. The Gdansk Branch of the Electrotechnical Institute
has maaged the special R&D project of a high-voltage
supercap-based three-phase power conditioner [2]. Each phase
has a similar structure of the power stage and a separate DSP
controller (Fig. 10, II).
L1 F
LOA
N
Figure 10. Power conditioner - schematic diagram of single phase
Figure 11. 3-phase power conditioner prototype
191
Multilevel current inverter structure analysis and control
algorithm development were proposed as a new Ph.D project
[3]. 3-phase outputs of three power inverters are connected
directly in parallel without any coupling transformer. A fexible
control system with an extended baseboard is used to manage
up to 18 power switches (Fig. 12, 13).
Figure 12. Multilevel current inverter - schematic diagram of power circuits
Figure 13. Multilevel current inverter - experimental setup
B. Educational Applications
The fexible control system architecture is well optimized for
complex AC/DC/AC converters topologies. A precision
sensorless AC drive system (Fig. 14, IS) with bidirectional
energy fow has been designed by a research team of the
Institute of Electrical Machines, Drives and Measurements
(Wroclaw University of Technology, Poland). Another
educational application of the fexible control system has been
developed at the Institute of Control and Industrial Electronics
(Warsaw Institute of Technology, Poland). The current inverter
design was based on SiC power switches [4]. High-speed
vector pulse-width modulation algorithms were implemented
using coupled DSP/CPLD hadware.
192
Figure 14. Precision motion control system with ACIC/AC converter
Figure 15. Precision motion control system - laboratory setup
C Industrial Applications
The presented fexible control system was adapted and
successflly applied to upgrade traditional DC drives in four
Polish integrated metropolita trains EN-S7 (Fig. 16, 17). New
drive systems includes high-voltage IGBTs (6.SkV) and a DSP
based CPU module which enables rapid prototyping,
implementation and testing of improved motion control
algorithms.
Figure 16. Metropolitan train EN-57 with motion control system upgrade
Figure 17. DSP-based motion control system for EN-57
The curent development works ae focused on a new
advanced design of motion control, diagnostic and an auxiliary
power supply system for the new prototype of a heavy electric
locomotive E6ACT (Fig. 10). It features a 6-axis motion
system with 5 MW asynchronous motors. Each axis/motor pair
is supplied fom a separate fequency converter, therefore three
fexible control systems must be used for this project.
Figure 18. Heavy electric locomotive E6ACT prototype with DSP controlled
high-power AC drives
Both presented industrial projects were made by Electric
Traction Depament of the Electrotechnical Institute. It has
been involved i development of electric and electronic
solutions for a wide range of electric traction vehicles (e.g.
locomotives, integrated trains, trams, trolleybuses and electric
cars).
V. HARDWARE TESTING
AND FUTURE DEVELOPMENTS
An advanced test bench for automatic setup and diagnostics
of the fexible control system is currently under development. It
consists of hardware (JT AG emulator, simulation and
monitoring modules) and sofware parts (testing and
visualisation sofware modules for the target system and PC
platform). The industrial versions of the system dedicated for
railway applications are additionally tested i a thermal
chamber and also according to EMC.
It is expected that efcient usage of limited energy
resources coupled with increasing environment protection
requirements will become more important. Combustion
engines are prognosed to be replaced by high-efciency
electric motors (AC, PMSM). Except motors and drives,
power supply systems of electric vehicles can include
functional blocks (batteries, super capacitors, fell cells)
which require effcient intelligent power management units.
These applications will defne future development works.
REFERENCES
[I] M. Frohlich M. , "Technology Trends in Railway Traction". In:
Proceedings of the Interational Conference for Power Electronics,
Intelligent Motion, Power Quality. PCIM 2009, May 12-14 2009,
Nurberg, Germany.
[2] P. Boguslawski , E. Lowiec, "Wielopoziomowy kompensator napicia z
superkondensatorowym zasobnikiem energii - wybrane aspekty
konstrukcyjne", Prace Instytutu Elektrotechniki, Zeszyt 239'08,
Waszawa, Poland, 2008.
[3] L. Wolski, "Wielopoziomowy falownik prdu", Prace Instytutu
Elektrotechniki, Zeszyt 227'06, Warszawa, Poland, 2006.
[4] M. Andrzejewski, 1. Rbkowski, "Modulator dla falownika prdu PWM
o podwyzszonej czstotliwosci - implementacja w procesorze
TMS320F2812", VII Og61nopolska Konferencja Naukowo-Techniczna
"Postpy w Elektrotechnice Stosowanej" (PES-7), Koscielisko, Poland,
2009.
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