2009 Spring CS211 Digital Systems & Lab

CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2)

What will we learn in this chapter?

2

How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs B i characteristics Basic h t i ti of f electronic l t i circuits i it (partially covered)

2009 Spring CS211 Digital Systems & Lab

IC Technology

Outline
4

Anatomy of integrated circuits Full-Custom (VLSI) IC Technology Semi-Custom (ASIC) IC Technology Programmable g Logic g Device (PLD) IC Technology
2009 Spring CS211 Digital Systems & Lab

MOS Transistor
5

S Source, Drain D i

Diffusion area where electrons can flow Can be connected to metal contacts (vias) Polysilicon area where control voltage is applied Si O2 Insulator so the gate voltage cant leak

Gate

Oxide

IC package

IC

2009 Spring CS211 Digital Systems & Lab

NMOS Transistor fabrication process(1) (1)

6

NMOS Transistor(NMOS FET)

SiO2 Silicon dioxide(0.6 micron) is grown all over the surface P type t silicon ili

Ultra-violet light Mask Photo-resist material SiO2 Photolithography

P type silicon SiO2 Silicon dioxide()(about 0.6 micron) P type silicon

2009 Spring CS211 Digital Systems & Lab

NMOS Transistor fabrication process(2) ( )

7 gate oxide(about 0.05 micron) is grown

Polysilicon is deposited (Low Pressure Chemical Vapor Deposition)

Diffuse AS (n type) n+ n+

Source, drain structures are formed

2009 Spring CS211 Digital Systems & Lab

NMOS Transistor fabrication process(3) (3)

8 SiO2 is grown n+ n+

deposit metal(aluminium) to make contact points n+ n+

Length unit --- ( (micron) ) 2

2009 Spring CS211 Digital Systems & Lab

Four views
9

Logic

Transistor

Layout

Physical

2009 Spring CS211 Digital Systems & Lab

NAND
10

Metal layers for routing (~10) PMOS dont like 0 NMOS dont like 1 A stick diagram form the basis for mask sets (layout)

2009 Spring CS211 Digital Systems & Lab

IC manufacturing steps
11

Structural St t ld design i from f functional f ti ld descriptions i ti t to th the optimized ti i d circuits at gate level Layout design from the gate level descriptions to the physical layout Tape out

Send design to manufacturing Drawing patterns by using photo-resist to form barriers for deposition

Photolithography g p y

Tape-out

2009 Spring CS211 Digital Systems & Lab

Full Custom
12

Very Large V L Scale S l Integration I t ti (VLSI) Placement

Place and o orient ient t transistors ansisto s Connect transistors Make fat, fast wires or thin, slow wires May y also need to size buffer

Routing

Si i Sizing

Design Rules

simple i l rules l f for correct circuit i i f function i Metal/metal spacing, min poly width

2009 Spring CS211 Digital Systems & Lab

Full Custom
13

Best B t size, i power, performance f Hand design

Horrible time-to-market/flexibility/NRE / y/ cost Reserve for the most important units in a processor ALU, Instruction fetch Less optimal, but faster
Vdd

Physical design tools

2009 Spring CS211 Digital Systems & Lab

Semi Custom Semi-Custom

14

Gate Array

Array of prefabricated gates place and route Higher density, faster time-to-market Does not integrate as well with full-custom

Standard Cell

A library of pre-designed pre designed cell Place and route Lower density, higher complexity Integrate great with full-custom

2009 Spring CS211 Digital Systems & Lab

A Sea Sea-of-gates of gates gate array

15
f1

x1

x2

x3

The logic function f1 = x2x3+x1x3 in the gate array

2009 Spring CS211 Digital Systems & Lab

16

A section of two rows in a standard cell

x1 x2 x3

f2

f1

f1 = x1x2+x1x3+x1x2x3 f2 = x1x2+x1x2x3+x1x3 f
2009 Spring CS211 Digital Systems & Lab

Semi Custom Semi-Custom

17

Most popular design style Jack of all trade

Good

Power, time-to-market, performance, NRE cost, per-unit cost, area

Master of none

Standard-cell integrated with full custom for critical regions of design

2009 Spring CS211 Digital Systems & Lab

What will we learn in this chapter?

18

How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs B i characteristics Basic h t i ti of f electronic l t i circuits i it (partially covered)

2009 Spring CS211 Digital Systems & Lab

Programmable Logic Devices

19

P Programmable bl L Logic i D Device i

Programmable Logic Array, Programmable Array Logic, Field Programmable Gate Array Designers can purchase an IC To implement desired functionality Connections on the IC are either created or destroyed to implement Very low NRE costs Great Time to Market High unit cost, bad for large volume Power Except special PLA Slower
2009 Spring CS211 Digital Systems & Lab

All l layers already l d exist i t

Benefits

Drawbacks

1600 usable gate, 7.5 ns $7 list price

Programmable Logic Devices

20

General purpose chip for implementing logic circuitry

It can be customized in diff different t ways

Inputs

(logic variables)

Logic gates and programmable switches

Outputs

(logic ( g functions) )

2009 Spring CS211 Digital Systems & Lab

Programmable Logic Array (PLA)

21

Pre-fabricated building block of many AND/OR gates

x1 x2

xn

personalized by making or breaking b ki connections ti among the gates Programmable g array y block diagram for sum of products form

Input buffers and inverters x1 x1 xn xn P1 AND plane OR plane Pk

f1 2009 Spring CS211 Digital Systems & Lab

fm

Gate-level Gate level Diagram of a PLA

22

x1

x2

x3 Programmable connections P1 OR plane

P2

P3

P4

Sum of Product terms Product terms

AND plane f1 f2 2009 Spring CS211 Digital Systems & Lab

f1 and f2 ??

Customary schematic
23

x1

x2

x3

OR plane P1 P2 P3 P4

AND plane f1
2009 Spring CS211 Digital Systems & Lab

f2

Programmable Array Logic (PAL)

24

x1

x2

x3

Programmable Fixed Hardwired

f1

P1 P2 P3 P4

f2

AND plane

What is the difference?

2009 Spring CS211 Digital Systems & Lab

Extra circuitry added to OR-gate OR gate

25

Select

Enable f1

Flip-flop D Clock Q

Output pin

Fed back to AND plane

2009 Spring CS211 Digital Systems & Lab

A PLD P programming unit (courtesy of Data ata IO Corp)

26

Figure 3.30. A PLD programming unit (courtesy of Data IO Corp).

2009 Spring CS211 Digital Systems & Lab

A PLCC package with socket

27

r boa t i cu cir d nte P ri

2009 Spring CS211 Digital Systems & Lab

Structure of a complex programmable logic device (CPLD) ( )

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I/O block k

I/O blo ock

PAL-like block

PAL-like block

Interconnection wires
I/O O block

I/O b block

PAL-like block

PAL-like block

Figure 3 3.32. 32 Structure of a complex programmable logic device (CPLD) (CPLD).

2009 Spring CS211 Digital Systems & Lab

A section of the CPLD

29
PAL-like block (details not shown)

Programmable switches

PAL-like block

macrocell
D Q

D Q

D Q

2009 Spring CS211 Digital Systems & Lab

30

CPLD packaging and programming

(a) CPLD in a Quad Flat Pack (QFP) package

To computer

Printed circuit board

(b) JTAG programming

2009 Spring CS211 Digital Systems & Lab

Field-Programmable Gate Arrays ( (FPGAs) )

31

FPGAs are programmable FPGA bl d devices i th that t support t relatively large circuits

Macrocell of PLDs : 20 gates

PAL : 8 macrocell (160 gates) CPLD : 500 macrocell (10,000 gates) Over 2.5 2 5 billion TRs, TRs 8 8.1 1 M ASIC gate equivalent

Altera 40nm Stratix IV in 2008

Different from CPLDs since they do not contain AND and OR planes Provide logic blocks for implementing the logic functions

Three main types of resources

Logic g blocks I/O blocks Interconnection wires

2009 Spring CS211 Digital Systems & Lab

Structure of an FPGA
32

2009 Spring CS211 Digital Systems & Lab

Logic Blocks
33

Each block has a small number of inputs and one output Usually use lookup tables (LUT)

Contains storage cells used to implement a small logic function Each storage cell can hold a 0 or a 1 Stored value is produced as the output of the storage cell

2009 Spring CS211 Digital Systems & Lab

A two two-input input lookup table

34
x1 0/1 0/1 0/1 0/1 x2
(a) Circuit for a two-input LUT

x1 x2 0 0 1 1 0 1 0 1

f1 1 0 0 1

(b) f 1 = x 1 x 2 + x 1 x 2

x1 1 0 0 1 x2
(c) Storage cell contents in the LUT

If x1=0 0

f1

If x2=1

2009 Spring CS211 Digital Systems & Lab

A three three-input input LUT

35

x1 x2 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 x3

2009 Spring CS211 Digital Systems & Lab

Inclusion of a flip-flop in an FPGA logic bl k block

36

Select

Out In1 In2 In3 Clock LUT Flip-flop D Q

2009 Spring CS211 Digital Systems & Lab

37

A section of a programmed FPGA

x3 f

f=x1x2+x2x3
x1 x1 0 0 f 0 1 x2 1 x2 0 1 f 0 2 x3 0

x2

f1 0 1 1 f2 1

2009 Spring CS211 Digital Systems & Lab

What will we learn in this chapter?

38

How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs B i characteristics Basic h t i ti of f electronic l t i circuits i it (partially covered)

2009 Spring CS211 Digital Systems & Lab

NMOS transistor when turned off

39

VG = 0 V SiO 2

VS = 0 V ++++++ ++++ ++++++ ++++++ ++++++ +++ ++++++ ++++++ ++++++ ++++++ ++++++ +++++++++++ ++++++ +++++++++++ +++++++++ Substrate (type p) +++++++++

VD

Source (type n)

Drain (type n)

When

VGS

= 0 V, the transistor is off

2009 Spring CS211 Digital Systems & Lab

NMOS transistor when turned on

40

V DD VG = 5V
VT 0.2VDD

VGS>VT

SiO2

ID VGS V Triode
T

Saturation VGS=5V 5V VGS=3V

VS = 0V ++++++++++ +++ ++++++ ++++++ ++++++ +++++++++++ +++++++++++++++++ +++++++++ ++++++++++ +++++++++

VD = 0 0V V

Channel (type n) , the e transistor a s s o is so on (b) When VGS = 5 V,

VDS

2009 Spring CS211 Digital Systems & Lab

Dynamic Operation of Logic Gates

41

Parasitic capacitance in integrated circuits

N x
(a) A NOT gate driving another NOT gate
1

N A

V DD

parasitic or p stray capacitance

VA

V DD

Vx
C

Vf

(b) The capacitive load at node A

2009 Spring CS211 Digital Systems & Lab

Voltage waveforms for logic gates

42

VDD Vx Gnd Propagation delay tPLH VDD 90% VA Gnd 50% 10% tr
2009 Spring CS211 Digital Systems & Lab

50%

50% Propagation delay tPHL

90% 50% 10% tf

Power Dissipation
0

Ec = i (t )V f dt = C
0

dV f dt

2 V f dt = C V f dV f = 1 2 CVDD 0

VDD

43

Energy dissipated in NMOS and PMOS

E = CVDD2

Power : Energy/unit time

P = fCVDD2
ID

VDD E =CVDD2/2
Vx ID Vf

E =CV CVDD2/2
Vf

Vx

E =CVDD2/2

(a) Current flow when input Vx changes from 0 V to 5 V

2009 Spring CS211 Digital Systems & Lab

(b) Current flow when input Vx changes from 5 V to 0V

Fan-in Fan in and Fan-out Fan out Problems

44

Fan-in problem

k input gate : k NMOS or k PMOS transistors in series

propagation delays Increasing VOL decreasing VOH : reducing noise margin

Fan-out problem

n gates t are connected t dt to an output t t

V f for f n =1

Cn = n x C
Vf Cn To inputs of n other inverters

VDD V f for f n=4 Gnd 0 Time

(c) Propagation times for different values of n 2009 Spring CS211 Digital Systems & Lab

Buffers
45

To improve performance

to drive a large capacitive load

Non-inverting buffer Inverting buffer

Vx

V DD

Vf

+ + L L
(a) Small transistor (b) Larger transistor

W1

W2

(a) Implementation of a buffer

x
(b) Graphical symbol

2009 Spring CS211 Digital Systems & Lab