CS221:DigitalDesign

FiniteStateMachine:Controller

Dr.A.Sahu DeptofComp.Sc.&Engg. IndianInstituteofTechnologyGuwahati

Out e Outline
FiniteStateMachine
Definition ExampleofFSM Convertafinitestatemachinetoa C t ll asequential Controller ti lcircuit i ithaving h i

AregisterandCombinationallogic FSMcontroller:Examples,Counter FSMController C t ll using i Others Oth FFs FF

FSMDefinition
Set S tof fstates t t
Ex:{Off,On1,On2,On3}

S Set tof finputs i t & setofoutputs

Ex:Inputs:{x},Outputs:{b}

Inputs: b; Outputs: x x=0 Off b x=1 On1 x=1 On2 x=1 On3 b

Initialstate
Ex:Off

Setoftransitions
ib next tstates, t t E iti D Describes Ex:H Has5t transitions

Setofactions
Sets S t outputs t t while hil in i states t t Ex:x=0,x=1,x=1,andx=1

We often draw FSM graphically, known as state diagram

Can also use table (state table), or textual languages

 Only onecondition should h ld be b true

CommonPitfallsRegardingTransition Properties a
Foralltransitionsleaving astate Ifnot,whichone?
b ab=11 next state?
a

One conditionmust be true

Foralltransitionsleaving astate Ifnot, t where h go?

ab
ab

ab what if ab=00?

a ab

VerifyingCorrectTransitionProperties
CanverifyusingBooleanalgebra
a ab b

Onlyoneconditiontrue:ANDofeachconditionpair(for transitionsleavingastate)shouldequal0 provespaircan neversimultaneouslybetrue

a

a * ab = (a * a) * b = 0 * b = 0

OK!

Oneconditiontrue:ORofallconditionsoftransitionsleaving astate) )should h ldequal l1 provesatleast l onecondition di i must betrue a + ab = a*(1+b) + ab = a + ab + ab = a + (a+a) b = a + b Fails! Might not be 1 (i.e., a=0, b=0)
Q: For shown transitions, transitions prove whether: * Only one condition true (AND of each pair is always 0) * One condition true (OR of all transitions is always 1)

EvidencethatPitfallisCommon
Wait u=0 s Start u=0 ar Red1 u=0 ab a Blue u=0 ag a Green u=0 ar a Red2 u=1 s s ar ab a ab ag ag ar a Inputs: s,r,g,b,a; Outputs: u
a

ar *a=0ok a*a(r+b+g)=0 ok

ar * a(r+b+g)
= (a*a)*(r+b+g) = 0*(r+b+g) = (a a) r (r +b+g) = a r (r +b+g) (a*a)*r*(r+b+g) a*r*(r+b+g) = arr+arb+arg = 0 + arb+arg = arb + arg = ar(b+g)

Fails! Means that two of Starts transitions could be true Intuitively: press red and blue buttons at same time: conditions ar, and a(r+b+g) will both be true. Which one should be taken? Q: How to solve?
a

ANS: ar should be arbg (likewise for ab, ag, ar)

InitialStateofaController
AllourFSMshadinitial state
Butoursequentialcircuit designs g didnot Canaccomplishusingflip flopswithreset/setinputs
Showncircuitinitializesflipflops to01
Inputs: x; Outputs: b x=0 Off b x=1 On1 b Combinational logic s1 State register D R Q Q s0 b x=1 On2 x=1 On3 x n1 n0 clk

Designer g mustensure resetinputis1during powerupofcircuit

Byelectroniccircuitdesign

D S

Q Q

reset

ControllerExample:ButtonPressSynchronizer
EnglishLanguageSpecification Wewantsimplesequentialcircuit
Convertsbuttonpresstosinglecycleduration Regardlessoflengthoftimethatbuttonactually pressed
clk Inputs: bi cycle1 cycle2 cycle3 cycle4

bi

Button press synchronizer controller

bo

Outputs: bo

FSMController:ButtonPressSynchronizer

St I Step
FSM inputs: bi; FSM outputs: bo bi b i A bo=0
IamOff WhenB=0

bi

B bo=1

bi

C bo=0

bi bi

IamOff EvenifB=1

Step 1: Design FSM

FSMController:ButtonPressSynchronizer

StepII
bi Combinational logic s1 s0 St t register State i t bo n1 n0 FS SM outp puts FS SM inpu uts clk

Step 2: Create architecture

FSMController:ButtonPressSynchronizer

StepIII
FSM Inputs: bi; Outputs: bo bi bi 00 bo=0 bi 01 bo=1 bi 10 bo=0

bi bi

Step 3: Encode states

FSMController:ButtonPressSynchronizer

StepIV
FSM Inputs: bi; FSM Outputs: bo bi bi 00 bo=0 bi 01 bo=1 bi 10 bo=0 bi bi

Inputs Outputs s1 s0 bi n1 n0 bo
a

Step 4: Create State table

0 0 B 0 0 C 1 1 U 1 n 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 0 0

0 1 0 0 0 0 0 0

0 0 1 1 0 0 0 0

FSMController:ButtonPressSynchronizer

StepIV
Inputs s1 A B C 0 0 0 0 1 1 Un 1 1 s0 0 0 1 1 0 0 1 1 bi 0 1 0 1 0 1 0 1 n1 0 0 0 1 0 1 0 0 Outputs n0 0 1 0 0 0 0 0 0 bo 0 0 1 1 0 0 0 0 clk s1 s0 State register n0 bi n1

n1 = s1s0bi + s1s0bi n0 = s1 s1s0bi s0 bi bo = s1s0bi + s1s0bi = s1s0

Combinational logic bo

Step 5: Create combinational circuit

FSMControllerExample:Sequence Generator
EnglishLanguageSpecification Wantgeneratesequence0001,0011,1100, 1000 (repeat) 1000,
Eachvalueforoneclockcycle Common,e.g.,tocreatepatternin4lights,or controlmagnetsofasteppermotor

FSMControllerExample:Sequence Generator
Inputs: none; Outputs: w,x,y,z wxyz=0001 wxyz=1000
Combinational logic

0001

1000
clk

w x y z

State register g

0111
wxyz=0011

1100
wxyz=1100

Encoded FSM: Bad Way, 4 input, 4 output

FSMControllerExample:Sequence Generator
Inputs: none; Outputs: w,x,y,z wxyz=0001 A wxyz=1000 D

B wxyz=0011

C wxyz=1100

Step 1: Create FSM

FSMControllerExample:Sequence Generator
Combinational logic n1 n0 s1 clk s0 State register w x y z

Step 2: Create architecture

FSMControllerExample:Sequence Generator
Inputs: p none; ; Outputs: p w,x,y,z , ,y,
wxyz=0001 A wxyz=1000 D

00 01
B wxyz=0011 C wxyz=1100

11 10

Step 3: Encode states

FSMControllerExample:Sequence Generator
Inputs
Inputs: none; Outputs: w,x,y,z
wxyz=0001 wxyz 0001 A wxyz=1000 wxyz 1000

Outputs y 0 1 0 0 z 1 1 0 0 n0 n1 0 1 1 0 1 0 1 0

s1 s0 w x 0 1 0 1 0 0 1 1 0 0 1 0

00
B

01

wxyz=0011

A 0 11 B 0 C 1 10 C B 1 wxyz=1100
D

Step 4: Create state table

FSMControllerExample:Sequence Generator w = s1
I Inputs t s1 s0 w x A 0 B 0 C 1 B 1 0 1 0 1 0 0 1 1 0 0 1 0 O t t Outputs y 0 1 0 0 z 1 1 0 0 n0 n1 0 1 1 0 1 0 1 0
s1 s0 State register x = s1s0 y = s1s0 s1 s0 z = s1 n1 = s1 xor s0 n0 = s0 s0 w x y z

n0 n1

Step St 5: 5 Create combinational circuit

clk

FSMofCounter:2bit
b =Outputb Statebits bits
A 00 B 01 C 10 D 11

Combinational logic s1 s0 State register

n1 n0

s1 s 0 A
B C
B

I/P / s1 0 0 1 1 s0 0 1 0 1 0 1 1 0

O/P / n0 n1 1 0 1 0

clk

FSMController:BinaryCounter
A 00 B 01 C 10 D 11

n1 = s1 xor s0 n0 = s0

I/P s1 A B C
B

O/P n0 n1 0 1 1 0 1 0 1 0

s1 s0

s0 0 1 0 1

0 0 1 1

s1 clk

s0 State register

n0

n1

UsingotherFFinCounter
TakesbenefitofdualinputstoFF CountercanbeimplementedusingSmall CombinationalCircuit MoreInputsfromCombinationalCircuit UseofExcitationTable
HowFFoutchangesfromonetoothers RequiredFFinputstochangeFFoutput 0to0,0to1,1to0and1to1

Thanks