Module Name: Digital Logic Laboratory Module Code: ELCE231

Laboratory Experiment No. 2

Experiment Title:
Aim:

Parity Generation and Error Detection

The aim of this experiment is to familiarise students with combinational circuits by studying methods of parity generation and detection.

Objectives:

On completion of this experiment the student should be able to: 1- Make the truth tables for parity detector and generator. 2- Use Karnaugh Maps to simplify Boolean function for parity detectors and generators. 3- Simulate the functions of parity Generator and Detector. 4- Construct circuits that perform parity generation and detection. 5- Test the circuits constructed and verify their operation. 6- Use ICs data books and select the appropriate ICs to implement the design.

Risk Assessment:
ELCE231-labscript-2.doc

Low
Page 1 of 8 Dr. J. Jeedella & Dr. M. Al-Qutayri

1. Introduction
Parity bits are extra signals which are added to a data-word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the data-word contains an odd number of ones. If the data-word contains an even number of ones then the output of the parity generator will be logic 0. Example: For the following group of digits 0111 the parity bit would be a 1; For 0101, the parity bit would be a 0. By concatenating the Parity bit to the data-word, a word will be formed which always has an even number of ones i.e. has even parity. Parity is used on communication channels (e.g. Modem lines) and is often included in memory systems. If a data-word is sent out with even parity, but has odd parity when it is received then the data has been corrupted and must be resent. As its name implies the operation of an Odd Parity generator is similar but it provides odd parity. 1.1 Equipment and Components used 1. NI ELVIS II board 2. PC loaded with Multisim 11.0 3. 74LS86 2 input XOR Gate IC 4. 74LS04 Hex Inverter or NOT gate IC

1.2 Pre-lab and Background Information

It is expected from you before coming to the lab, to read the pre-lab section and to answer all of the mentioned questions and to execute the required tasks. You have to write the answers in the electronic version of your initial lab report. At the start of the lab, you have to submit a hardcopy of the initial lab report containing your design diagram, Multisim schematics etc. Also you have to bring the electronic versions of your design diagrams and Multisim schematics in a USB key for reference and use during the lab session. This pre-lab work you submit will be graded as a part of this laboratory assignment. Incorrect or incomplete designs and Multisim simulation files will not receive full credit for pre-lab work.

1.3 Pre-Lab Reading and Tasks:

1. Read the Lab Introduction Manual 2. Read the NI ELIVS II Orientation Manual and Data sheets of ICs involved in the experiments in appendix A in the Lab Introduction Manual. 3. Design and simulate the circuit for Task 1. Try to design the circuit with minimum number of gates. Draw the logic diagram using gate symbols, refer to the data sheet and label the input/outputs with IC pin numbers. You have to show the design steps

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clearly in the pre-lab report. Bring the simulation files and your simulation results with you to the lab. 4. Repeat step 3 for Task 2.

2. TASK-1: Parity Generation

In this task of the lab, you will design and build a circuit to generate odd parity for three-bit words. Our parity generator circuit will take three input bits (x, y, and z) and produce one output bit (P). The truth table for this parity generator is shown in Figure 1 below:

X
0 0 0 0 1 1 1 1

Y
0 0 1 1 0 0 1 1

Z
0 1 0 1 0 1 0 1

P
1 0 0 1 0 1 1 0

Figure 1 Parity generator truth table. Use the K- Map to produce a MSOP representation of this function by grouping the 1's of the function.
x xy z

00 0
0

01
2

11
6

10
4

1
1 3 7 5

P=

Figure 2 K-map for the parity generator. How many two input AND gates and OR gates, and inverters would be required to implement the equation for P? (Note that it takes two 2-input gates to make one 3- input gate) ANDs ------------------ORs ----------------------NOTs -------------------------

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You can implement this circuit with the chips available in your lab kit, however you will suffer during the wiring of this circuit! You may ask yourself this question: is it possible to simplify this function in order to simplify the logic circuit? This can be done by an engineer and it cannot be done by a computer program. When using K-map, it guarantees for us MSOP form, however the generated form is not the simplest form for this problem. Also the MPOS form that can be derived by grouping the zeroes is not simple. (Try it and see.) It can be seen from the K-map that it exhibits a checkerboard pattern (every other square). When we have this pattern, we can implement the function in either an XOR or XNOR operation. Using Boolean algebra, the function obtained for P can be simplified as follows:

P = ( xy + xy ) z + ( xy + xy) z P = ( x y ) z + ( x y ) z
If we let A= x y then, we have

P = Az + Az = ( A z ) = ( x y z )
Thus, the parity (P) can be implemented using three-variable XNOR gate. Since you don't have a three input XNOR gate in your lab kits, you can easily build one from two XOR gates (7486) and single inverter as shown in Figure 3. (Recall that XOR is associative operation, like AND or OR, so that ( x y) z = x y z)
Z Y X 7486N U3A U4B 7486N U7A 7404N P

Figure 3 Parity Generator using XOR gates and an inverter. 1. Use Multisim to create a subcircuit of your parity generator circuit as shown in Figure 4. Verify its operation by the use of the Digital Writer and Reader in Multisim. 2. Wire up the circuit on NI ELVIS II prototyping board and verify its function by the use of the Digital Writer and Reader. Note that you have to keep the circuit as it is since it is required to test the parity detector that you are going to implement in the next task.

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Figure 4 Schematic for Parity Generation.

3. TASK 2: Parity Detector

After you have implemented Parity generator in Task 1, you will implement a Parity Detector circuit. This circuit will have four inputs: the three information bits, x, y, and z and the newly created parity bit, P. The output of this circuit is one output bit, the error E, which will be asserted a value of 1 whenever there is a parity error. Fill in the value for E in the truth table for this circuit below. Remember, E will be 1 whenever P is not the correct odd parity bit for the values of x, y, and z: x 0 0 0 0 0 0 0 0 y 0 0 0 0 1 1 1 1 z 0 0 1 1 0 0 1 1 P 0 1 0 1 0 1 0 1 E x 1 1 1 1 1 1 1 1 y 0 0 0 0 1 1 1 1 z 0 0 1 1 0 0 1 1 P 0 1 0 1 0 1 0 1 E

Figure 5 Parity detector truth table

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Now, find an MSOP equation for E using the Karnaugh map below:
x xy zP

00
0

01
4

11
12

10
8

00 01
1 5 13 9

11
z
3 7 15 11

10
2 6 14 10

E=

Figure 6 K-map for parity detector. As you will notice after filling the values of E in the K-map, you cannot form any group on the map. Accordingly, the equation for E will be difficult to wire up using AND gates, OR gates and inverters. Once again, you will notice the familiar checkerboard pattern. The E is true when there is an even number of 1s in the four input variables (x,y,z,P). The same as P in Figure 1which was 1 whenever there was an even number of 1 's in the input (x,y,z) for our generator circuit. This function can be implemented, once more using an XNOR with four input variables,

E=

( x y z P)

'

Thus, the XNOR is sometimes referred to as the even function and XOR is also sometimes referred to as odd function. In case that our truth table was modified such that our output is true whenever there is an odd number of 1s, the resulting function will be an XOR, and the Kmap will have the checkerboard pattern. However, the first 1 will be in cell 0001 instead of 0000. 1. Connect the circuit for the parity detection logic function E above as a subcircuit in MultiSim with four inputs and 1 output and verify its function. To test your circuits, create a new schematic and embed your generator and detector subcircuits as shown in Figure 7. 2. Wire up your circuit on your breadboard. This will require three more XOR gates and one more inverter. You should have two 7486 chips in your lab kit. Connect your parity generator to your parity detector and verify that it works correctly. Show the results to your instructor

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3. How could you change the circuit that you built above to simulate a communication system where a single bit error may be introduced to one of the four inputs to the parity detector?

Figure 7 Parity generator and detector.

4. Assignments Questions:
123How could the circuit in Figure 3 be modified to create an Even Parity generator? How could the odd parity detector that you used in Task 2 be modified to create an Even Parity detector? Could the even-parity detector detect the error in the transmission of following sequence? Why or why not? Transmitted data: 0101 0011 Received data: 0100 001

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Digital Logic Laboratory (ELCE231)

Laboratory Experiment No.2 MARKING SHEET
(Include this as the cover sheet for your report)
Student Names and ID Nos: .. .. .. Laboratory Section: Experiment Date:

Please note that your work for this laboratory experiment will be assessed according to the marking scheme below. Please take this into account when conducting the experiment and writing the report.

No.
1

Criteria
Pre-lab

Description
A mark will be allocated to each student that reflects his preparations for the lab. A mark will be allocated to each student individually that reflects his performance in the lab Documentation and analysis of the results for each task performed in the lab Conclusions for each task performed in the lab Answers to assignment questions Overall presentation of the report including proper layout and clarity of figures, tables, and graphs. Correct use of English language.

Weight %
20

Mark

Comments

Performance in the lab

20

Results and Analysis Summary/ Conclusions Assignment Questions Report Presentation

30

4 5 6

10 10 10

Total

100

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Dr. J. Jeedella & Dr. M. Al-Qutayri