EXP NO: 01 Date: 25.09.

12 MODELING AND SIMULATION OF FLIPFLOPS (JK, SR, D, T) USING VERILOG HDL

AIM To model the following sequential circuits using Verilog HDL and to check the functionality of the circuit using XILINX ISE. a. JK flip flop b. SR flip flop c. D flip flop d. T flip flop (a) JK FLIP-FLOP The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. TRUTH TABLE CLK J 0 0 1 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t)

BLOCK DIAGRAM

PROGRAM module jk_ff (q,j,k,clk,res); inputj,k,clk,res; output q; reg q; always@(negedge clk) begin if (res) q=1'b0; else if (j==1'b0 && k==1'b1) q=1'b0; else if(j==1'b1&&k==1'b0) q=1'b1; else if(j==1'b1&&k==1'b1) q=~q; else q=q; end endmodule TEST BENCH module jk; // Inputs reg j; reg k; reg clk; reg res; // Outputs wire q; // Instantiate the Unit Under Test (UUT) jk_ffuut ( .q(q), .j(j), .k(k), .clk(clk), .res(res)

); initial begin // Initialize Inputs j = 0; k = 0; clk = 1; res = 1;#50; res=0; // Add stimulus here j=0;k=0;#100; j=0;k=1;#100; j=1;k=0;#100; j=1;k=1;#100; end always #50 clk=~clk; endmodule SIMULATION RESULT

(b) SR FLIP-FLOP While the S and R inputs are both low, feedback maintains the Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low TRUTH TABLE CLK S 0 0 1 BLOCK DIAGRAM R 0 1 0 Q(t+1) Q(t) 0 1

PROGRAM module ffsr(q,s,r,clk,res); input s,r,clk,res; output q; reg q; always@(negedge clk) begin if (res) q=1'b0; else if(s==0 && r==0)q=q; else if(s==0 && r==1)q=0; else if (s==1 && r==0)q=1; else q=1'bz; end endmodule TEST BENCH module srff; // Inputs reg s; reg r; reg clk; reg res; // Outputs wire q; // Instantiate the Unit Under Test (UUT)

ffsruut ( .q(q), .s(s), .r(r), .clk(clk), .res(res) ); initial begin // Initialize Inputs s = 0; r = 0; clk = 1; res = 1;#50; res=0; // Add stimulus here s=0;r=0;#100; s=0;r=1;#100; s=1;r=0;#100; s=1;r=1;#100; end always #50 clk=~clk; endmodule SIMULATON RESULT

(c) D FLIP-FLOP The D ip-op is the most common flip-flop better known as data or delay flip-flop .The Q output takes on the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low).It is called the D flip-flop for this reason, since the output takes the value of the D input or data input, and delays it by one clock cycle.

TRUTH TABLE

CLK D 1 0

Q(t+1) 1 0

BLOCK DIAGRAM

PROGRAM module dff1 (q,d,clk,res); output q; input d,clk,res; reg q; always@(posedge res or negedge clk) if (res) q<=1'b0; else q<=d; endmodule TEST BENCH module dff1; // Inputs reg d; reg clk; reg res;

// Outputs wire q; // Instantiate the Unit Under Test (UUT) dff1uut ( .q(q), .d(d), .clk(clk), .res(res) ); initial begin // Initialize Inputs d = 0; clk = 1; res = 1;#100; res=0; // Add stimulus here d=0;#100; d=1;#100; d=0;#100; d=1;#100; end always #50 clk=~clk; endmodule SIMULATION RESULT

(d) T FLIP-FLOP If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobe. If the T input is low, the flip-flop holds the previous value.

TRUTH TABLE

CLK T

Q(t+1)

1 0

Q(t) Q(t)

BLOCK DIAGRAM

PROGRAM module tff1 (q,qb,t,clk,rst); output q, qb; input t,clk,rst; reg q, qb; always@(posedge rst or negedge clk) if (rst==1) q<=t^q; end endmodule TEST BENCH module tff1; // Inputs reg t; reg clk; reg rst; // Outputs wire q;

wire qb; // Instantiate the Unit Under Test (UUT) dver1uut ( .q(q), .qb(qb), .t(t), .clk(clk), .rst(rst) ); initial begin // Initialize Inputs t = 0; clk = 1; rst = 0;#100; rst=1; // Add stimulus here t=0;#100; t=1;#100; t=0;#100; t=1;#100; end always #50 clk=~clk; endmodule SIMULATION RESULT

RESULT: Thus the above Flip flops are implemented using VERILOG HDL and the functionality is verified using XILINX ISE.