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ECEN 248 –Introduction to Digital Systems Design (Spring 2008)

248 –Introduction to Digital Systems Design (Spring 2008) (Sections: 501, 502, 503, 507) Prof. Xi Zhang
248 –Introduction to Digital Systems Design (Spring 2008) (Sections: 501, 502, 503, 507) Prof. Xi Zhang

(Sections: 501, 502, 503, 507)

Prof. Xi Zhang ECE Dept, TAMU, 333N WERC

http://www.ece.tamu.edu/~xizhang/ECEN248

Programmable logic device (PLD)

Programmable logic device (PLD) A PLD is a general-purpose chip for implementing logic circuit. It contains
Programmable logic device (PLD) A PLD is a general-purpose chip for implementing logic circuit. It contains

A PLD is a general-purpose chip for implementing logic circuit. It contains a collection of logic circuit elements that can be customized in different ways. A PLD can be viewed as a “black box” that contains logic gates and programmable switches. The programmable switches allow the logic gates inside the PLD to be connected together to implement logic circuits.

Programmable logic device as a black box

Programmable logic device as a black box Inputs (logic variables) Logic gates and programmable switches Outputs
Programmable logic device as a black box Inputs (logic variables) Logic gates and programmable switches Outputs

Inputs

(logic variables)

Logic gates and programmable switches
Logic gates
and
programmable
switches
(logic variables) Logic gates and programmable switches Outputs (logic functions) Figure 3.24. Programmable logic
(logic variables) Logic gates and programmable switches Outputs (logic functions) Figure 3.24. Programmable logic
(logic variables) Logic gates and programmable switches Outputs (logic functions) Figure 3.24. Programmable logic

Outputs

(logic functions)

Programmable logic devices

Programmable logic devices Different types of PLD Simple PLD (SPLD) Programmable logic array (PLA) Programmable array
Programmable logic devices Different types of PLD Simple PLD (SPLD) Programmable logic array (PLA) Programmable array

Different types of PLD

Simple PLD (SPLD)

Programmable logic array (PLA) Programmable array logic (PAL)

Complex PLD (CPLD) Field-programmable gate arrays (FPGA)

Programmable logic array (PLA)

Programmable logic array (PLA) PLA is developed based on the sum-of-product form. A PLA includes a
Programmable logic array (PLA) PLA is developed based on the sum-of-product form. A PLA includes a

PLA is developed based on

the sum-of-product form. A PLA includes a circuit

block called an AND plane (or AND array) and a circuit block called an OR plane (or OR array). Input Buffer/inverters And plane OR plane Output

x 1 x 2

x n

And plane OR plane Output x 1 x 2 x n Input buffers and inverters x

Input buffers and inverters

Output x 1 x 2 x n Input buffers and inverters x n x n x

x n x n

1 x 2 x n Input buffers and inverters x n x n x 1 x
1 x 2 x n Input buffers and inverters x n x n x 1 x
1 x 2 x n Input buffers and inverters x n x n x 1 x

x 1 x 1

x n Input buffers and inverters x n x n x 1 x 1   P
x n Input buffers and inverters x n x n x 1 x 1   P
x n Input buffers and inverters x n x n x 1 x 1   P
 

P

1

  P 1  
 
  P 1   AND plane OR plane P k

AND plane

AND plane OR plane

OR plane

P

k

P k
P k
n x 1 x 1   P 1   AND plane OR plane P k f

f 1

f

m

Gate-level diagram of a PLA

Gate-level diagram of a PLA x 1 x 2 x 3 Output of And plane: Programmable
Gate-level diagram of a PLA x 1 x 2 x 3 Output of And plane: Programmable
x 1 x 2 x 3 Output of And plane: Programmable connections P 1 =
x 1
x 2
x 3
Output of And plane:
Programmable
connections
P 1 = x x
1
2
OR plane
P
1
P
= x x
2
1
3
P
P
2
3
3
P
= x x x
= x x
1
2
4
1
3
P
3
Output of OR plane:
P
4
f
= x x + x x + x x x
1
1
2
1
3
1
2
3
f
= x x + x x x + x x
AND plane
2
1
2
1
2
3
1
3
f 1
f 2

Customary schematic for the PLA

Customary schematic for the PLA x 1 x 2 x 3 Output of And plane: P
Customary schematic for the PLA x 1 x 2 x 3 Output of And plane: P
x 1 x 2 x 3 Output of And plane: P 1 = x x
x 1
x 2
x 3
Output of And plane:
P 1 = x x
1
2
OR plane
P
P
= x x
1
2
1
3
P
P
2
3
1
2
3
P
= x x x
= x x
P
4
1
3
3
Output of OR plane:
P
4
f
= x x + x x + x x x
1
1
2
1
3
1
2
3
AND plane
f
= x x + x x x + x x
2
1
2
1
2
3
1
3
f 1
f 2

Programmable array logic (PAL) device

Programmable array logic (PAL) device Programmable array logic (PAL) device PAL is a programmable logic device
Programmable array logic (PAL) device Programmable array logic (PAL) device PAL is a programmable logic device

Programmable array logic (PAL) device PAL is a programmable logic device similar to PLA. Difference between PLA and PAL

PLA: both AND plane and OR plane are programmable. PAL: Only AND plane is programmable, while OR plane is fixed.

An example of a PAL

An example of a PAL P 1 = x x x 1 2 3 x 1
An example of a PAL P 1 = x x x 1 2 3 x 1
P 1 = x x x 1 2 3 x 1 x 2 x 3
P 1 = x x x
1
2
3
x 1
x 2
x 3
P
= x x x
2
1
2
3
fixed
Programmable
P
= x x
3
1
2
P
1
P
= x x x
4
1
2
3
f
1
P
f = x x x + x x x
2
1
1
2
3
1
2
3
f
= x x + x x x
2
1
2
1
2
3
P
3
f
2
P
4
OR plane

AND plane

Figure 3.28.

An example of a PLA.

Comparison between PLA and PAL

Comparison between PLA and PAL Comparison between PLA and PAL Drawbacks of PLA PLA were hard
Comparison between PLA and PAL Comparison between PLA and PAL Drawbacks of PLA PLA were hard

Comparison between PLA and PAL

Drawbacks of PLA

PLA were hard to be implemented PLA reduced the speed performance of circuits.

Advantage of PAL

Simple to manufacturers Less expensive Better performance

Disadvantage of PAL

Not flexible as compared PLA, because OR plane is fixed.

Complex Programmable Logic Device (CPLDs)

Complex Programmable Logic Device (CPLDs) SPLDs, including PLA, PAL, and etc, are useful for implementing a
Complex Programmable Logic Device (CPLDs) SPLDs, including PLA, PAL, and etc, are useful for implementing a

SPLDs, including PLA, PAL, and etc, are useful for implementing a wide variety of small digital circuits.

CPLD are used to implement more sophisticated type of chip.

Complex Programmable Logic Device (CPLDs)

Complex Programmable Logic Device (CPLDs) A CPLD comprises multiple circuit blocks on a single chip, with
Complex Programmable Logic Device (CPLDs) A CPLD comprises multiple circuit blocks on a single chip, with

A CPLD comprises multiple circuit blocks on a single chip, with internal wiring resources to connect the circuit blocks. Each circuit block is similar to a PLA or a PAL We will refer to the circuit blocks as PAL-like blocks.

Complex Programmable Logic Device (CPLDs)

Complex Programmable Logic Device (CPLDs) PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O
Complex Programmable Logic Device (CPLDs) PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O
Complex Programmable Logic Device (CPLDs) PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O

PAL-like

block

PAL-like

block

I/O block

I/O block
I/O block
PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like
PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like
PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like
PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like
PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like
PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like
PAL-like block PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like

Interconnection wires

PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like block I/O block
PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like block I/O block
PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like block I/O block
PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like block I/O block
PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like block I/O block
PAL-like block I/O block I/O block Interconnection wires I/O block PAL-like block PAL-like block I/O block

I/O block

PAL-like

block

PAL-like

block

I/O block

wires I/O block PAL-like block PAL-like block I/O block Figure 3.32. Structure of a complex programmable
wires I/O block PAL-like block PAL-like block I/O block Figure 3.32. Structure of a complex programmable
wires I/O block PAL-like block PAL-like block I/O block Figure 3.32. Structure of a complex programmable
wires I/O block PAL-like block PAL-like block I/O block Figure 3.32. Structure of a complex programmable

Field-Programmable Gate Arrays (FPGA)

Field-Programmable Gate Arrays (FPGA) Larger and larger logic circuits need to accommodate in a single chip.
Field-Programmable Gate Arrays (FPGA) Larger and larger logic circuits need to accommodate in a single chip.

Larger and larger logic circuits need to accommodate in a single chip. One way to quantify a circuit’s size is to assume that the circuit is to be built using only simple logic gates and then estimate how many of these gates are needed. A commonly used measure is the total number of two-input NAND gates. This measure is often called the number of equivalent gates. By modern standards, a logic circuit with 10,000 gates is not large.

Field-Programmable Gate Arrays (FPGA)

Field-Programmable Gate Arrays (FPGA) FPGA is a programmable logic device that supports implementation of relatively
Field-Programmable Gate Arrays (FPGA) FPGA is a programmable logic device that supports implementation of relatively

FPGA is a programmable logic device that supports implementation of relatively large logic circuits. Not like CPLD, FPGAs do not contain AND or OR planes. Instead, FPGAs provide logic blocks for connecting to the pins of the package, and interconnection wires and switches.

General structure of an FPGA

General structure of an FPGA The logic blocks are arranged in a two-dimensional array, depicted as
General structure of an FPGA The logic blocks are arranged in a two-dimensional array, depicted as

The logic blocks are arranged

in a two-dimensional array, depicted as hollow black box; The interconnection wires,

depicted as solid blue box, are organized as horizontal and vertical routing channels between rows and columns of logic blocks. Programmable connections

also exist between I/O blocks and the interconnection wires. FPGA can implement circuit of more than a million equivalent gates in size.

Lookup Table (LUT)

Lookup Table (LUT) Lookup table (LUT) is the most commonly used logic block in FPGA. A
Lookup Table (LUT) Lookup table (LUT) is the most commonly used logic block in FPGA. A

Lookup table (LUT) is the most commonly used logic block in FPGA. A lookup table contains storage cells that are used to implement a small logic function. Each cell is capable of holding a single logic value, either 0 or 1. LUTs of various sizes may be created, where the size is defined by the number of inputs. LUTs are implemented by using multiplexers.

Circuits for a two-input lookup table

Circuits for a two-input lookup table 2-to-1 multiplexer x 1 0/1 0/1 0/1 0/1 cells x
Circuits for a two-input lookup table 2-to-1 multiplexer x 1 0/1 0/1 0/1 0/1 cells x

2-to-1 multiplexer

x 1 0/1 0/1 0/1 0/1 cells x 2
x
1
0/1
0/1
0/1
0/1
cells
x
2

f

(a) Circuit for a two-input LUT

Example of a two-input lookup table

Example of a two-input lookup table x 1 x 2 f 1 0 0   1
Example of a two-input lookup table x 1 x 2 f 1 0 0   1

x 1

x 2

f 1

0

0

 

1

0

1

0

1

0

0

1

1

1

 
 
 

=

x

x

+

f 1

1

2

(b)

x 1 x 2

x 1 1 0 0 1 x 2 (c) Storage cell contents in the LUT
x
1
1
0
0
1
x
2
(c) Storage cell contents in the LUT

f 1

A three-input LUT

A three-input LUT x 1 x 2 0/1 0/1 0/1 0/1 f 0/1 0/1 0/1 0/1
A three-input LUT x 1 x 2 0/1 0/1 0/1 0/1 f 0/1 0/1 0/1 0/1
x 1 x 2 0/1 0/1 0/1 0/1 f 0/1 0/1 0/1 0/1 x 3
x
1
x
2
0/1
0/1
0/1
0/1
f
0/1
0/1
0/1
0/1
x
3

Figure 3.37.

A three-input LUT.

x 3

f

x 3 f x 1 x 0 x 0 1 2 0 1 f 1 f
x 3 f x 1 x 0 x 0 1 2 0 1 f 1 f
x 3 f x 1 x 0 x 0 1 2 0 1 f 1 f
x 3 f x 1 x 0 x 0 1 2 0 1 f 1 f
x 3 f x 1 x 0 x 0 1 2 0 1 f 1 f
x 1 x 0 x 0 1 2 0 1 f 1 f 2 0
x
1
x
0
x
0
1
2
0
1
f 1
f 2
0
0
x
x
x
2
2
1
3
0
f
0
1
1
f
1
f
2
1

This section

includes 3 lookup tables. Using the 3 lookup tables, we implement output function

f.

f 1 = x x 1 2 f = x x 2 2 3
f 1 = x x
1
2
f
= x x
2
2
3

f = f + f

1

2