Вы находитесь на странице: 1из 8

VLSI dan Perancangan Logika

Outline
CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops

Lecture 2 CMOS Gate

Mohammad Syafrudin
CMOS Gate
VLSI dan Perancangan Logika

Slide 1

CMOS Gate

VLSI dan Perancangan Logika

Slide 2

Transistor Types
Bipolar transistor Struktur silicon npn atau pnp Arus kecil pada base mengontrol arus yang besar antara emitter dan collector Metal Oxide Semiconductor Field Effect Transistor nMOS dan pMOS MOSFETS Tegangan pada insulated gate mengontrol arus antara source dan drain Low power bisa diperoleh pada very high integration
CMOS Gate
VLSI dan Perancangan Logika

MOS Integrated Circuits


Proses-proses 1970an hanya nMOS transistor Tidak mahal, tapi konsum power ketika idle

Intel 1101 256-bit SRAM


CMOS Gate

Intel 4004 4-bit Proc


Slide 4

1980 -sekarang: Proses-proses CMOS untuk low idle power


Slide 3
VLSI dan Perancangan Logika

CMOS Gate Design


Activity: Sketch a 4-input CMOS NOR gate

CMOS Gate Design


Activity: Sketch a 4-input CMOS NOR gate

A B C D Y

CMOS Gate

VLSI dan Perancangan Logika

Slide 5

CMOS Gate

VLSI dan Perancangan Logika

Slide 6

CMOS Circuit Basics

CMOS Switching Characteristics

CMOS Gate

VLSI dan Perancangan Logika

Slide 7

CMOS Gate

VLSI dan Perancangan Logika

Slide 8

Switch-level Boolean Logic

Switch-level Boolean Logic

CMOS Gate

VLSI dan Perancangan Logika

Slide 9

CMOS Gate

VLSI dan Perancangan Logika

Slide 10

Complementary CMOS
Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network inputs a.k.a. static CMOS
pMOS pull-up network

Series and Parallel


a g1 0 0 b (a) b OFF a 0 0 b (b) b ON 0 1 b OFF a a 0 1 b OFF a 1 0 1 0

a 1 1 b

output
nMOS pull-down network

nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON

g2

b ON a 1 1

OFF a

a g1 g2

b OFF

b OFF

a g1 b (c) g2 0

a 0 b OFF 0

a 1 b ON 1

a 0 b ON 1

a 1 b ON

Pull-up OFF Pull-down OFF Pull-down ON Z 0

Pull-up ON 1 X

a g1 b (d) g2 0

a 0 b ON 0

a 1 b ON 1

a 0 b ON 1

a 1 b OFF

CMOS Gate

VLSI dan Perancangan Logika

Slide 11

CMOS Gate

VLSI dan Perancangan Logika

Slide 12

Conduction Complement
Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Y Requires parallel pMOS
A

Compound Gates
Compound gates can do any inverting function Ex: Y = A B + C D (AND-AND-OR-INVERT, AOI22)
A B (a) C D A B (b) C A (d) D B Y A B (e) C D (f) A B C D Y D B C D

A (c) C A

B C

Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel

CMOS Gate

VLSI dan Perancangan Logika

Slide 13

CMOS Gate

VLSI dan Perancangan Logika

Slide 14

CMOS Logic Function Implementation


Approach to implement a CMOS logic function Create nMOS network Invert output Reduce function, use DeMorgan to eliminate NANDs/NORs Implement using series for AND and parallel for OR Create pMOS network Complement each operation in nMOS network i.e. make parallel into series and visa versa
CMOS Gate
VLSI dan Perancangan Logika

Example: O3AI
Y = ( A + B + C) D

Slide 15

CMOS Gate

VLSI dan Perancangan Logika

Slide 16

Example: O3AI
Y = ( A + B + C) D
A B C D Y D A B C
b) Y . c) Y . d) Y .

Latihan Soal:
Gambarkan skematik level-transistor dari gerbang logika CMOS untuk tiap-tiap fungsi berikut:
a) Y .

= ABC + D
= ( AB + C ) D = AB + C ( A + B ) = ( A + B ) (C + D)

CMOS Gate

VLSI dan Perancangan Logika

Slide 17

CMOS Gate

VLSI dan Perancangan Logika

Slide 18

Signal Strength
Strength of signal How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network

Pass Transistors
Pass Transistors: an nMOS or pMOS is used alone as an imperfect switch.

CMOS Gate

VLSI dan Perancangan Logika

Slide 19

CMOS Gate

VLSI dan Perancangan Logika

Slide 20

Pass Transistors
Transistors can be used as switches
g s d s g=1 s g s s d g=1 s d 1 g=0 d d 1 Input 0 g=0 g=0 g=0 d Input g = 1 Output 0 strong 0 g=1 degraded 1 Output degraded 0 strong 1

Transmission Gates
Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

CMOS Gate

VLSI dan Perancangan Logika

Slide 21

CMOS Gate

VLSI dan Perancangan Logika

Slide 22

Transmission Gates
Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well
Input g a gb g a gb
CMOS Gate

Tristates
Tristate buffer produces Z when not enabled
EN A Y

Output

EN 0 0 1 1

A 0 1 0 1

g = 0, gb = 1 a b b g = 1, gb = 0 a b

g = 1, gb = 0 0 strong 0 g = 1, gb = 0 strong 1 1

EN A Y EN

g b a gb b a

g b gb
VLSI dan Perancangan Logika

Slide 23

CMOS Gate

VLSI dan Perancangan Logika

Slide 24

Tristates
Tristate buffer produces Z when not enabled
EN 0 0 1 1 A 0 1 0 1 Y Z Z 0 1

Nonrestoring Tristate
EN A Y

Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y

EN
EN A EN Y

A EN

CMOS Gate

VLSI dan Perancangan Logika

Slide 25

CMOS Gate

VLSI dan Perancangan Logika

Slide 26

Tristate Inverter
Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output
A EN Y EN EN

Tristate Inverter
Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output
A A EN Y Y Y A

EN = 0 Y = 'Z'
CMOS Gate
VLSI dan Perancangan Logika

EN = 1 Y=A
Slide 28

Slide 27

CMOS Gate

VLSI dan Perancangan Logika

Multiplexers
2:1 multiplexer chooses between two inputs

Multiplexers
2:1 multiplexer chooses between two inputs

S 0 0 1 1

D1 X X 0 1

D0 0 1 X X

S 0 0 1 1

D1 X X 0 1

D0 0 1 X X

Y 0 1 0 1

CMOS Gate

VLSI dan Perancangan Logika

Slide 29

CMOS Gate

VLSI dan Perancangan Logika

Slide 30

Gate-Level Mux Design


Y = SD1 + SD0 (too many transistors)
How many transistors are needed?

Gate-Level Mux Design


Y = SD1 + SD0 (too many transistors)
How many transistors are needed? 20

D1 S D0

D1 S D0
CMOS Gate
VLSI dan Perancangan Logika

4 2 4

2 4 2 2

Slide 31

CMOS Gate

VLSI dan Perancangan Logika

Slide 32

Transmission Gate Mux


Nonrestoring mux uses two transmission gates

Transmission Gate Mux


Nonrestoring mux uses two transmission gates Only 4 transistors

S D0 S D1 S
CMOS Gate
VLSI dan Perancangan Logika

Slide 33

CMOS Gate

VLSI dan Perancangan Logika

Slide 34

Inverting Mux
Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter
D0 S S S D1 Y S S S D1 1 D0 S D1 S Y D0 0 Y S

4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects

CMOS Gate

VLSI dan Perancangan Logika

Slide 35

CMOS Gate

VLSI dan Perancangan Logika

Slide 36

4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes S1S0 S1S0 S1S0 S1S0 Or four tristates
D0 S0 D0 D1 D2 D3 0 D1 1 0 Y 0 1 D3 1 D2 Y S1

D Latch
When CLK = 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch

CLK D Latch Q

CLK D Q

CMOS Gate

VLSI dan Perancangan Logika

Slide 37

CMOS Gate

VLSI dan Perancangan Logika

Slide 38

D Latch Design
Multiplexer chooses D or old Q
D

D Latch Operation
Q Q D Q Q

CLK D 1 0 CLK CLK


CLK

Q Q D

CLK

Q Q

CLK = 1

CLK = 0

CLK

D Q

CMOS Gate

VLSI dan Perancangan Logika

Slide 39

CMOS Gate

VLSI dan Perancangan Logika

Slide 40

D Flip-flop
When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

D Flip-flop Design
Built from master and slave D latches
CLK CLK D CLK Latch QM Latch CLK Q CLK CLK CLK QM CLK CLK CLK Q

CLK

CLK
D

Flop

Q
Q

CMOS Gate

VLSI dan Perancangan Logika

Slide 41

CMOS Gate

VLSI dan Perancangan Logika

Slide 42

D Flip-flop Operation
D QM Q CLK = 0

QM

CLK = 1

CLK D Q
CMOS Gate
VLSI dan Perancangan Logika

Slide 43