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INTRODUCTION:
I/O (Input/Output): It communicates with the outside world. I/O includes two
types of devices: input and output; these I/O devices are
also known as peripherals.
Ø System Bus: The system bus is a communication path between the
microprocessor and peripherals: it is nothing but a group of wires to carry bits
Data Bus:
The data bus is a group of eight lines used for data flow. These lines are
bidirectional —data flow in both directions between the MPU and memory and
peripheral devices. The MPU uses the data bus to perform the second function:
transferring binary information .The eight data lines enable the MPU to manipulate 8-
bit data ranging from 00 to FF (28 = 256 numbers). The largest number that can
appear on the data bus is 11111111.
Control Bus:
The control bus is comprised of various single lines that carry synchronization
signals, providing timing signals. The MPU generates specific control signals for every
operation it performs. These signals are used to identify a device type with which the
MPU intends to communicate.
Registers:
Ø Flags:
The ALU includes five flip-flops that are set or reset according to the result of
an opera tion. The microprocessor uses them to perform the third operation; namely,
testing for data conditions. They are Zero (Z), Carry (CY), Sign (S), Parity (P), and
Auxiliary Carry (AC) flags. The most commonly used flags are Sign, Zero, and Carry;
the others will be explained as necessary.
The bit position for the flags in flag register is,
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
(1) Sign Flag (S): After execution of any arithmetic and logical
operation, if D7 of the result is 1, the sign flag is set. Otherwise it is
reset. D7 is reserved for indicating the sign; the remaining is the
magnitude of number. If D7 is 1, the number will be viewed as
negative number. If D7 is 0, the number will be viewed as positive
number.
(2) Zero Flag (z): If the result of arithmetic and logical operation is
zero, then zero flag is set otherwise it is reset.
(3) Auxiliary Carry Flag (AC): If D3 generates any carry when doing
any arithmetic and logical operation, this flag is set. Otherwise it is
reset.
(4) Parity Flag (P): If the result of arithmetic and logical operation
contains even number of 1’ s then this flag will be set and if it is odd
number of 1’ s it will be reset.
(5) Carry Flag (CY): If any arithmetic and logical operation results
any carry then carry flag is set otherwise it is reset.
Temporary Register: It is used to hold the data during the arithmetic and logical
operations.
Instruction Decoder: It gets the instruction from the instruction register and
decodes the instruction. It identifies the instruction to be performed.
Serial I/O Control: It has to control signals named SID and SOD for serial data
transmission.
Timing and Control unit: It has control and status signals. It provide control signal
to synchronize the components of microprocessor and timing for instruction to
perform the operation.
Interrupt Control Unit: It is used to receive an interrupt signal for process the
operation and send an acknowledgement for receiving the interrupt signal.
I/O INTERFACING:
Thus the I/O devices (Keyboards and displays) can be interfaced using two methods
namely:
• Peripheral-mapped I/O: The device is identified with an 8-bit address and
enabled by I/O – related control signals.
• Memory-mapped I/O: The device is identified with a 16-bit address and
enabled by memory related control signals.
Here, the input and output devices are assigned and identified by 16-bit
addresses. To transfer data between 8085 and I/C devices, memory – related
instructions like LDA, STA etc are used. The control signals MEMR and MEMW
should be connected to I/O devices.
2050 32;
2051 00;
2052 80;
8085 requires 4 Machine cycles to execute STA; Instruction fetch and decode
in M1; read 2051 and 2052 in M2 an M3; In M4 8085 places the entire address
(8000H) on the address lines, the contents of the accumulator on data bus and
generates MEMW
The 8085 instruction set can be classified into the following five functional
headings.
1. DATA TRANSFER INSTRUCTIONS :
Includes the instructions that moves (copies) data between registers or
between memory locations and registers. In all data transfer operations the content
of source register is not altered. Hence the data transfer is copying operation.
2. ARITHMETIC INSTRUCTIONS:
Includes the instructions, which performs the addition, subtraction,
increment or decrement operations. The flag conditions are altered after execution of
an instruction in this group.
3. LOGICAL INSTRUCTIONS:
The instructions which performs the logical operations like AND, OR,
EXCLUSIVE- OR, complement, compare and rotate instructions are grouped under
this heading. The flag conditions are altered after execution of an instruction in this
group.
4. BRANCHING INSTRUCTIONS:
The instructions that are used to transfer the program control from one
memory location to another memory location are grouped under this heading.
Description: The 8-bit data (operand) and the Carry flag are added to the contents
of the accumulator, and the result is stored in the accumulator. All flags are modified
to reflect the result of the addition.
Description: The contents of the operand (register or memory) and the Carry flag
are added to the contents of the accumulator and the result is placed in the
accumulator.
The contents of the operand are not altered; however, the previous Carry flag is
reset.
All flags are modified to reflect the result of the addition.
Description: The contents of the operand (register or memory) are added to the
contents of the accumulator and the result is stored in the accumulator. If the
operand is a memory location, that is indicated by the 16-bit address in the HL
register. All flags are modified to reflect the result of the addition.
Description : The 8-bit data (operand) are added to the contents of the
accumulator, and the result is placed in the accumulator. All flags are modified to
reflect the result of the addition.
Description: The contents of the accumulator are logically AND ed with the
contents of the operand (register or memory), and the result is placed in the
accumulator. If the operand is a memory location, its address is specified by the
contents of HL registers. Flags S, Z, P are modified to reflect the result of the
operation. CY is reset. In 8085 AC is set.
Description: The contents of the operand (register or memory) are compared with
the contents of the accumulator.
Description: The second byte (8-bit data) is compared with the contents of the
accumulator.
Description: The contents of the accumulator are changed from a binary value to
two 4-bit binary-coded decimal (BCD) digits. This is the only instruction that uses the
auxiliary flag (internally) to perform the binary-to-BCD conversion. Flags S, Z, AC, P.
CY flags are altered to reflect the results of the operation.
Description: The 16-bit contents of the specified register pair are added to the
contents of the HL register and the sum is saved in the HL register. The contents of
the source register pair are not altered. If the result is larger than 16 bits the CY
flag is set. No other flags are affected.
Description: The Interrupt Enable flip-flop is reset and all the interrupts except the
TRAP (8085) are disabled. No flags are affected.
Description: The Interrupt Enable flip-flop is set and all interrupts are enabled. No
flags are affected.
Description: The MPU finishes executing the current instruction and halts any
further execution. The MPU enters the Halt Acknowledge machine cycle and Wait
states are inserted in every clock period. The address and the data bus are placed in
the high impedance state. The contents of the registers are unaffected during the
HLT state. An interrupt or reset is necessary to exit from the Halt state. No flags are
affected.
19. IN: Input Data to Accumulator from a Port with 8-bit Address
Description: The contents of the input port designated in the operand are read and
loaded into the accumulator. No flags are affected.
Description: The contents of the specified register pair are incremented by 1. The
instruction views the contents of the two registers as a 16-bit number. No flags are
affected.
Jump Conditionally:
Description:
Jump on carry
Jump on No carry
Jump on Positive
Jump on minus
Jump on Parity Even
Jump on parity Odd
Jump on Zero
Jump on No Zero
Description: The instruction copies the contents of the memory location pointed out
by the 16-bit address in register L and copies the contents of the next memory
location in register H. The contents of source memory locations are not altered. No
flags are affected.
Description: The instruction loads 16-bit data in the register pair designated in the
operand. This is a 3-byte instruction; the second byte specifies the low-order byte
and third byte specifies the high-order byte.
Description: This instruction copies the contents of the source register into the
destination register; the contents of the source register are not altered. If one of the
operand is a memory location, it is specified by the contents of HL registers. No flags
are affected.
Description: The 8-bit data is stored in the destination register or memory. If the
operand is a memory location, it is specified by the contents of HL registers. No flags
are affected.
Description: The contents of the accumulator are logically OR with the contents of
the operand (register or memory), and the results are placed in the accumulator. If
the operand is a memory location, its address is specified by the contents of HL
registers. Flags Z, S, P are modified to reflect the results of the operation. AC and CY
are reset.
31. ORI: Logically OR Immediate
Description: The contents of the accumulator are logically OR with the 8-bit data in
the operand and the results are placed in the accumulator. Flags S, Z, P are modified
to reflect the results of the operation. CY and AC are reset.
32. OUT: Output Data from Accumulator to a Port with 8-Bit Address
Description: The contents of the accumulator are copied into the output port
specified by the operand. Flags No flags are affected.
Description: The contents of registers H and L are copied into the program counter.
The contents of H are placed as a high-order byte and of L as a low-order byte. No
flags are affected.
Description: The contents of the memory location pointed out by the stack pointer
register are copied to the low-order register (such as C, E, L, and flags) of the
operand. The stack pointer is incremented by 1 and the contents of that memory
location are copied to the high-order register (B, D, H, A) of the operand. The stack
pointer register is again incremented by 1. No flags are modified.
Description: The contents of the register pair designated in the operand are copied
into the stack in the following sequence. The stack pointer register is decremented
and the contents of the high-order register (B, D, H, A) are copied into that location.
The stack pointer register is decremented again and the contents of the low-order
register (C, E, L, flags) are copied to that location. No flags are modified.
Description: Each binary bit of the accumulator is rotated left by one position
through the Carry flag. Bit D is placed in the bit in the Carry flag and the Carry flag is
placed in the least significant position D. Flags CY is modified to bit D S, Z, AC, P are
not affected.
Description: Each binary bit of the accumulator is rotated right by one position. Bit
D is placed in the position of D as well as in the Carry flag. Flags CY is modified
according to bit Do. S. Z, P, AC are not affected.
Description: The RST instructions are equivalent to 1-byte call instruction to one of
the eight memory locations on page 0. The instructions are generally used in
conjunction with interrupts and inserted using external hardware. However, these
can be used as software instructions in a program to transfer program execution to
one of the eight locations. No flags are affected.
Description: The contents of the operand (register or memory) and the Borrow flag
are subtracted from the contents of the accumulator and the results are placed in the
accumulator. The contents of the operand are not altered; however, the previous
Borrow flag is reset. All flags are altered to reflect the result of the subtraction.
Description: The 8-bit data (operand) and the borrow are subtracted from the
contents of the accumulator, and the results are placed in the accumulator. All flags
are altered and the results are placed in the accumulator.
Description: The contents of register L are stored in the memory location specified
by the 16 bit address in the operand, and the contents of H register are stored in the
next memory location by incrementing the operand. The contents of registers HL are
not altered. This is a 3-byte instruction; the second byte specifies the low-order
address and the third byte specifies the high order address. No flags are affected.
Description: The contents of the accumulator are copied into the memory location
specified by the contents of the operand (register pair). The contents of the
accumulator are not altered. No flags are affected.
Description: The contents of the register or the memory location specified by the
operand are subtracted from the contents of the accumulator, and the results are
placed in the accumulator. The contents of the source are not altered. All flags are
affected to reflect the result of the subtraction.
Description: The 8-bit data (the operand) are subtracted from the contents of the
accumulator and the results are placed in the accumulator. All flag are modified to
reflect the results of the subtraction.
Description: The contents of register H are exchanged with the contents of register
D and the contents of register L are exchanged with the contents of register E. No
flags are affected.
Description: The 8 bit data (operand) are exclusive ORed with the contents of the
accumulator, and the result are placed in the accumulator. Z,S,P are altered to
reflect the results of the operation. CY and AC are reset.
56. XTHL: Exchange H and L with Top of Stack.
Description: The contents of the L register are exchanged with the stack location
pointed out by the contents of the stack pointer register. The contents of the H
register are exchanged with the next stack location (SP+1); however, the contents
of the stack pointer register are not altered. No flags are affected.
ADDRESSING MODES:
Every instruction of a program has to operate on a data. The method of
specifying the data to be operated by the instruction is called Addressing. The 8085
has the following 5 different types of addressing.
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
Immediate Addressing:
In immediate addressing mode, the data is specified in the instruction itself.
The data will be a part of the program instruction.
Ex: MVI B, 3EH - Move the data 3EH given in the instruction to B register.
Direct Addressing:
In direct addressing mode, the address of the data is specified in the
instruction. The data will be in memory. In this addressing mode, the program
instructions and data can be stored in different memory.
Ex: LDA 1050H - Load the data available in memory location 1050H in to
accumulator..
Register Addressing:
In register addressing mode, the instruction specifies the name of the register
in which the data is available.
Ex: MOV A, B - Move the content of B register to A register.
Implied Addressing:
In implied addressing mode, the instruction itself specifies the data to be
operated.
Ex: CMA - Complement the content of accumulator.
Parallelogram
To represent input or output operation
Rectangular box
To represent simple operations other than I/O
operations
Rectangular box with
double lines on vertical
sides To represent a subroutine or procedure
Initialize
Display
Update
No
Is this
final
count
Yes
Time delay:
Ø The procedure used to design a specific delay is similar too that used to set
up a counter.
Ø A register is loaded with a number, depending on the time delay required and
then the register is decremented until it reaches zero by setting up a loop
with a conditional jump instruction.
Ø The loop causes the delay, depending upon the clock period of the system.
Time delay using one register:
Ø The flow chart shows a time delay loop.
Ø A count is loaded in a register, and the loop is executed until the count
reaches zero.
Ø The set of instructions necessary to set up the loop is shown below.
Load delay Register
Decrement Register
No
Is
Register=0
Yes
The time delay can be considerably increased by setting a loop and using a
register pair with a 16-bit number (maximum FFFFH). The 16 bit number is
decremented by using the instruction DCX.
Label Opcode Operand Comments T-
States
LXI B,2384H ;Load BC with 16 bit count 10
Loop: DCX B ;Decrement (BC) by one 6
MOV A,C ;Place contents of C in A 4
ORA B ;OR (B) with (C)
to set Zero flag
JNZ Loop ;if result =
0,jump back to Loop 10/7
Time delay:
• The time delay in the loop is calculated as in the previous example. The loop
includes four instruction: DCX, MOV, ORA, and JNZ, and takes 24 clock
periods for execution. The loop is repeated of 2384H times which is converted
to decimal as
2384H= 2x (16)3 + 3x(16)2 + 8x(16)1 + 4(16)0 = 909210
If the clock period of the system =0.5µs, the delay in the loop T
TL= (0.5 x 24 x 909210)
≈109 ms (without adjusting for the last cycle)
Total delay Td = 109 ms + T0:
≈ 109 ms (The instruction LXI adds only 5µs.
Time delay using a loop within a loop technique:
A time delay similar to that of a register pair can also be achieved by using
two loops; one-loop insides the other loop is shown in below figure. For example,
register C is used in the inner loop (LOOP 1) and register B is used for the outer loop
(LOOP 2). The following instructions can be used to implement the flow chart is
shown in figure.
MVI B, 38H 7T
Loop2: MVI C,FFH 7T
Loop1: DCR C 4T
JNZ Loop1 10/7T
DCR B 4T
JNZ Loop2 10/7T
Delay calculations:
The delay in Loop 1 is TL1=1783.5µs. We are replace loop1 by
TL1. Now we can calculate these delay in Loop2 as if it is one loop; this loop is
executed 56 times because of the count (38H) in register B:
TL2=56(Tl1+21 T states x 0.5µs) = 56(1783.5µs+10.5µs) = 100.46ms.
Loop 2
Load register C
TL, Delay
Loop1 in Loop
Decrement
Register C
No DCR
B
Is register
C=0
JNZ
Loop2
Yes
Decrement register
B
No
Is register
B=0
• The total delay should include the execution time of the first instruction (MVI
B,&T); however, the delay outsides these loops insignificant. The time delay
can be increased considerably by using register pairs in the above example.
• Using INTEL 8279, a keyboard and six numbers of 7-segment LEDs are
interfaced to the system. The system has been designed to accept the
desired temperature and various control commands through keyboard.
The traffic lights placed at the road crossings can be automatically switched
ON/OFF in the desired sequence using the microprocessor system. The system can
also have a manual control option, so that during heavy traffic (or during traffic jam)
the duration of ON/OFF time can be varied by the operator.
• The system has been developed using 8085 as CPU. The system has
EPROM memory for system program storage and RAM memory for
stack operation. For manual control a keyboard have been provided. It
will be helpful for the operator if the direction of traffic flow is
displayed during manual control. Hence 7 segment LEDs are interfaced
to display the direction of traffic flow both during manual and
automatic mode.
• The primary function of the microprocessor in the system is to switch
ON/OFF the Red/Yellow/Green lights in the specified sequence. In the
demonstration system of fig shown, Red/Yellow/Green LEDs are
provided instead of lights (lamps). The LEDs are interfaced to the
system through buffer (74LS245) and ports of 8255.
Ø In the practical implementation scheme the lights can be turned ON/ OFF
using driver transistors and relays.
Ø In practical implementation the output of buffer (74LS245) can be connected
to the driver transistor.
Ø A relay placed at the collector of the transistor can be used to switch ON/ OFF
the light as shown in fig.
Ø A reverse biased diode is connected across relay coil to prevent relay
chattering (for free-wheeling action).
The microprocessor sends HIGH through a port line to switch ON the light and
LOW to switch OFF the light. A switching schedule (or sequence) can be developed as
shown in table. In this switching sequence it is assumed that the traffic is allowed
only in one direction at a time.
Switching Circuit for Traffic light
Ø The processor can output the codes for switching the lights for
schedule-I and then waits. After a specified time delay the processor
output the codes for schedule-I and so on.
Ø For each schedule the processor can wait for a specified time. After
schedule-XH, the processor can again return to schedule-I. On
observing the schedules we can conclude that three different delay
routines are sufficient for implementing the twelve switching
schedules.
Ø The step size in the motor is determined by the number of poles in the
rotor and the number of pairs of stator windings (one pair of stator
winding is called one phase). The stator windings are also called
control windings.
Ø The basic step size of the motor is called full-step. By altering the
switching sequence, the motor can be made to run with incremental
motion of half the full-step value.
8085 Microprocessor Based Stepper Motor Control System
Ø A two phase or four winding stepper motor control system is shown in
above figure. The system consists of 8085 microprocessor as CPU,
EPROM and RAM memory for program & data storage and for stack.
Ø Using INTEL 8279, a keyboard and six number of 7-segment LED display
have been interfaced in the system. Through the keyboard the operator can
issue commands to control the system. The LED displays have been
provided to display messages to the operator.
Ø The windings of stepper motor are connected to the collector of
Darlington pair transistors. The transistors are switched ON/OFF by the
microprocessor through the ports of 8255 and buffer (74LS245).
Ø A freewheeling diode is connected across each winding for fast switching.
The flowchart for the operational flow of the stepper motor control system
is shown.
Ø The processor has to output a switching sequence and wait for 1 to 5 msec
before sending next switching sequence.
Part A
1. Distinguish I/O mapped I/O and memory mapped I/O.
2. Explain the execution of the instruction CMA M in 8085.
3. What is the function performed by SIM instruction?
4. What is meant by processor cycle?
5. Explain the different types of flags in 8085.
6. What are the two compare instructions available in 8085.
7. When the READY signal of 8085 processor is sampled by the processor?
8. What is DAD and what are the flags, affected by this instruction?
9. List the Software and Hardware interrupts of 8085?
10. How to calculate the vector address of software interrupts and calculate for all.
Part B
1. Explain the 8085 architecture in detail
2. Draw the pin configuration of 8085 processor & explain the signals
3. Draw the Timing diagram for the following machine cycles.
(i) Opcode fetch (ii) Memory Read (iii) Memory Write
(iv) I/O Read (v) I/O write
4. (i) Explain the classification of 8085 Instruction set with some examples.
(ii) Write about the addressing modes of 8085.
5. (i) How do you Interface a memory with 8085?
(ii) Explain the memory mapped I/O Interface.
6. (i) Draw the Timing diagram of STA 8080 instruction and explain each cycle.
(ii) Draw the Timing diagram of IN 10 and MVI A, 70H instruction & explain
each cycle.
7. How will you interface a peripheral device with 8085 processor? Explain.
8. (i) Discuss the interrupt system of 8085.
(ii) Draw the timing diagram for memory read operation performed by
8085 (Use associated signals).
12. Write a program to count continuously in hexadecimal from FFH to OOH in a
system with a 5 µsec clock period. Use register C to set up a one millisecond
delay between each count and display the number at one of the output ports.
13. (i)List all the control signals of the Timing and control unit. Explain the use of each
of these signals.
(ii)Write an ALP to evaluate the expression C=A2 +B2.
14. (i)Compare the similarities and differences between PUSH /POP and CALL/RET
instructions.
(ii)What are the features of FIFO and LIFO memory structure?
(iii)Draw and explain the timing diagram for the execution of the instruction LDA
2080 H.
15. What is the memory mapped I/O and I/O mapped I/O. Explain.
16. (i)Explain with the help of suitable diagram how the INTR pin can be used to
interrupt the 8085 and how it to the signal.
(ii)Bring out the differences between memory mapped I/O and I/O mapped I/O.
17. (i)Explain the logic instructions of 8085 microprocessor with examples.
(ii)Write an ALP using 8085 instruction set to add two n-byte numbers stored at
memory locations starting and respectively. Store the result at memory
location starting from . Draw the flow chart.
Unit-II
Part A
1. Distinguish microprocessor and micro controller.
2. List any two applications of micro controller.
3. Write and ALP for 8051 to implement a BCD, counter and store the count in
memory location starting from .
4. What is the significance of Interrupt Priority control register in 8051
microcontrollers?
5. Write an ALP for time delay using a register pair available in 8085.
6. What is the job of the TMOD register?
7. What is the function of DPTR register?
8. Name the interrupts of 8051 micro controllers.
9. What is the importance of special function registers available in 8051 micro
controllers?
10.What is the voltage level used in RS 232?
Part B
1. Explain briefly the architecture or 8051.
2. (i)List the various special function registers in 8051 and explain its usage.
(ii)With neat diagram explain ports 1 pin configuration.
3. (i)Explain the significance of SFRs in 8051 micro controller.
(ii)Explain how to interface external memory devices with 8051 micro controller.
4. (i)Write an ALP in 8051 to sort the numbers stored in an array.
(ii)Compare the features of 8 bit and 16 bit micro controller.
5. Explain with neat diagram of port pin and circuits that connect the 8051 micro
controller to the outside world.
6. With neat sketch, describe the hardware features of 8051 microcontroller.
7. (i)Draw the bit pattern of program status word of 8051 and explain the
significance of each bit with examples.
(ii)List the special function registers of 8051 micro controller and explain their
functions.
8. (i)Explain the various modes available for timer in 8051 microcontroller.
(ii) Discuss the interrupt structure of 8051 microcontroller.
9. Draw the pin configuration of 8051 and explain the signals.
10. (i)Explain the hardware circuits used in 8051 microcontrollers.
(ii)Explain the operation of the following hardware circuits in 8051.
(i) Timers (ii) Serial data I/O (iii) Interrupts (iv) External memory
11. Explain the architecture of 16 bit microcontroller in detail (80196).
12. With necessary hardware and software details explain how to interface
LCDs with 8051 micro controller.
13. (a) Explain with neat diagram of port pin & circuits that connect the 8051
microcontroller to the outside world.
(b) With neat sketch, describe the hardware features of 8051 microcontroller.
Unit-III
Part A
Part B
1. With neat diagram explain the architecture of 8086 processor.
2. (i)Explain the instruction set of 8086 with examples.
(ii)Briefly explain the advanced design features in Intel Pentium processor when
compared with 486 processor.
3. (i)Explain with examples the addressing modes of 8086 processor.
(ii)Explain the interrupt structure or 8086 processor.
4. Explain the minimum and maximum mode of operation of o8086 microprocessors
5. (i)Explain any three addressing modes of 8086.
6. (ii)Discuss the interrupt mode configuration of 8086 processor.
7. (i)Design an 8086 based system in minimum modes to intsesrfac3e 64 KB
EPROM and 64KB RAM with starting address 00000H and 80000H respectively.
(ii) Draw the pin configurations of 8086 and explain the signals
8. Discuss the features and architecture of Pentium processor with necessary
diagrams.
9. Explain the architecture of 80386 (32-bit)
10. Explain the architecture of 80486 (32-bit)
11. Explain the working of 8086 in maximum mode systems.
12. Explain the working of 8086 in minimum mode systems.
13. (i) Explain the Instruction set of 8086.
(ii) Write any 5 features of 8086.
Unit-IV
Part A
Part B
1. List the major components of the 8279 keyboard/ display interface and explain
their functions, with neat diagram.
2. Design an interfacing circuit to read data from an A/D converter using 8255 in
memory mapped I/O form.
3. (i)Explain the important features of programmable DMA controller.
(ii)Show how the 8255 PPI can be interfaced to the 8085 processor based system
with 2 K bytes of EPROM.
4. What are the different modes of serial communication? Draw the internal block
diagram of 8251 and explain how the CPU uses it for serial communication.
5. (i)What are the different modes of DMA transfer?
(ii)With a neat sketch show how a DMA controller is connected to the 8085
processor. Outline the sequence of operation needed in performing a DMA
transfer.
6. (i)Interface 8251 A to 8086 in I/O mapped I/O mode and memory mapped I/O
mode.
(ii)Discuss the features of programmable DMA controller with functional block
diagram.
7. Explain how to interface:
a. ADC and
b. DAC with 8051 micro controller.
Unit-V
Part A
1. With neat block diagram explain the operation of 8085 based stepper motor
control system.
2. With neat diagram explain the operation of 8085 based industrial temperature
control system.
3. With necessary hardware and software details explain how to interface LCDs with
8051 microcontroller.
4. (i)Explain with diagram how to interface stepper motor with a microprocessor.
(ii)How optical motor shaft encoders are used in motor control applications.
5. (i)With a block diagram and flow chart, explain the operation of microcomputer
based smart scale.
(ii)Show how will interface a stepper motor to the microprocessor.
6. (i)Develop a hardware and necessary software algorithm to run a stepper motor in
the forward direction through five revolutions in 10 seconds. Assume necessary
specification for the stepper motor.
(ii)With block diagram explain briefly the microprocessor based scale.