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Extraction of Si-SiO2 Interface Trap Densities in MOSFETs With Oxides Down to 1.

3 nm Thick
By D. Bauza, Institut de Microelectronique, Electromagntisme et Photonique (IMEP), UMR CNRS 5130, INPG, ENSERG, 23, rue des Martyrs, BP 257, 38016 Grenoble Cedex 1, FRANCE. E-mail: bauza@enserg.fr Abstract
It is shown that reliable interface trap density values can be extracted from MOS devices with ultrathin oxides by using charge pumping and small gate voltage swings. This presents three advantages with respect to the conventional large gate voltage swing approach: the extraction is simple as carrier emission do not contribute to the CP signal so that the CP current magnitude directly reflects the interface trap density; the tunneling current is strongly reduced allowing a more easy extraction of the CP signal; this prevents the insulator and the insulator-silicon interface from any degradation. By doing so, interface trap densities from MOS devices with oxides down to 1.3 nm thick are reported for the first time. edges are assumed. This model holds at the maximum of Elliot curves [5], in which the gate bias is scanned while keeping the gate pulse amplitude constant. It is based on the fact that the traps located at Fermi level during the time at the high and low bias levels have identical emission and capture rates so that when switching the device from one level to the other, the traps that could emit their carrier towards the nearest carrier band, capture a carrier from the other carrier band and emission do not contribute to the CP current. Accounting for the large distribution of trap time constants at the Si-SiO2 interface, the charge recombining during one period of the gate signal, Qcp, can be written as [6, 7]:

1. Introduction
In VLSI MOS devices, conventional interface trap characterizations techniques become unusable as soon as the parasitic Fowler-Nordheim or direct tunneling currents become significant. This is an important feature, as interface trap density, Dit, measurements have always been a standard characterization tool for technological processes. For this, the use of charge pumping (CP) at high frequencies has been proposed but the ratio CP over leakage current remains small [1]. Methods based on stress induced leakage current are also studied [2, 3]. In this article, Dit is measured simply with CP using small gate voltage pulses. This strongly increases the frequency range in which the CP signal can be measured and allows reliable Dit values to be obtained.

Q cp = I cp /f = qWL



d ox

N t (E, x)F(E, x)dE


where Icp is the CP current, f is the gate signal frequency, q is the absolute electron charge, W and L are the width and length of the device, Eh and El are the Fermi level position at the interface during the high and low bias, dox is the gate oxide thickness, Nt(E,x) is the volumic trap concentration at energy E and distance x from the SiSiO2 interface when assuming tunneling for the capture of carriers [6, 7]. F(E), the filling function variation of the traps primarily derived by Wachnik and Lowney [4], has been modified to account for the large trap time constant distribution [6, 7]:

2. Extraction of interface trap densities using small gate voltage pulses

Wachnik and Lowney [4] have proposed a model of CP in which small gate pulses with abrupt transition

[1 exp{ c (E, x)t }] F(E, x) = 1 exp{ 2c (E, x)t }

2 n, p h,l n, p h,l


In equation 2, th,l = (1/2f 2 tr,f) is the time for capture, tr,f = tr = tf, being the transition time of the gate signal. cn,p(E, x) is the capture rate for electrons and

holes of the traps at E and x. cn(E, x) = cp(E, x) are equal at Elliot maxima [7]:

50 ns

Voltage swing (V)

cn,p(E, x) = cn(E, x) = cp(E, x) = (n=p) e,h(x) vth (3), with: e,h(x) = e,h(0) exp(-x/) (4).


e = h (cm2) = 10-17 10-16

n and p are the electron and hole concentration at the silicon surface, e,h(x) = e(x) = h(x) is the trap capture cross sections for electrons and holes at x, vth is the average carrier thermal velocity, and is the tunnel attenuation distance [8]. In practical situations, the transition times of the gate signal cannot be overlooked. Emission does not contribute to the CP current if the trap that could emit a carrier after the whole transition time are situated outside the interval (Eh El). From Shockley-Read-Hall kinetics, this means that:

dox = 1.8 nm Na = 61017 cm-3


0.0 10-8

10-7 10-6 Transition time (s)


Figure 2. Maximum Vsw Values for equation 1 to hold Figure 1 shows Eh and El given by equation 5 and 6 between which emission can be neglected and therefore equation 1 holds. Figure 2 shows, the values of Vsw corresponding to Eh and El in Fig. 1 for a device with dox = 1.8 nm and Na = 6 1017 cm-3. As a result, when tr = tf = 50 ns in figure 2, as used in the experiments, equation 1 holds up to Vsw = 0.7 to 1 V depending on the trap cross sections and provided that most of the traps are filled, that is, F(E,x) = 1 in equation 1 as far as possible towards the oxide depth [7]. In the small gate pulse approach, saturation of the traps with carriers and therefore saturation of Qcp can be obtained by increasing the time for capture, that is, reducing the gate signal frequency.

E em,e E i = kTln(n i e v th t f ) > E h E i (5),


E i - E em,h = kTln(n i h v th t r ) > E i E l (6),

where Eem,e and Eem,h are the energy position of the traps that can emit after tf and tr, Ei is the intrinsic level, ni is the intrinsic carrier density, k and T being the Boltzmann constant and the temperature, respectively.



E - Ei (eV)

Vsw (V) = 1.0 0.8 0.6 0.5 0.4 0.3 dox = 1.8 nm f = 103 Hz


e = h (cm2) = 10-15 10-16 10-17 El

CP current (pA)

2 1 0 -1 -1.5

-0.5 10-8 10-7 10-6 10-5 Transition time (s)

Figure 1. Energies Eh and El between which equations 5 and 6 are verified as function of the transition time of the gate signal for three values of the trap cross sections


0.5 -0.5 0 Low bias (V)

Figure 3. CP and leakage current at dox = 1.8 nm

Then, the areal interface trap density, Dit, can be very simply obtained from equation 1 and from the CP signal magnitude as:

D it = 3. Results

Q cp qWL(E h - E l )


Figure 3 shows Elliot curves recorded at 1000 Hz for Vsw values comprised between 0.3 and 1 V from a device with dox = 1.8 nm. With such small gate pulses, the CP current can be easily observed down to such frequencies. Nevertheless, the leakage current must be removed by subtracting CP curves recorded at 50 Hz in which the CP signal is negligible [1].

0.2 0.0
CP current (A)

Dit (eV-1cm-2)

The devices used are n-channel transistors fabricated at CPMA-Grenoble, France. Their width and length were 300 x 0.2 m2 for the devices with dox = 2.3 and 1.3 nm and 10 x 10 m2 for the devices with dox = 1.8 nm. For these later devices, the transition time of the gate signal was increased from 50 ns to 300 ns to suppress the geometric effect [9]. The doping concentrations were 3 1017 cm-3, 6 1017 cm-3 and 2 1018 cm-3 for the devices with dox = 2.3, 1.8 and 1.3 nm, respectively. 1011 dox = 2.3 nm Vsw (V) = 10 1.0 10 0.8

f (Hz) = 10 3.0 105 5.5 105 1.1 106 1.8 106 3.0 106

-0.4 -0.6 -0.8 -1.0

dox = 1.3 nm Vsw = 0.8 V

40 20
f (Hz) = 3 106


0 0.5 Low bias (V)

109 10

0.6 0.5 0.4

Figure 5. As measured CP curves as a function of frequency when dox = 1.3 nm and Elliot curve extracted In Figures. 4a and 4b, the evolution of Dit with f for different Vsw when dox = 2.3 and 1.8 nm is displayed. As expected, Dit saturates when increasing Vsw and reducing f so that from the CP curves at 0.8 or 1 V, Dit = 1.4 1010 eV-1 cm-2 and 1.8-2 1010 eV-1 cm-2 for these technologies. The slight decrease of Dit for the largest Vsws at low frequencies results from the small CP current that exists in the curves at 50 Hz used to suppress the leakage component or by the inaccuracy of this method for a very precise extraction of the CP current. Figs. 5 and 6 show the results obtained for a device with dox = 1.3 nm. The CP current is now swamped in the leakage current (Fig. 5). Nevertheless, Elliot curves can be extracted at high frequency, as also shown in Fig 5, so that for this technology, Dit is around 2 1012 eV-1 cm-2 as shown in Fig. 6. One can note in Fig. 6, that the dependence of Dit with Vsw is weaker for this oxide thickness than for the thicker oxides in Fig. 4. This suggests large trap capture cross sections for this oxide. In addition, the increase of Dit between dox = 1.8 and 1.3 nm is much greater than between dox = 2.3 and 1.8 nm. This could result from the





104 105 106 Frequency (Hz)

Vsw (V) = 1.0 0.8 0.6


dox = 1.8 nm

Dit (eV-1cm-2)

1010 10

0.5 0.4

108 107 2 10


103 104 105 106 Frequency (Hz)

Figure 4. Evolution of Dit with f and Vsw when (a) dox = 2.3 nm and (b) dox = 1.8 nm

Qcp (fC)



increase of the stress at the Si-SiO2 interface when reducing dox, in relation with the reduction of the time to breakdown [10]. 1013 dox = 1.3 nm


Vsw (V) = 0.8 0.7 0.6 0.5

1011 102


104 105 106 Frequency (Hz)


Figure 6. Dit obtained as a function of f and Vsw for a device with dox = 1.3 nm

4. Conclusion
It has been shown that reliable interface trap densities values can be measured in MOS devices with ultrathin oxides. This is achieved by using charges pumping in the small gate pulse mode and has been applied to devices with different oxide thickness, down to 1.3 nm. This prevents the oxides from any degradations and strongly reduces the oxide leakage allowing the extraction of the CP current in a large range of gate signal frequencies and/or down to very small thicknesses.

Monitor for Untrathin Oxides IEEE Trans. Electron Devices ED-47, 2358 (2000). [3] D. Ielmini, A.S. Spinelli, M.A. Rigamonti, and A.L. Lacaita, Modeling of SILC Based on Electron and Hole Tunneling-Part II: Steady-State IEEE Trans. Electron Devices ED-47, 1266 (2000). [4] R.A. Wachnik and J.R. Lowney, A Model for the Charge-Pumping Current Based on Small Rectangular Voltage Pulses Solid-St. Electron. 29, 447 (1986). [5] A.B.M. Elliot, The Use of Charge Pumping Currents to Measure Surface State Densities in MOS Transistors Solid-St. Electron. 19, 241 (1976). [6] D. Bauza and G. Ghibaudo, Analytical Study of the Contribution of Fast and Slow Oxide Traps to the Charge Pumping Current in MOS Structures Solid-St. Electron. 39, 563 (1996). [7] D. Bauza and Y. Maneglia, In-Depth Exploration of Si-SiO2 Interface Traps in MOS Transistors Using the Charge Pumping Technique IEEE Trans. Electron Devices ED-44, 2262 (1997). [8] F.P. Heiman and G. Warfield, The effect of oxide traps on the MOS Capacitance, IEEE Trans. Electron Devices ED-12, 167 (1965). [9] J.S. Brugler and P.G.A. Jespers, Charge Pumping in MOS Devices, IEEE Trans. Electron Devices ED-16, 297 (1969). [10] T. Yang and K. Saraswat, Effect of Physical Stress on the Degradation of Thin SiO2 Films Under Electrical Stress IEEE Trans. Electron Devices ED-47, 746 (2000).

5. References
[1] P. Masson, J.L. Autran, and J. Brini, On the Tunneling Component of Charge Pumping Current in Ultrathin Gate Oxide MOSFETs IEEE Electron Device Lett. 20, 92 (2000). [2] A. Ghetti, E. Sangiorgi, J. Bude, T.W. Sorsch, and G. Weber, Tunneling into Interface States as Reliability

Dit (eV-1cm-2)

This work has been supported by Ultimox/RMNT and RA-Nanodiel projects. The author wish to thank Martine Gri from IMEP for technical assistance.