6.

012

Microelectronic Devices and Circuits

Optical Receiver Design Project
Assigned Out: Wednesday, April 24, 2013 Due: Friday, May 10, 2013

Spring 2013

1. Introduction In this project, you are going to design an optical receiver for laser pulses sent over an optical fiber by a transmitter as part of a data communication channel. In the fiber optic system, a transmitter encodes the data as IR laser pulses and transmits the pulses over a long optical fiber. At the other end of the optical receiver detects the attenuated optical signal, transduces it to an electrical signal and then amplifies electrical signal to digital levels. For simplicity we shall assume that the data transmitted is encoded into a 4-bit word. The transmitter sends these words using infra-red pulses, four pulses per word, or one pulse per bit. The bit rate is 10 MHz. Your task is to design the receiver to detect IR signals sent by the transmitter and convert them back into digital bits. To make things more interesting, the words transmitted are actually encrypted. In order to get the correct word at the output, you need to perform a NOR function of the detected word with the encryption key, 1101. Finally, your design needs to be able to drive a load capacitor of 1pF. A 1.5m CMOS process is available for this design. You can download the model file from the course website under the link Project. The relevant parameters are the SPICE Level I parameters such as VTO, UO, TOX (or COX), CGDO, CJSW, CJ, PB, MJ, MJSW, etc. Note that 1.5 m CMOS process means Lmin = 1.5 m and in most instances means minimum LG = Lmin and minimum Ldiff = 2Lmin. How does IR receiver work? The functional blocks of the IR optical receiver are shown in Figure 1. The photodiode receives the IR signal and converts IR pulses into current pulses as shown in Figure 2. This current signal will vary depending on the distance between the IR transmitter and the receiver. The current is converted to voltage by an input stage and the resulting voltage signal is passed through a gain stage in which the voltage signal is amplified to a sufficient level to drive a decoder logic. The last stage of the gain stage(s) serves essentially as an analog to digital converter. After the signal is decoded it is used to drive another chip which is represented by the load capacitance. 2. Design Specifications 1.5m CMOS process, with a supply voltage VDD=5V Frequency fTX=10 MHz (bit rate) Maximum power consumption Pdc=7.5mW Maximum total propagation delay td= tPHL +tPLH=50ns Load capacitor CL=1pF High output (bit 1) voltage VH>4.9V, and low output (bit 0) voltage VL<0.1V

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3. Design process

Figure 1: Block Diagram

The project can be divided into four parts as shown in the block diagram in Figure 1.

Signal source: A reverse biased photo diode is used to detect the IR signal. The current on this photo diode provides the input for your design. The diode can be represented by an ideal current source in parallel with a 1pF parasitic capacitor as shown in Figure 2. The diode current has a peak current of 10A when detecting the bit 1, and 0 when detecting the bit 0. Although the laser diode in the optical transmitter produces a large square wave pulse at the end of the fiber, dispersion and loss make the diode current, is, appear sinusoidal. This current is guaranteed to have a peak of about 10 A.

Photons

A
1pF

A
is

is 10A

100 200 Time (ns)

300

400

B
Photo Diode

B
Circuit Model
Figure 2: Photo Diode Signal Source

Example: detecting 1011

Input stage: Usually, it is easier to amplify voltages than currents. In addition, your design needs to drive a logic gate. Therefore, the input signal, in the form of the current on the photo diode, needs to be converted into voltage. This conversion can be accomplished by a trans-impedance amplifier (TIA) (it is also referred to as trans-resistance amplifiers). TIAs usually have small input impedance and large output resistance. Hint: which of the transistor configurations (common-gate, common-source ) fit this description?

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 Gain stage(s): Additional gain stage(s) might be necessary to amplify the input signal enough to drive the decoding logic. Keep in mind that these gain stages are voltage amplifiers and the last of these stages essentially converts the analog signal to digital signal by clipping the analog signal, hence the last of the gain stages is often called a saturating (or limiting) amplifier. [See lecture 18 notes that introduces amplifiers]. You are free to choose the topologies as well as biasing circuits for these amplifiers. Decoding Logic: A NOR gate provides the decoding logic and it drives an output buffer. The two inputs of this NOR gate are the encryption key 1101, and the detected word from the infra-red signal. The key 1101 can be represented by an ideal piecewise linear voltage source. Output stage: A buffer driving a 1pF load capacitor provides the output. The 1pF load capacitor presents a design challenge. In order to satisfy the time delay requirement, you will need a reasonably sized output buffer to drive the 1pF load. However, a large output buffer has two drawbacks. First, it consumes more power. Second, since it is the load to the decoding logic, it directly affects the power consumption as well as time delay of the decoding stage. It is possible to size the output buffer such that it can drive the 1pF load capacitor directly and still satisfy both the power consumption and time delay requirement. However, you might find it easier to insert another sized buffer stage between the decoding logic and the 1pF load capacitor (Read Section 13.5.3 of Howe and Sodini).

4. Design Approach You are encouraged to approach the design using hand-calculations. Use the NMOS & PMOS parameters in the SPICE model file. You should only use HSPICE after you have chosen topologies and determined all the component values. The results from HSPICE help you with verifying your prediction from handcalculation, and final tweaking to meet all the specifications. You are strongly encouraged to present your rough hand calculations and design approach to the instructors for feedback during office hours.

5. Schedule As in most technical design problems, time is not an infinite resource and it often has an effect on the overall cost. Furthermore, time to market determines very much the success of products. With this in mind we suggest that you follow the schedule outlined below with individual milestones and deliverables which will be turned in.. The first milestone is the topological design outlining the circuit elements (transistors and passive elements) that comprise each of the stages in the block diagram (a) transimpedance amplifier (TIA), (b) gain stages including the limiting amplifier, (c) the NOR gate for the decoding logic and (d) output driver. This could be done without the bias

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circuits but the schematic of the bias circuit should be specified. This should be completed and a copy turned in by Thursday, May 2, 2013 at 5:00 PM or earlier. Remember to retain a copy for later use. Our objective is to make sure you are on schedule. The second milestone is the completion of design based on hand calculation including (a) bias circuits, (b) transistor sizes for each block & values of passive elements comprising each block, (c) performance of each block and overall transceiver performance. This should be completed by Monday, May 6, 2013 by 5:00 PM or earlier. Please turn-in a copy of your calculations but remember to retain a copy for later use. Our objective is to make sure you are on schedule. The third milestone is simulation of your device using SPICE and adjustment of parameters to improve performance. This should be completed by Thursday, May 9, 2013 at 5:00 PM or earlier but no report is due. The final milestone and your final deliverable is the report which is due on Friday, May 10, 2013 at 5:00 PM by electronic submission if possible.

6. Report You are expected to submit a complete report. Your report must describe your design in a clear, concise, and complete manner. The report should include the following parts: Circuit schematic (maximum 1 page). Neatly draw your final circuit, labeling all the component names, size and values. Make sure to indicate all the dc bias conditions (dc voltage of all nodes, and dc current of all components) Approach (maximum 2 pages) Explain your design approach and topology selections. For each stage (TIA, voltage amplifier, decoding logic, output), discuss the design tradeoffs that you discovered. Final HSPICE input file (maximum 1 page) You should remove all the model parameter lines from the printout. Hand in only the circuit description and simulation portion. HSPICE output Plots (maximum 1 page) Include the transient analysis plot of the output. Please mark the time delays (tPHL and tPLH). Hand Calculations (maximum 3 pages) If you turned in your hand calculations earlier, you do not need to turn in another one if there are no significant changes NB: Please be prepared to demonstrate that your circuit simulation works. The TAs may ask you to load the SPICE deck and run the simulation on Friday, May 10, 2013 (Due Date). The interim reports will only be graded when the final report is graded.

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POLICY FOR ACADEMIC CONDUCT

The homework and design problems in 6.012 are prepared with the aim of complementing lectures and recitations and are designed to reinforce important concepts and material. Working on the problem sets and design problems is extremely effective in assuring your command of the course material. In order to encourage you to do the homework and design problems in a timely manner, a significant fraction of the final grade will be based on your performance in these exercises. This brings up important ethical questions to the foreground. Our judgment is that allowing and encouraging collaboration with fellow students best serve the primary learning purpose of homework and design problems. After all, modern engineering is almost exclusively a team effort. However, fairness requires us to be able to assess your own contribution. This also provides you with feedback that helps you learn better. Towards this goal, below are the rules for academic conduct in 6.012 this semester: You are allowed and encouraged to work with fellow students on homework and design problems. All parties must acknowledge collaborations or discussions in writing in the assignment. You must work out the entire assignment. The written material that you hand in must be your own work.

The policy of academic conduct outlined in this handout is intended to help you make the most out of 6.012 by freely working with your classmates and any material you may find useful. If you have any doubts as to what constitutes ethical or unethical behavior, please contact any member of the staff. Violations to this policy will be handled with the maximum severity allowed by the Institute's Rules and Regulations regarding academic honesty as outlined on the web at http://web.mit.edu/discipline/academic.html.

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