Phase Locked Loop PLL

Phase Locked Loop (PLL)
Suchendranath Popuri
References
F. M. Gardner, Charge Pump Phase Locked Loops, IEEE transactions on Communications, vol. COM28, no.11, Nov 1980, pp. 1849-1858 Nagendra Krishnapura, Synthesis Based Introduction to Opamps and Phase Locked Loops, Proc. 2012 IEEE ISCAS, May 2012 F. M. Gardner, Phaselock Techniques, Wiley Interscience
S. Popuri
VIT
Lecture Topics
Analogy with amplifier & basic operation
Basic PLL Incremental models for PD, VCO & Counter
Type I PLL
Incremental analysis
Type II PLL
Charge pump PLL (CPLL) Incremental analysis Adding extra pole Stability analysis Design procedure & example
Problems with incremental model

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Lecture Topics
Type I PLL
Type II PLL

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Analogy between amplifier & frequency multiplier

Amplifier
In steady state, Vout = N.Vin
Ve = 0
Frequency multiplier
In steady state, fout = N. fref
fe = 0
K is dimension less
VCVS
Units of K are Hz/Volt

VCO
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VIT
Frequency Multiplier
Phase detector
Counter
VCO
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Phase Locked Loop (PLL)
Basic version of PLL; consists of phase detector, VCO & counter In steady state, ref fb 0 so that PD will generate a control voltage Vctl, which inturn drives the VCO to lock to the loop.
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Phase detector
Phase detector should not be sensitive to different duty cycle signals of same period.
k PD
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average(QA QB )
AB
VPD ; units 2
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Volts radians
VIT
Transfer characteristics of PD
QA & QB together contain the phase error information. Their time difference is proportional to the phase error.
k PD
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average(QA QB )
AB
VPD ; units 2
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Volts radians
VIT
State Diagram of Phase detector

It has only 3 states (00, 10, 01); hence the name 3-state phase detector. If fA > fB AB always positive; only 2 states (00,10) If fA < fB AB always negative; only 2 states (00,01); hence the name 3-state phase frequency detector.
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Equivalent circuit of 3-state PD
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Voltage Controlled Oscillator (VCO)

O/p frequency (Hz)
f out
out
f free
k vco Vctl
k vco Hz / V
2 f out
O/p phase (radians)

out
2 2
f out dt f free t 2 k vco Vctl dt
out
free running
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incremental part
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VIT
Incremental equivalent of VCO

out
2
out
f free t
2
2 k vco Vctl dt
vctl ) dt
out
f free t 2 kvco (Vctl
out
2 kvco vctl dt
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Incremental equivalent of counter
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Lecture Topics
Type I PLL
Type II PLL

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Type I PLL Incremental analysis (1)

It is a first order system. Inherently stable. The system tracks phase variations whose frequencies are less than bandwidth of the system.
2 k PD kVCO Ns
N 1 s 2 k PD kVCO / N
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LG ( s)
( s) ref ( s )
out
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Periodic error is introduced. It is a first order system.

LG ( s)
( s) E ( s)
out | out
2 k PD kVCO Ns
N 1 s 2 k PD kVCO / N
( s) ref ( s )
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To reject the PD error[e (t )], f ref should be chosen 2 k PD kVCO such that; f ref Phase difference between reference & feedback signal in steady state = Nf ref f free
k PD kVCO
The condition on phase difference in steady state is

Nf ref f free k PD kVCO 2
From combining the above two conditions, we get

Nf ref
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f free
2 kPD kVCO
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f ref
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Phase difference between reference & feedback signal
Nf ref
ref fb
f free
k PD kVCO
DC condition
Small Phase modulation

OUT , pk pk
2 k PD kVCO 2 f ref
Condition at fref
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Lecture Topics
Type I PLL
Type II PLL

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Moving from Type I to Type II PLL
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CPLL (Charge Pump phase locked loop)
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CPLL Incremental analysis
I CP R k PD k PD , I ; 2 2 k PD kVCO u ,loop N k PD , I 1 z1 k PD RC LG ( s )
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I CP ; 2 C I CP RkVCO N
u ,loop
3 dB , PLL
;
ref
; I CP 2 sC
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u ,loop
2 kVCO Ns
I CP R 2
I CP kVCO ( sCR 1) 2 Ns C
VIT
CPLL with 1st order loop filter
Loop filter is of 1st order.
F ( s)
R(1 s 1 ) s 1
1
RC1
VIT
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Frequency response
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Adding extra pole

Periodic error from PD can be reduced further without changing other parameters by adding extra poles into the system between u ,loop and ref .
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Adding extra pole : equivalent circuit
Generally, a 2nd order filter is preferred.

b 1 (1 s 1 ) F ( s) R b s 1 (1 s p ) C1 b 1 C2 RC1 1
1
F ( s)
R(1 s 1 ) s 1
RC1
p
C1C2 C1 C2
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Magnitude response with extra pole
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Stability
LG ( s )
K
PM
K (1 s 1 ) s 2 1 (1 s p )
b 1 I CP kVCO R b N
tan 1 ( K 1 ) tan 1 ( K
1
/ b)
Two poles at origin cause instability. The zero provides phase margin (PM) ensuring stability. Large K 1 values give better PM.
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Design procedure
Given quantities
fref, N, kVCO, minimum phase margin, PMmin required closed loop bandwidth, fBW (Hz)
Calculate b:
PM min tan
1
b 1/ b 2
Calculate ICP, R, C1 such that
Nf BW I CP R and RC1 b 1 kVCO Calculate C2 such that C1 C2 b 1 b

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b 2 f BW
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Example: FM Radio [ 88 - 108 MHz ]

88.1 107.9 MHz; channel spacing is 0.2 MHz, so 88.1 MHz + K(0.2 MHz) has to be generated. N = 881, 883,., 1079; 11 flip flops are needed for counter. Counter has to be adjustable. Type II, 3rd order PLL is used. fref = 0.1 MHz B.W = 2.5 kHz Z1 << BW
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Example : FM radio contd..

Z1 BW 1 2 RC1 2.5kHz C1C2 C1 C2
extra pole 2.5kHz

BW
1 ; C12 2 RC12 1 2 RC12
100kHz
2 (2.5kHz) volts 159 A
VIT
I CP R kVCO N
for N
1000; I CP R I CP
2 20k
if R 10k
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Lecture Topics
Type I PLL
Type II PLL

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We have used a continuous time incremental model for PLL so far. PFD compares the phase only once every reference cycle.
Only the samples of VCO are fed back Causes delay in the phase feedback
The charge pump, and the loop filter operation depends on the position and the width of Up, Dn pulses.
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Additional References
J. P. Hain, et al, z-Domain Model for Discrete-Time PLL's, IEEE Transactions on Circuits and Systems, VOL. 35, NO. 11, NOVEMBER 1988 Tom A, et al, Delta-Sigma Modulation in Fractional-N Frequency Synthesis, IEEE Journal of Solid-State Circuits, VOL. 28, NO. 5, MAY 1993 M. Perrott, et al, A Modeling Approach for fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis, IEEE Journal of Solid-State Circuits, VOL. 37, NO. 8, AUGUST 2002 U.K.Moon, et al, Spectral Analysis of Time-Domain Phase Jitter Measurements, IEEE Transactions on Circuits and Systems-II: Analog & Digital Signal Processing, VOL. 49, NO. 5, MAY 2002
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Phase Locked Loop PLL

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Phase Locked Loop PLL

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Phase Locked Loop (PLL)

Problems with incremental model

Problems with incremental model

Analogy between amplifier & frequency multiplier

Units of K are Hz/Volt