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Design Rules
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Interface between the circuit designer and process engineer Guidelines for constructing process masks Rules constructed to ensure that design works even when small fabrication errors (within some tolerance) occur
Tutorial 1
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different layers
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Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fabrication
minimum line width is set by the resolution of the
Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab.
0.3 micron 0.15 0.15 0.3 micron
Select regions are the diffusions of an invert type to implement contacts to the wells or to the substrate.
2102-545 Digital ICs
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B.Supmonchai
Different Potential
1. Transistor rules transistor formed by the overlap of active and poly layers
Transistors
Catastrophic error
Well
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Polysilicon
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Active
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Metal1
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Select
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Metal2
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both materials
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Lambda-based design rules are based on the assumption that one can scale a design to the appropriate size before manufacture The assumption is that all manufacturing dimensions scale equally
For example: if a design is completed with a poly
width of 2l and a metal width of 3l then minimum width metal will always be 50% wider than minmum width poly wires
It works only over some modest span of time
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Retargetable Layouts
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Probably for retargeting between similar processes, e.g., when later process is a simple shrink of the earlier process.
This often happens between generations as a mid-life
Invent some way of entering a design symbolically but use a more sophisticated technique for producing the masks for a particular process.
Relative sizes may change but topological Instead of shrinking a design, compact it!
Most industrial designs use micron rules to get the extra space efficiency.
Cost of retargeting by hand is acceptable for a
More often nowadays, designs are described by HDLs, such as VHDL or Verilog
Re-compiled and mapped to a new technology Best performance functional units are laid by hands -
difficult to shrinks
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Layout Styles
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Avoid long (> 50 squares) Poly runs Do not capture white space in a cell Do not obsess over the layout, instead make a second pass, optimize when it counts
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Optimizing Connections
Which is the better gate layouts? Considering node capacitances? Considering composibility with the neighboring gates?
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Eleminating Gaps
Replicating Cells
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What does this cell do? What if we want to replicate this cell vertically, i.e., make a stack of cells to process many bits in parallel?
Which nodes are shared
Use Logic Graphs and the method of Euler path to reorder inputs
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Vertical Replication
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Building a Datapath
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It is often the case that we want to operate on many bits in parallel. A sensible way to arrange the layout of this sort of logic is as a datapath where
data signals run
Logic that generates the control signals can be placed at the bottom of the datapath. If control logic is complicated or irregular, it might be placed in a separate standard cell block
Only the control signal buffers can be placed just
Although it is tempting to run control signals in Poly (so they can control FETs) this is unwise for tall datapaths because of poly resistance
E.g., 32 bits x 20u/bit = 640u = ~1000 sqs. ~ 20 k
Design Rules and Layout Techniques 32
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Example: Adder
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Example: Shifter
Think Globally
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Make sure that all the design rules are not violated Verification of the Layout usually takes a very long time.
Old timers use room-size layout plots. Newbies use computer-aided design tools.
Design Rule Checkers (DRC) Layout vs Schematic (LVS)
A program that checks each piece of the layout against the process design rules
Canonicalize layout into a set of leading and trailing
non-overlapping mask edges. Some boolean mask operations may be needed. edge with the node it belongs to.
Determine electrical connectivity and label each Test each edge end point against neighboring edges
to check for spacing (leading edges) and width (trailing edges) violations.
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Circuit Extraction
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First a netlist is extracted from the layout. Use the electrical info generated by the DRC and then recognize which transistors are juxtapositions of channel with diffusion See if extracted netlist is isomorphic to the schematic netlist
Initialize all nodes to the same color Compute a new color for each node as some hashing Worry about parallel FETs, ambiguous nodes
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