Convolutional Codes

Last time, we talked about:

Channel coding

Linear block codes

The error detection and correction capability Encoding and decoding Hamming codes Cyclic codes

Today, we are going to talk about:

Another class of linear codes, known as Convolutional codes.

We study the structure of the encoder.

We study different ways for representing the encoder.

Convolutional codes

Convolutional codes offer an approach to error control coding substantially different from that of block codes.

A convolutional encoder:

encodes the entire data stream, into a single codeword. does not need to segment the data stream into blocks of fixed size (Convolutional codes are often forced to block structure by periodic truncation). is a machine with memory.

This fundamental difference in approach imparts a different nature to the design and evaluation of the code.

Block codes are based on algebraic/combinatorial techniques. Convolutional codes are based on construction techniques.

Convolutional codes-contd

A Convolutional code is specified by three parameters (n, k , K ) or (k / n, K ) where

Rc k / n is the coding rate, determining the number of data bits per coded bit.

In practice, usually k=1 is chosen and we assume that from now on.

K is the constraint length of the encoder a where the encoder has K-1 memory elements.

There is different definitions in literatures for constraint length.

Block diagram of the DCS

Information source

Rate 1/n Conv. encoder

Modulator

m (m1 , m2 ,..., mi ,...)

Input sequence

U G(m) (U1 ,U 2 ,U 3 ,...,U i ,...)

Codeword sequence

Channel

U i u1i ,...,u ji ,...,uni

Branch wo rd ( n coded bits)

Information sink

Rate 1/n Conv. decoder

Demodulator

(m 1, m 2 ,..., m i ,...) m
Zi

Z ( Z1 , Z 2 , Z 3 ,..., Z i ,...)
received sequence

Demodulator outputs for Branch wor di

z1i ,...,z ji ,...,zni

n outputsper Branch wor d

A Convolutional encoder

Convolutional Encoder Representation

To describe a convolutional code, one need to characterize the encoding function G(m), so that given input sequence m, one can readily compute the output sequence U. Several methods are used for representing a convolutional encoder, the most popular: Connection pictorial Connection vector or polynomial State diagram Tree diagram Trellis diagram

A Rate Convolutional encoder

Convolutional encoder (rate , K=3)

3 shift-registers where the first one takes the incoming data bit and the rest, form the memory of the encoder.

u1
Input data bits

First coded bit (Branch word) Output coded bits

u1 , u2

u2

Second coded bit

Figure 7.3

A Rate Convolutional encoder

Message sequence:
Time
u1

m (101)
Output (Branch word)
u1 u 2 1 1

Time
u1

Output (Branch word)

u1 u 2 1 0

t1

1 0 0
u2

t2

0 1 0
u2

u1

u1

t3

1 0 1
u2

u1 u 2 0 0

t4

0 1 0
u2

u1 u 2 1 0

A Rate Convolutional encoder

Time
u1

Output (Branch word)

u1 u 2 1 1

Time
u1

Output (Branch word)

u1 u 2 0 0

t5

0 0 1
u2

t6

0 0 0
u2

m (101)

Encoder

U (11 10 00 10 11)

Effective code rate

Initialize the memory before encoding the first bit (allzero) Clear out the memory after encoding the last bit (allzero)

Hence, a tail of zero-bits is appended to data bits.

tail

data

Encoder

codeword

Effective code rate :

L is the number of data bits and k=1 is assumed:

Reff

L Rc n( L K 1)

Encoder Representation

Vector representation:

We define n binary vector with K elements (one vector for each modulo-2 adder). The i:th element in each vector, is 1 if the i:th stage in the shift register is connected to the corresponding modulo2 adder, and 0 otherwise.

Example:

g1 (111) g 2 (101)

u1

u1 u2

u2

Encoder representation contd

Impulse response representaiton:

The response of encoder to a single one bit that goes through it.

Example:

Register contents

Branch word

u1

u2

Input sequence :

1 0 0

100 010 001

1 1 1 0 1 1

Output sequence : 11 10 11
Input m Output

1 11 10 11 0 1
Modulo-2 sum:

00 00 00 11 10 11 11 10 00 10 11

Encoder representation contd

Polynomial representation:

We define n generator polynomials, one for each modulo-2 adder. Each polynomial is of degree K-1 or less and describes the connection of the shift registers to the corresponding modulo-2 adder.

Example:
(1) (1) g1 ( X ) g 0 g1(1) . X g 2 .X 2 1 X X 2 ( 2) ( 2) g 2 ( X ) g0 g1( 2) . X g 2 .X 2 1 X 2

The output sequence is found as follows:

U( X ) m( X )g1 ( X ) interlaced with m( X )g 2 ( X )

Encoder representation contd

In more details:
m( X )g1 ( X ) (1 X 2 )(1 X X 2 ) 1 X X 3 X 4 m( X )g 2 ( X ) (1 X 2 )(1 X 2 ) 1 X 4 m( X )g1 ( X ) 1 X 0. X 2 X 3 X 4 m( X )g 2 ( X ) 1 0. X 0. X 2 0. X 3 X 4 U( X ) (1,1) (1,0) X (0,0) X 2 (1,0) X 3 (1,1) X 4 U 11 10 00 10 11

State diagram
A finite-state machine only encounters a finite number of states. State of a machine: the smallest amount of information that, together with a current input to the machine, can predict the output of the machine. In a Convolutional encoder, the state is represented by the content of the memory. K 1 Hence, there are 2 states.

State diagram contd

A state diagram is a way to represent the encoder. A state diagram contains all the states and all possible transitions between them. Only two transitions initiating from a state. Only two transitions ending up in a state. The encoder state is said to be Markov, in the sense that the probability P(Xi+1|Xi,Xi-1,,X0) of being in the state Xi+1, give all previous states, depends only on the most recent state Xi; that is, the probability is equal to P(Xi+1|Xi).

State diagram contd

Current state input Next state output

0/00
Input

Output (Branch word)

1/11

S0
00

0/11

S0 00

1/00

S2
10

S1
01

S1 01 S2 10
S3 11

0/10 1/01

S3
11

0/01

1/10

0 1 0 1 0 1 0 1

S0 S2 S0 S2

S1 S3 S1 S3

00 11 11 00 10 01 01 10

State diagram contd

State diagram contd

State diagram contd

Trellis

Trellis diagram is an extension of the state diagram that shows the passage of time.

Example of a section of trellis for the rate code

State

S0 00
S 2 10

0/00
1/11 0/11 1/00 1/01 0/01 1/10 0/10

S1 01

S3 11
ti

ti 1

Time

Trellis contd

A trellis diagram for the example code

Input bits
1 11 0 10 1 0 10 Tail bits 0 11

Output bits
00

0/00 1/11

0/00 1/11 0/11 1/00

0/00 1/11 0/11 1/00

1/01 0/10

0/00 1/11 0/11 1/00

1/01 0/10

0/00 1/11 0/11 1/00

1/01 0/10

0/11 1/00
1/01 0/10

1/01
0/01

0/10

0/01
t1
t2

0/01
t3

0/01
t4
t5

0/01
t6

Trellis contd
Input bits
1 11 0 10 1 0 10 Tail bits 0 11

Output bits
00

0/00 1/11

0/00
1/11 0/10

0/00 1/11 0/11 1/00

0/00

0/00

0/11 0/10 0/01

t4
t5

0/11

1/01

1/01
0/01

0/10

t1

t2

t3

t6