UNIVERSITY OF TEHRAN Electrical and Computer Engineering Department ECE 517-3586 Logic Design, Test # 2 Spring Semester 1376-1377

Week of Lecture 32

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Grade: Problem 1. ______/20 Problem 2. ______/20 Problem 3. ______/20 Problem 4. ______/20 Problem 5. ______/20

Total: ______/100

DO NOT USE LAPTOPS EXTRA SHEETS WILL NOT BE ACCEPTED THIS IS A CLOSED BOOK CLOSED NOTE EXAM YOU MUST SHOW COMPLETE WORK ON ALL PROBLEMS YOU HAVE TWO HOURS FOR WORKING ON THIS TEST

1. Use D-type flip-flops and the PLA shown below to implement a 10110 Moore sequence detector. The state machine searches on its X input for a sequence of 10110 and generates a synchronous pulse on its Z output when the sequence is found. Overlapping sequences are allowed to set the output. 1) Show the complete state diagram for this machine. 2) Show mapping of the AND-plane and the OR-plane of the PLA for implementing the combinational part of this circuit. Show flop-flop wiring and clocking. Use Karnaugh maps for minimizing the number of rows of the PLA.

Q0

Q1

Q2

X d0 d1 d2 Z

+ + + + + + +

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND

xq2
q1q0

xq2

00 01 11 10

q1q0

00 01 11 10

00 01 11 10

00 01 11 10

xq2
q1q0

xq2

00 01 11 10

q1q0

00 01 11 10

00 01 11 10

00 01 11 10

2. Show the design of a 3 mode discrete counter. The counter has a and b control inputs that specify the 3 possible modes of operation. If ab is 00 the counter is disabled and clock pulses do not change the count state or value. The 3 modes of operation are binary up-count (00 > 01 > 10 > 11 > ), binary down-count (00 > 11 > 10 > 01 > ) and Gray up-count (00 > 01 > 11 > 10 > ...). The values of ab = 01, 11, and 10 determine these modes in this same order. Use JK flip-flops and standard logic to implement this counter. Show a complete circuit diagram. You need not draw gate level circuit diagrams. For the inputs of the flip-flops show logic boxes with appropriate Boolean equations.

3. A synchronous parallel-to-serial adapter is to be designed. The circuit has a dataready control input, a 4-bit databus data input, a transmitting output, and a serial dataout output. Parallel data is ready on the 4-bit inputs when dataready is 1. The circuit to be designed receives this data and in the next 4 clock pulses makes it available on the dataout serial output. While serial data is being shifted out, the transmitting output remains at level 1. While data is being transmitted and while transmitting is 1, new parallel data input will not be accepted. After complete transmission of a 4-bit data, the circuit will be ready for receiving the next 4-bit parallel data. A) Show the complete datapath for this circuit using packages shown below. B) Show one-hot implementation of the controller for this circuit. Show all input and output signals of this controller. C) Show all connections between the data and control parts. You need not be concerned with resetting mechanism for this circuit.

dataready

P2S
databus

transmitting dataout

clock

4. Use counter packages shown below and a minimum number of discrete gates to design a waveform generator circuit as described here. The generator has a clock input and a single output. The output is a periodic signal that is normally 1 and becomes 0 for every 140, 156, and 172 clock pulses. Initially the circuit divides its clock input by 140, then it will be dividing by 156, and then by 172. After (140+156+172) clock pulses the output returns to its initial state and starts this sequence of dividing again. Show complete hardware for this circuit. Use as few discrete gates as possible. Use of packages is encouraged.

5. A fundamental mode circuit with two inputs a and b and output z is to be designed. The circuit has odd and even modes of operation. While in the odd mode, a positive pulse on the a input switches the circuit to even mode, and while in the even mode, a positive pulse on a switches the circuit to odd mode. While in the even mode, a positive pulse on b appears on the z output of the circuit. At no time, the two inputs will be 1 at the same time, and for the purpose of this problem this situation can be set to dont care. A) Generate a primitive flow table and minimize it to a flow table. B) Make a race-free state assignment and specify output values for all unstable states. C) Show a general block diagram of the final circuit.