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5 4 3 2 1 Topstar Digital technologies Co.,LTD D D Board name: Mother Board
5
4
3
2
1
Topstar Digital technologies Co.,LTD
D
D
Board name: Mother Board Schematic
Project name: X01
1. System Block Diagram & Schematic page description;
2. Power Block Diagram & Discription;
Version: Ver B
Initial Date:
3. Annotations & information;
4. Schematic modify Item and history;
New update:
5. Power on & off Sequence;
6. ACPI Mode Switch Timings;
7. Power On Sequence Map;
8. CLOCK Distribution;
C
9. Power Distribution;
C
Topstar Confidential
Hardware drawing by:
许沐锌
Hardware check by:
EMI Check by:
Power drawing by:
Power check by:
B
B
Manager Sign by:
A
A
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Page Name
Page Name
Page Name
Title
Title
Title
Size
Size
Size
Project Name
Project Name
Project Name
Rev
Rev
Rev
A3
A3
A3
X01
X01
X01
B
B
B
Date:
Date:
Date:
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Sheet
Sheet
Sheet
1
1
1
of
of
of
39
39
39
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
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2
1
5 4 3 Topstar Confidential ShenZhen Topstar Industry Co.,LTD D P01 SYSTEM BLOCK Ver:A CK505M
5
4
3
Topstar Confidential
ShenZhen Topstar Industry Co.,LTD
D
P01 SYSTEM BLOCK Ver:A
CK505M
Clocking
Backlight
Connector
ICS9LPRS365
+VDC
PG
15
+V3.3S
PG 6
Pineview
10.1' LED
LVDS
DDR2
DDR2 SODIMM0
+V3.3S
FCBGA 437PIN
667
667
PG 12
+VCC_CORE,+VCCP
+V0.9S,+V1.8,+V3.3S
+1.05V,+V0.89V,+V1.8V
PG 13
VGA
R/G/B
PG 7,8,9,10
+V5S
C
PG 11
SIM CARD
PG 20
DMI x2
Gen1
PCIE mini Card
PCIE mini Card
10/100M
PG 20
PG 19
LAN
PCIE X1
RTL8102E
RJ45
+V3.3AL,+V3.3S
PG 26
PCIE 1X
Tigerpoint
82801GBM 652 BGA
USB1.1/2.0
S-ATA
+V1.05S,+V3.3S
+V3.3AL,+V5AL
2.5" HHD
BIOS
Bluetooth
+V1.5S,+V5S
SATAO(R1.0)
+V5S,+V3.3S
B
8Mbit
+V3.3A_RTC
+V5AL
PG 17
+V3.3AL
PG 14,15,16
PG 25
USB PORT1
+V5AL
Speaker
AMP
HDA
L
USB PORT2
TPS6017A2
+V5AL
+V5S
PG 22
R
KB Matrix
KB Controller/EC
USB PORT3
KB3310B
MiC
+V5AL
+V3.3AL
PG 25
LED & TouchPAD
AZALIA
PG 22
ALC662
+V5S,+V3.3S
Audio Jack
CAM
+V5S
PG 22
BIOS
8Mbit
A
+V3.3AL
PG 18
PG 25
SD/MMC/MS/XD CARD
USB HUB
Touch Panel
+V5S

2

1

CONTENT

1

2 System Block & Sch Page

3 PWR Block & description

4 NOTE and Annotations

5 Sch Modify and history

6 CK-505M

7 Pineview Host/k/LVDS/DMI

8 Pineview DDR2

9 Pineview VGA/RVDS

10 Pineview Power

11 CTR CONN

12 LVDS Inverter CONN

13 DDRII SODIMM0

14 Tigerpoint (1of3)

15 Tigerpoint (2of3)

16 Tigerpoint (3of3)

17 SATA HDD

18 Card Reader

19 PCIE MINI SLOT 1

20 PCIE MINI SLOT 2

21 USB Port & FAN

22 Audio (ALC662)

23 LED

24 OTP

25 KBC(KB3310B)

26 LAN(RTL8101E)

27 ADAPTER IN

28 BATTERY JACK

29 V3.3AL/+V5AL POWER

30 DDR V1.8/+V0.9S POWER

31 V1.5S/+V1.05S POWER

32 Power Good Logic_OVP

33 V5S/V3.3S/V1.8S/V1.2 Power

34 VCORE POWER

35 Power Discharge Circuit

36 CHARGER

37 Power On Secquence & Reset M

38 Power ON/OFF

39 Touchpad Board

Title

& Reset M 38 Power ON/OFF 39 Touchpad Board Title TOPSTAR TECHNOLOGY TOPSTAR TECHNOLOGY TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Swain Xu(许沐锌)

Swain Xu(许沐锌)

Swain Xu(许沐锌)

Page Name

Page Name

Page Name

System Block & Index

System Block & Index

System Block & Index

Size

Size

Size

A3

A3

A3

Project Name

Project Name

Project Name

Rev

Rev

Rev

B

B B

X01

X01

X01

Date:

Date:

Date:

Tuesday, September 29, 2009

Tuesday, September 29, 2009

Tuesday, September 29, 2009

Sheet

Sheet

Sheet

2

2 2

of

of

of

39

39

39

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

D

C

consent of TOPSTAR the expressed written consent of TOPSTAR the expressed written consent of TOPSTAR D

B

A

5

4

3

2

1

5 4 3 2 1 X01 POWER BLOCK Ver:A D D Charger power Battery ISL6251
5
4
3
2
1
X01 POWER BLOCK Ver:A
D
D
Charger power
Battery
ISL6251
11V-12.6V
4A
Adapter
VCC_CORE
+VCC_CORE
Power
+VDC
19V 2.1A
TPS51218
1.1V(4A)
Switch
40W
C
C
Chipset Power
Always power
DDR Power
GFX Power
TPS51218
TPS51125
TPS51218
TPS51218
+V5AL,5A
+V1.05S,3.085A
+V1.8 (5.5A)
+V3.3AL,5A
Cam 0.5A
DMI(0.48A)
PLL(0.3A)
+0.89S ( 1.38A)
GFX
PCIE(1.6A)
VCC5refP 10mA
DDRAnalog(1.32A)
DDRIO(0.82A)
Disply(0.08A)
USB(3.5A)
GIO,DPLLetc(0.33A)
DDRII SODIMM0(1.3A)
Clock(0.5A)
TPT(0.995A)
TGP(0.43A)
B
B
MOSFET
LAN(0.2A)
Switch
EC,Audio(0.055A)
MOSFET
+V5S,1.5A
LDO
LDO
Switch
APL5331
APL5331
Audio etc (0.5A)
Cam 0.5A
FAN 0.3A
CRT ??
MOSFET
Switch
+V1.8S ( 0.5A)
+V1.5S (1.5A)
+V0.9S( 1A)
+V3.3S,4A
DMI SFR (0.1A)
CFUSFR (0.15A)
DDRII SODIMM0
LVD(0.06A)
LCDVDD 0.5A
ICH (0.85A)
HD(?)
A
A
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Page Name
Page Name
Page Name
PWR Block & description
PWR Block & description
PWR Block & description
Size
Size
Size
Project Name
Project Name
Project Name
Rev
Rev
Rev
A3
A3
A3
X01
X01
X01
B
B
B
Date:
Date:
Date:
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Sheet
Sheet
Sheet
3
3
3
of
of
of
39
39
39
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
1

D

C

B

A

5

4

3

2

1

Voltage Rails

+VDC

Primary DC system power supply (6V-9.5V)

+VBATTERY

Battery Power supply (6-8.4V)

+VCC_CORE

Core Voltage for CPU

+V1.05S

1.05V for Calistoga & ICH7M core / FSB VTT

+V1.8

1.8V power rail for DDR2

+V0.9S

0.9V DDR2 Termination voltage

+V3.3AL

3.3V always on power rail

+V5AL

5V for ICH7-M's VCC5 Refsus

+V3.3S

3.3V main power rail

+V5S

5V main power rail

+V0.89S

0.89V power rail for Pineview Graphics core

Board stack up description

I2C SMB Address

Device

Address

Hex

Master

Clock Generator

1101

001x

D2

ICH7-M

SO-DIMM0

1010

000x

A0

ICH7-M

CPU Thermal Sensor

1001

100x

98

KBC

Smart Battery

0001

011x

16

KBC

PCIE Slot

TBD

TBD

ICH7-M

Power States

Signal

SLP_S3#

SLP_S4#

SLP_S5#

+V*ALW

+V*

+V*S

Clock

S0(Full On)

HIGH

HIGH

HIGH

ON

ON

ON

ON

S3(STM)

HIGH

HIGH

ON

ON

LOW

OFF

OFF

S4(STD)

LOW

HIGH

ON

OFF

OFF

LOW

OFF

S5(SoftOff)

LOW

LOW

ON

OFF

OFF

OFF

LOW

D

ON OFF OFF LOW OFF S5(SoftOff) LOW LOW ON OFF OFF OFF LOW D C PCB

C

PCB Layers

Trace Impedence:55ohm +/-15%

Top(Signal1)

VCC 2

Signal 3

Signal4

Ground 5

Bottom(Signal6)

USB Table

USB Port#

Function Description

0

Standard USB2.0 Port

1

Standard USB2.0 Port

2

Standard USB2.0 Port

3

MINICARD_USB

4

CAM_USB

5

MINICARD_USB

6

CR_USB

7

NC

Wake up Events

LID switch from EC Power switch from EC

PCB Footprints

3 5 4 SOT23 SOT23_5 1 2 1 2 3
3 5
4
SOT23
SOT23_5
1
2
1
2
3

ns: Component marked "ns" is not stuff

1 2 1 2 3 ns: Component marked "ns" is not stuff 5 4 3 2

5

4

3

2

2 3 ns: Component marked "ns" is not stuff 5 4 3 2 B TOPSTAR TECHNOLOGY

B

3 ns: Component marked "ns" is not stuff 5 4 3 2 B TOPSTAR TECHNOLOGY TOPSTAR

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Swain Xu(许沐锌)

Swain Xu(许沐锌)

Swain Xu(许沐锌)

A

Page Name

Page Name

Page Name

NOTE

NOTE

NOTE

Size

Size

A3

A3

A3

Size

Project Name

Project Name

Project Name

X01

X01

X01

Rev

Rev

Rev

B

B

B

Date:

Date:

Date:

Tuesday, September 29, 2009

Tuesday, September 29, 2009

Tuesday, September 29, 2009

Sheet

Sheet

Sheet

4

4

4

of

of

of

39

39

39

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

1

5 4 3 2 1 Schematic modify Item and history: D D C C B
5
4
3
2
1
Schematic modify Item and history:
D
D
C
C
B
B
A
A
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Page Name
Page Name
Page Name
Sch Modify and history
Sch Modify and history
Sch Modify and history
Size
Size
Size
Project Name
Project Name
Project Name
Rev
Rev
Rev
A3
A3
A3
X01
X01
X01
B
B
B
Date:
Date:
Date:
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Sheet
Sheet
Sheet
5
5
5
of
of
of
39
39
39
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
1
5 4 3 2 1 +V3.3S 7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32 +V1.05S 7,10,15,16,20,21,28,29,31
5
4
3
2
1
+V3.3S
7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32
+V1.05S
7,10,15,16,20,21,28,29,31
U14
U14
ICS9LPRS365
ICS9LPRS365
+V3.3S
FB7
FB7
TSSOP64_0D5_6D1
TSSOP64_0D5_6D1
100ohm@100MHz,3A
100ohm@100MHz,3A
SMBUS ADD:1101 001X
FB0805
FB0805
2
VDD_PCI
+V3.3S_CK_VDD
1
2
9
48
VDD_48
IO_VOUT
16
VDD_PLL3
C117
C117
C116
C116
C118
C118
R385
R385
0
0
R0402
R0402
61
63
VDD_REF
SMB_DATA
SMB_DATA_S
13,16,17,18
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
R386
R386
0
0
R0402
R0402
64
SMB_CLK
SMB_CLK_S
13,16,17,18
C0402
C0402
C0402
C0402
C0402
C0402
39
VDD_SRC
D
55
D
VDD_CPU
+V3.3S_CK_VDD
R372R372
00
R0402R0402
38
SRC5/PCI_STOP#
PM_STP_PCI#
15
+VDDIO_CLK
R373
R373
0
0
R0402
R0402
12
37
VDD_IO
SRC5#/CPU_STOP#
PM_STP_CPU#
15
C98
C98
C103
C103
C92
C92
C93
C93
C97
C97
+VDDIO_CLK
20
VDD_PLL3_IO
10UF/6.3V,X5R
10UF/6.3V,X5R
4.7UF/10V,Y5V
4.7UF/10V,Y5V
0.047uF/16V,X7R
0.047uF/16V,X7R
0.047uF/16V,X7R
0.047uF/16V,X7R
0.1UF/25V,Y5V
0.1UF/25V,Y5V
+VDDIO_CLK
CPU0
26
54
VDD_SRC_IO_1
CPU0
CLK_CPU_BCLK
7
C0805
C0805
C0805
C0805
C0402
C0402
C0402
C0402
C0402
C0402
CPU#0
36
53
VDD_SRC_IO_2
CPU0#
CLK_CPU_BCLK#
7
45
VDD_SRC_IO_3
+VDDIO_CLK
CPU1
49
51
VDD_CPU_IO
CPU1
CLK_MCH_BCLK
9
CPU#1
50
CPU1#
CLK_MCH_BCLK#
9
1
PCI0/OE#_0/2_A
47
SRC8/CPU2_ITP
CLK_PCIE_EXPCARD2
18
3
46
PCI1/OE#_1/4_A SRC8#/CPU2#_ITP
CLK_PCIE_EXPCARD2#
18
+V3.3S
TME
4
34
PCI2/TME
SRC10
CLK_PCIE_EXPCARD
17
35
SRC10#
CLK_PCIE_EXPCARD#
17
R313
R313
22
22
R0402
R0402
5
22
PCI_CLK_EC
PCI3/FSD
MPCIE_CLKREQ
R375R375
475,1%475,1%
R0402R0402 nsns
33
SRC11/OE#_10
PCIE_CLKREQ#
17
FB8
FB8
R312R312
2222
R0402R0402
27M_SEL
MCH_CLKREQ
6
32
17 PCI_CLK_DEBUG
PCI4/SRC5_SEL
SRC11#/OE#_9
100ohm@100MHz,3A
100ohm@100MHz,3A
R311
R311
22
22
R0402
R0402
PCIF_ITP_EN
7
30
FB0805
FB0805
14
PCI_CLK_ICH
PCIF5/ITP_EN
SRC9
CLK_MCH_EXP
7
31
SRC9#
CLK_MCH_EXP#
7
CLK_XTAL_IN
60
XTAL_IN
+VDDIO_CLK
R299
R299
10K R0402
10K R0402
R380
R380
475,1%
475,1%
R0402 ns
R0402 ns
44
SRC7/OE#_8
PCIE_CLKREQ2#
18
C100
C100
C119
C119
Set to SRC8
CLK_XTAL_OUT
59
43
XTAL_OUT
SRC7#/OE#_6
C106
C106
10UF/6.3V,X5R
10UF/6.3V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
No more than 500 mil
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C0402
C0402
R316
R316
22
22
R0402
R0402
41
20
CR_USB48
SRC6
DREFSSCLK
9
C0805
C0805
R310R310
2222
R0402R0402
10
40
14
CLK_USB48
USB_48/FSA
SRC6#
DREFSSCLK#
9
+VDDIO_CLK
CLK_BSEL0
R304
R304
2.2K R0402
2.2K R0402
27
SRC4
CLK_PCIE_ICH
14
C
C99
C99
C120
C120
CLK_BSEL1
C
57
28
FSB/TEST_MODE
SRC4#
CLK_PCIE_ICH#
14
10UF/6.3V,X5R
10UF/6.3V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
CLK_BSEL2
R384
R384
10K R0402
10K R0402
62
REF0/FSC/TEST_SEL
C0805
C0805
C0402
C0402
24
SRC3/OE#_0/2_B
CLK_PCIE_LAN
23
R395R395
2222
R0402R0402
25
15
CLK_ICH14
SRC3#/OE#_1/4_B
CLK_PCIE_LAN#
23
8
21
VSS_PCI
SRC2/SATA
CLK_ICH_SATA
15
+VDDIO_CLK
11
22
VSS_48
SRC2#/SATA#
CLK_ICH_SATA#
15
C105
C105
C94
C94
C115
C115
C96
C96
15
VSS_IO
10UF/6.3V,X5R
10UF/6.3V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
19
17
VSS_PLL3
SRC1/SE1
CLK_PCIE_HD
14
C0805
C0805
C0402
C0402
C0402
C0402
C0402
C0402
52
18
VSS_CPU
SRC1#/SE2
CLK_PCIE_HD#
14
C303
C303
23
VSS_SRC_1
27pF/50V,NPO
27pF/50V,NPO
CLK_XTAL_IN
29
13
VSS_SRC_2
SRC0/DOT96
DREFCLK
9
C0402
C0402
58
14
Y6
Y6
VSS_REF
SRC0#/DOT96#
DREFCLK#
9
+VDDIO_CLK
42
VSS_SRC3
C104
C104
C95
C95
VR_CLK_EN
R512
R512
0
0
R0402
R0402
3
4
56
CK_PWRGD/PWRDWN#
CK505_CLK_EN#
15,32
10UF/6.3V,X5R
10UF/6.3V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
C0805
C0805
C0402
C0402
ns
ns
2
1
Remove all 4P2R resitor
许沐锌 090918
14.318MHz
14.318MHz
XS4_5032_0D8
XS4_5032_0D8
CLK_ICH14
C313
C313
10PF/50V,NPO
10PF/50V,NPO
ns
ns
C301
C301
C0402
C0402
27pF/50V,NPO
27pF/50V,NPO
CLK_XTAL_OUT
+V3.3S
CLK_USB48
C295
C295
10PF/50V,NPO
10PF/50V,NPO
ns
ns
C0402
C0402
C0402
C0402
PCI_CLK_DEBUG
C291
C291
10PF/50V,NPO
10PF/50V,NPO
ns
ns
C0402
C0402
update Y6 footprint
许沐锌 090917
R131
R131
PCI_CLK_EC
C292
C292
10PF/50V,NPO
10PF/50V,NPO
ns
ns
10K
10K
C0402
C0402
B
B
R0402
R0402
PCI_CLK_ICH
C294
C294
10PF/50V,NPO
10PF/50V,NPO
ns
ns
ns
ns
C0402
C0402
VR_CLK_EN
BUS FREQUENCE SELECT
R139
R139
Q2
Q2
1K
1K
2N7002
2N7002
+V1.05S
R0402
R0402
C129
C129
R130
R130
SOT23
SOT23
ns
ns
0.1uF/10V,X5R
0.1uF/10V,X5R
1
10K
10K
15,32
CK505_CLK_EN#
ns
ns
C0402
C0402
R0402
R0402
ns
ns
C293
C293
ns
ns
+V3.3S
R302
R302
R382
R382
R383
R383
0.1UF/25V,Y5V
0.1UF/25V,Y5V
56
56
1K
1K
1K
1K
C0402
C0402
R0402
R0402
R0402
R0402
R0402
R0402
ns
ns
ns
ns
ns
ns
MCH_CLKREQ
R315R315
10K10K
R0402R0402
R270R270
00
R0402R0402
CLK_BSEL0
R271R271
1K1K
R0402R0402
MPCIE_CLKREQ
R389R389
10K10K
R0402R0402
7
CPU_BSEL0
MCH_BSEL0
9
R275R275
00
R0402R0402
CLK_BSEL1
R272R272
1K1K
R0402R0402
7
CPU_BSEL1
MCH_BSEL1
9
+V3.3S
R274R274
00
R0402R0402
CLK_BSEL2
R273R273
1K1K
R0402R0402
TME
R314R314
10K10K
R0402R0402
7
CPU_BSEL2
MCH_BSEL2
9
0:Normal mode
1:No Overclocking
R303
R303
R381
R381
R392
R392
FSC
FSB
FSA
HOST Clock
R301
R301
+V1.05S
1K
1K
0
0
0
0
10K
10K
R0402
R0402
R0402
R0402
R0402
R0402
BSEL2
BSEL1
BSEL0
frequency
R0402
R0402
ns
ns
ns
ns
ns
ns
ns
ns
A
A
27M_SEL
C133
C133
0
1
1 166MHz
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Swain Xu(许沐锌)
0.1UF/25V,Y5V
0.1UF/25V,Y5V
0
0
1 133MHz
Page Name
Page Name
Page Name
C0402
C0402
CK505M
CK505M
CK505M
R300
R300
10K
10K
Size
Size
Size
Project Name
Project Name
Project Name
Rev
Rev
Rev
R0402
R0402
A3
A3
A3
1
0
1 100MHz
X01
X01
X01
B
B
B
Date:
Date:
Date:
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Sheet
Sheet
Sheet
6
6
6
of
of
of
39
39
39
EMI CAP
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
1
1
2
2
3
5 4 3 2 1 PINEVIEW_M PINEVIEW_M PINEVIEW_M PINEVIEW_M 6,10,15,16,20,21,28,29,31 +V1.05S +V3.3S U3D U3D U3A
5
4
3
2
1
PINEVIEW_M
PINEVIEW_M
PINEVIEW_M
PINEVIEW_M
6,10,15,16,20,21,28,29,31
+V1.05S
+V3.3S
U3D
U3D
U3A
U3A
? ?
? ?
REV = 1.1
REV = 1.1
REV = 1.1
REV = 1.1
U25
E7
12
LVD_A_CLK_DN
LVD_A_CLKM
SMI_B
H_SMI#
15
C22
C22
0.1uF/10V,X5R
0.1uF/10V,X5R
R28
R28
0
0
R0402
R0402
U26
H7
F3
G2
12
LVD_A_CLK_DP
LVD_A_CLKP
A20M_B
H_A20M#
15
14
DMI_TXP0
DMI_RXP_0
DMI_TXP_0
DMI_RXP0
14
+V3.3S
C21
C21
0.1uF/10V,X5R
0.1uF/10V,X5R
R29
R29
0
0
R0402
R0402
R23
H6
F2
G1
12
LVD_A_DATA0_DN
LVD_A_DATAM_0
FERR_B
H_FERR#
15
14
DMI_TXN0
DMI_RXN_0
DMI_TXN_0
DMI_RXN0
14
C28
C28
0.1uF/10V,X5R
0.1uF/10V,X5R
R39
R39
0
0
R0402
R0402
R24
F10
H4
H3
12
LVD_A_DATA0_DP
LVD_A_DATAP_0
LINT00
H_INTR
15
14
DMI_TXP1
DMI_RXP_1
DMI_TXP_1
DMI_RXP1
14
C26
C26
0.1uF/10V,X5R
0.1uF/10V,X5R
R45
R45
0
0
R0402
R0402
N26
F11
G3
J2
12
LVD_A_DATA1_DN
LVD_A_DATAM_1
LINT10
H_NMI
15
14
DMI_TXN1
DMI_RXN_1
DMI_TXN_1
DMI_RXN1
14
N27
E5
12
LVD_A_DATA1_DP
LVD_A_DATAP_1
IGNNE_B
H_IGNNE#
15
R258
R258
0
0
R0402
R0402
R26
F8
12
LVD_A_DATA2_DN
LVD_A_DATAM_2
STPCLK_B
H_STPCLK#
15
R37
R37
R50
R50
R27
12
LVD_A_DATA2_DP
LVD_A_DATAP_2
2.2K
2.2K
2.2K
2.2K
D
D
R0402
R0402
R0402
R0402
G6
DPRSTP_B
H_DPRSTP#
15
LCTLA_CLK
LVD_IBG
R22
G10
N7
L10
LVD_IBG
DPSLP_B
H_DPSLP#
15
6 CLK_MCH_EXP#
EXP_CLKINN
EXP_RCOMPO
LCTLA_DATA
J28
G8
N6
L9
LVD_VBG
INIT_B
H_INIT#
15
6
CLK_MCH_EXP
EXP_CLKINP
EXP_ICOMPI
LVD_VREFH_OUT_R
H_BPM4_PRDY#
N22
E11
L8
LVD_VREFH
PRDY_B
EXP_RBIAS
LVD_VREFL_OUT_R
H_BPM5_PRDQ#
N23
F15
R10
LVD_VREFL
PREQ_B
RSVD_R10
L27
R9
N11
12,22
LVDS_BKLTEN
LBKLT_EN
RSVD_R9
RSVD_TP_N11
L26
N10
P11
12
LBKLT_CTL
LBKLT_CTL
RSVD_N10
RSVD_TP_P11
LCTLA_CLK
R277
R277
R278
R278
L23
E13
N9
LCTLA_CLK
THERMTRIP_B
PM_THRMTRIP#
15,21
RSVD_N9
LCTLA_DATA
49.9,1%
49.9,1%
750
750
K25
LCTLB_CLK
K23
R0402
R0402
R0402
R0402
12
LDDC_CLK
LDDC_CLK
R245
R245
68
68
R0402 ns
R0402 ns
K24
+V1.05S
12
LDDC_DATA
LDDC_DATA
K2
K3
H26
RSVD_K2
RSVD_K3
12
LVDD_EN
LVDD_EN
J1
L2
R232
R232
0
0
R0402
R0402
VR_PROCHOT#
C18
RSVD_J1
RSVD_L2
PROCHOT_B
M4
M2
R62
R62
0
0
R0402
R0402
W1
RSVD_M4
RSVD_M2
CPUPWRGOOD
H_PWROK
15
L3
N2
RSVD_L3
RSVD_N2
NOTE
+V1.05S
PNV_22MM_REV1P10
PNV_22MM_REV1P10
Place Resistor close to PNV
GTLREF_EA
1
1
OF 6
OF 6
A13
GTLREF
PWROK 预留0 ohm
电阻,以备debug用
许沐锌
PNV_22MM_REV1P10
PNV_22MM_REV1P10
R55
R55
2.37K,1%
2.37K,1%
LVD_IBG
? ?
H27
VSS
R0402
R0402
R49
R49
0
0
R0402
R0402
LVD_VREFH_OUT_R
R56
R56
0
0
R0402
R0402
LVD_VREFL_OUT_R
L6
RSVD_L6
R498
R498
R499
R499
R500
R500
E17
RSVD_E17
+V1.05S
H_BPM_N0
470
470
470
470
470
470
G11
BPM_1B_0
+V1.05S
H_BPM_N1
R0402
R0402
R0402
R0402
R0402
R0402
Note:
E15
H10
BPM_1B_1
BCLKN
CLK_CPU_BCLK#
6
H_BPM_N2
Note:
G13
J10
BPM_1B_2
BCLKP
CLK_CPU_BCLK
6
H_BPM_N3
F13
BPM_1B_3
GTLREF MAX TRACE
length of 500 Mil
and 5 Mil spacing
CPU GTLREF need to be
2/3 of VCCP1 1.05V
please near GTLREF's pin
C
C
K5
BSEL_0
CPU_BSEL0
6
H_BPM2_N0
R253
R253
B18
H5
BPM_2_0#/RSVD
BSEL_1
CPU_BSEL1
6
H_BPM2_N1
R268
R268
1K,1%
1K,1%
B20
K6
BPM_2_1#/RSVD
BSEL_2
CPU_BSEL2
6
H_BPM2_N2
976,1%
976,1%
R0402
R0402
C20
BPM_2_2#/RSVD
H_BPM2_N3
T6T6
ICTPICTP
nsns
R0402
R0402
GTLREF_EA
B21
H30
BPM_2_3#/RSVD
VID_0
T5T5
ICTPICTP
nsns
EXTBGREF
H29
VID_1
T7T7
ICTPICTP
nsns
C221
C221
H28
VID_2
T4T4
ICTPICTP
nsns
C238
C238
C220
C220
C0402
C0402
R252
R252
G30
VID_3
CPU_RSVD
T3T3
ICTPICTP
nsns
C0402
C0402
R269
R269
C0402
C0402
2K,1%
2K,1%
G5
G29
RSVD_G5
VID_4
H_TDI
T2T2
ICTPICTP
nsns
3.32K,1%
3.32K,1%
R0402
R0402
D14
F29
TDI
VID_5
H_TDO
T1T1
ICTPICTP
nsns
D13
E29
R0402
R0402
TDO
VID_6
H_TCK
B14
TCK
H_TMS
C14
L7
TMS
RSVD_L7
H_TRST#
C16
D20
TRST_B
RSVD_D20
H13
RSVD_H13
D18
RSVD_D18
H_THERMDA
D30
THRMDA_1
H_THERMDC
E30
K9
THRMDC_1
RSVD_TP_K9
D19
RSVD_TP_D19
EXTBGREF
K7
EXTBGREF
+V1.05S
+V3.3S
R15
R15
R257R257
nsns5151
R0402R0402
H_BPM_N0
220
220
R249R249
nsns5151
R0402R0402
H_BPM_N1
R0402
R0402
R238R238
nsns5151
R0402R0402
H_BPM_N2
C30
RSVD_C30
R250R250
nsns5151
R0402R0402
H_BPM_N3
D31
RSVD_D31
R246R246
nsns5151
R0402R0402
H_BPM2_N0
C17
C17
R243R243
nsns5151
R0402R0402
H_BPM2_N1
0.1uF/10V,X5R
0.1uF/10V,X5R
B
B
R234R234
nsns5151
R0402R0402
H_BPM2_N2
4
4
OF 6
OF 6
C0402
C0402
R233R233
nsns5151
R0402R0402
H_BPM2_N3
? ?
R255R255
nsns5151
R0402R0402
H_BPM4_PRDY#
H_THERMDA
R244R244
5151
R0402R0402
H_BPM5_PRDQ#
EC SMBUS ADD:1001 100X
R266R266
6262
R0603R0603
CPU_RSVD
C20
C20
8
2 DXP
SMBCLK
I2C_CLK
22
R236R236
5151
R0402R0402
H_TDI
2200pF/25V,X7R
2200pF/25V,X7R
R248R248
5151
R0402R0402
H_TMS
C0402
C0402
7
3 DXN
SMBDATA
I2C_DATA
22
R254R254
5151
R0402R0402
H_TDO
H_THERMDC
G781
G781
ADM1032AR
ADM1032AR
6
ALERT#
OVT_SHUTDOWN#
21
LM86CIM
LM86CIM
MAX6657MSA
MAX6657MSA
THERM#
R27
R27
0
0
R0402
R0402
4
THERM#
PM_THRM#
15
SOIC-8
SOIC-8
ns
ns
C18
C18
C19
C19
R251R251
5151
R0402R0402
H_TCK
U2
U2
R31
R31
R26
R26
27pF/50V,NPO
27pF/50V,NPO
27pF/50V,NPO
27pF/50V,NPO
R247R247
5151
R0402R0402
H_TRST#
F75393S
F75393S
10K
10K
10K
10K
C0402
C0402
C0402
C0402
SO8_50_150
SO8_50_150
R0402
R0402
R0402
R0402
NOTE
+V3.3S
1.H_THERMDA/C线宽10 MILS,并配对走线,
然后再包地处理.
+V3.3S
R229
R229
10K
10K
2.H_THERMDA/C走线远离19V及VGA或高速线走线
R0402
R0402
EC_PROCHOT#
22
A
A
+V1.05S
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
R241
R241
Q16
Q16
R235
R235
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Swain Xu(许沐锌)
1K
1K
MMBT3904-F
MMBT3904-F
1K
1K
R0402
R0402
Q15
Q15
SOT23
SOT23
R0402
R0402
Page Name
Page Name
Page Name
Diamondville(1of2)(Host BUS)
Diamondville(1of2)(Host BUS)
Diamondville(1of2)(Host BUS)
MMBT3904-F
MMBT3904-F
R230
R230
1
1
+V1.05S
+V1.05S
SOT23
SOT23
Size
Size
Size
1K
1K
Project Name
Project Name
Project Name
Rev
Rev
Rev
A3
A3
A3
X01
X01
X01
R0402
R0402
B
B
B
VR_PROCHOT#
Date:
Date:
Date:
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Sheet
Sheet
Sheet
7
7
7
of
of
of
39
39
39
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
1
2
3
LVDS
LVDS
CPU
CPU
ICH
ICH
23
1
VCC
5
GND
1uF/10V,Y5V
1uF/10V,Y5V
DMI
DMI
220pF/50V,X7R
220pF/50V,X7R
1uF/10V,Y5V
1uF/10V,Y5V

6,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32

5 4 3 2 1 +V1.8 10,13,27,28,29,30,31 13 MA_DATA[63:0] 13 MA_DQS#[7:0] 13 MA_DQS[7:0] D D
5
4
3
2
1
+V1.8
10,13,27,28,29,30,31
13
MA_DATA[63:0]
13
MA_DQS#[7:0]
13
MA_DQS[7:0]
D
D
13
MA_DM[7:0]
U3B
U3B
PNV_22MM_REV1P10
PNV_22MM_REV1P10
REV = 1.1
REV = 1.1
2
2
OF 6
OF 6
?
?
?
?
C
C
+V1.8
DDR_RPD
R82
R82
80.6,1%
80.6,1%
R0402
R0402
10K
10K
R71
R71
R0402
R0402
+V1.8
R69
R69
0
0
R0402
R0402
Add R915 10K Follow CRB 1.0
许沐锌 090602
DDR_RPU
R81
R81
80.6,1%
80.6,1%
ns
ns
R0402
R0402
C270
C270
0.1UF/25V,Y5V
0.1UF/25V,Y5V
13
MA_A_A[14:0]
C0402
C0402
M_CLK_DDR#1
13
+V1.8
M_CLK_DDR1
13
M_CLK_DDR#0
13
B
B
M_CLK_DDR0
13
M_ODT1
13
Note:
M_ODT0
13
COLSE TO MCH PIN ON MCH_VREF
R84
R84
1K,1%
1K,1%
M_CKE1
13
R0402
R0402
M_CKE0
13
DDR_VREF
M_CS#1
13
M_CS#0
13
R83
R83
MA_A_BS#2
13
C65
C65
1K,1%
1K,1%
MA_A_BS#1
13
0.1UF/25V,Y5V
0.1UF/25V,Y5V
R0402
R0402
MA_A_BS#0
13
C0402
C0402
MA_A_CAS#
MA_A_RAS#
13
13
MA_A_WE#
13
A
A
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Page Name
Page Name
Page Name
Diamondville (PWR&GND)(2of2)
Diamondville (PWR&GND)(2of2)
Diamondville (PWR&GND)(2of2)
Size
Size
Size
Project Name
Project Name
Project Name
Rev
Rev
Rev
A3
A3
A3
X01
X01
X01
B
B
B
Date:
Date:
Date:
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Sheet
Sheet
Sheet
8
8
8
of
of
of
39
39
39
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
1
PINEVIEW_M
PINEVIEW_M
MA_DQS0
AD3
DDR_A_DQS_0
MA_A_A0
MA_DQS#0
AH19
AD2
DDR_A_MA_0
DDR_A_DQSB_0
MA_A_A1
MA_DM0
AJ18
AD4
DDR_A_MA_1
DDR_A_DM_0
MA_A_A2
AK18
DDR_A_MA_2
MA_A_A3
MA_DATA0
AK16
AC4
DDR_A_MA_3
DDR_A_DQ_0
MA_A_A4
MA_DATA1
AJ14
AC1
DDR_A_MA_4
DDR_A_DQ_1
MA_A_A5
MA_DATA2
AH14
AF4
DDR_A_MA_5
DDR_A_DQ_2
MA_A_A6
MA_DATA3
AK14
AG2
DDR_A_MA_6
DDR_A_DQ_3
MA_A_A7
MA_DATA4
AJ12
AB2
DDR_A_MA_7
DDR_A_DQ_4
MA_A_A8
MA_DATA5
AH13
AB3
DDR_A_MA_8
DDR_A_DQ_5
MA_A_A9
MA_DATA6
AK12
AE2
DDR_A_MA_9
DDR_A_DQ_6
MA_A_A10
MA_DATA7
AK20
AE3
DDR_A_MA_10
DDR_A_DQ_7
MA_A_A11
AH12
DDR_A_MA_11
MA_A_A12
MA_DQS1
AJ11
AB8
DDR_A_MA_12
DDR_A_DQS_1
MA_A_A13
MA_DQS#1
AJ24
AD7
DDR_A_MA_13
DDR_A_DQSB_1
MA_A_A14
MA_DM1
AJ10
AA9
DDR_A_MA_14
DDR_A_DM_1
MA_DATA8
AB6
DDR_A_DQ_8
MA_DATA9
AK22
AB7
DDR_A_WEB
DDR_A_DQ_9
MA_DATA10
AJ22
AE5
DDR_A_CASB
DDR_A_DQ_10
MA_DATA11
AK21
AG5
DDR_A_RASB
DDR_A_DQ_11
MA_DATA12
AA5
DDR_A_DQ_12
MA_DATA13
AJ20
AB5
DDR_A_BS_0
DDR_A_DQ_13
MA_DATA14
AH20
AB9
DDR_A_BS_1
DDR_A_DQ_14
MA_DATA15
AK11
AD6
DDR_A_BS_2
DDR_A_DQ_15
MA_DQS2
AD8
DDR_A_DQS_2
MA_DQS#2
AD10
DDR_A_DQSB_2
MA_DM2
AH22
AE8
DDR_A_CSB_0
DDR_A_DM_2
AK25
DDR_A_CSB_1
MA_DATA16
AJ21
AG8
DDR_A_CSB_2
DDR_A_DQ_16
MA_DATA17
AJ25
AG7
DDR_A_CSB_3
DDR_A_DQ_17
MA_DATA18
AF10
DDR_A_DQ_18
MA_DATA19
AH10
AG11
DDR_A_CKE_0
DDR_A_DQ_19
MA_DATA20
AH9
AF7
DDR_A_CKE_1
DDR_A_DQ_20
MA_DATA21
AK10
AF8
DDR_A_CKE_2
DDR_A_DQ_21
MA_DATA22
AJ8
AD11
DDR_A_CKE_3
DDR_A_DQ_22
MA_DATA23
AE10
DDR_A_DQ_23
AK24
DDR_A_ODT_0
MA_DQS3
AH26
AK5
DDR_A_ODT_1
DDR_A_DQS_3
MA_DQS#3
AH24
AK3
DDR_A_ODT_2
DDR_A_DQSB_3
MA_DM3
AK27
AJ3
DDR_A_ODT_3
DDR_A_DM_3
MA_DATA24
AH1
DDR_A_DQ_24
MA_DATA25
AJ2
DDR_A_DQ_25
MA_DATA26
AG15
AK6
DDR_A_CK_0
DDR_A_DQ_26
MA_DATA27
AF15
AJ7
DDR_A_CKB_0
DDR_A_DQ_27
MA_DATA28
AD13
AF3
DDR_A_CK_1
DDR_A_DQ_28
MA_DATA29
AC13
AH2
DDR_A_CKB_1
DDR_A_DQ_29
MA_DATA30
AL5
DDR_A_DQ_30
MA_DATA31
AJ6
DDR_A_DQ_31
AC15
DDR_A_CK_3
MA_DQS4
AD15
AG22
DDR_A_CKB_3
DDR_A_DQS_4
MA_DQS#4
AF13
AG21
DDR_A_CK_4
DDR_A_DQSB_4
MA_DM4
AG13
AD19
DDR_A_CKB_4
DDR_A_DM_4
MA_DATA32
AE19
DDR_A_DQ_32
MA_DATA33
AG19
DDR_A_DQ_33
MA_DATA34
AD17
AF22
RSVD_AD17
DDR_A_DQ_34
MA_DATA35
AC17
AD22
RSVD_AC17
DDR_A_DQ_35
MA_DATA36
AB15
AG17
RSVD_AB15
DDR_A_DQ_36
MA_DATA37
AB17
AF19
RSVD_AB17
DDR_A_DQ_37
MA_DATA38
AE21
DDR_A_DQ_38
MA_DATA39
AD21
DDR_A_DQ_39
MA_DQS5
AE26
DDR_A_DQS_5
MA_DQS#5
AG27
DDR_A_DQSB_5
MA_DM5
AB4
AJ27
VSS
DDR_A_DM_5
AK8
RSVD_AK8
MA_DATA40
AE24
DDR_A_DQ_40
MA_DATA41
AG25
DDR_A_DQ_41
MA_DATA42
AD25
DDR_A_DQ_42
MA_DATA43
AB11
AD24
RSVD_TP_AB11
DDR_A_DQ_43
MA_DATA44
AB13
AC22
RSVD_TP_AB13
DDR_A_DQ_44
MA_DATA45
AG24
DDR_A_DQ_45
DDR_VREF
MA_DATA46
AL28
AD27
DDR_VREF
DDR_A_DQ_46
DDR_RPD
MA_DATA47
AK28
AE27
DDR_RPD
DDR_A_DQ_47
DDR_RPU
AJ26
DDR_RPU
MA_DQS6
AE30
DDR_A_DQS_6
MA_DQS#6
AK29
AF29
RSVD_AK29
DDR_A_DQSB_6
MA_DM6
AF30
DDR_A_DM_6
MA_DATA48
AG31
DDR_A_DQ_48
MA_DATA49
AG30
DDR_A
DDR_A
DDR_A_DQ_49
MA_DATA50
AD30
DDR_A_DQ_50
MA_DATA51
AD29
DDR_A_DQ_51
MA_DATA52
AJ30
DDR_A_DQ_52
MA_DATA53
AJ29
DDR_A_DQ_53
MA_DATA54
AE29
DDR_A_DQ_54
MA_DATA55
AD28
DDR_A_DQ_55
MA_DQS7
AB27
DDR_A_DQS_7
MA_DQS#7
AA27
DDR_A_DQSB_7
MA_DM7
AB26
DDR_A_DM_7
MA_DATA56
AA24
DDR_A_DQ_56
MA_DATA57
AB25
DDR_A_DQ_57
MA_DATA58
W24
DDR_A_DQ_58
MA_DATA59
W22
DDR_A_DQ_59
MA_DATA60
AB24
DDR_A_DQ_60
MA_DATA61
AB23
DDR_A_DQ_61
MA_DATA62
AA23
DDR_A_DQ_62
MA_DATA63
W27
DDR_A_DQ_63

5

4

3

2

1

+V3.3S 6,7,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32 Note: PINEVIEW_M PINEVIEW_M U3C U3C ? ?
+V3.3S
6,7,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32
Note:
PINEVIEW_M
PINEVIEW_M
U3C
U3C
? ?
HSYNC/VSYNC: Locate series
esistor strsps within 750 mil of MCH
REV = 1.1
REV = 1.1
D12
6
MCH_BSEL0
XDP_RSVD_00
R0402R0402
1010
R42R42
A7
M30
CRT_HSYNC
11
6
MCH_BSEL1
XDP_RSVD_01
CRT_HSYNC
R0402R0402
1010
R41R41
D6
M29
CRT_VSYNC
11
6
MCH_BSEL2
XDP_RSVD_02
CRT_VSYNC
C5
XDP_RSVD_03
D
D
C7
XDP_RSVD_04
XDP_RSVD_5
C6
N31
XDP_RSVD_05
CRT_RED
CRT_RED
11
+V3.3S
D8
P30
XDP_RSVD_06
CRT_GREEN
CRT_GREEN
11
B7
P29
XDP_RSVD_07
CRT_BLUE
CRT_BLUE
11
A9
N30
XDP_RSVD_08
CRT_IRTN
XDP_RSVD_9
D9
XDP_RSVD_09
R30R30
10K10K R0402R0402
PM_EXTTS0#
C8
XDP_RSVD_10
XDP_RSVD_11
B8
XDP_RSVD_11
R70 为T 物料, 需要修改
许沐锌 090513
C10
L31
XDP_RSVD_12
CRT_DDC_DATA
CRT_DDC_DATA
11
D10
L30
XDP_RSVD_13
CRT_DDC_CLK
CRT_DDC_CLK
11
B11
XDP_RSVD_14
DACREFSET
R70R70
665,1%665,1%R0402R0402
B10
P28
XDP_RSVD_15
DAC_IREF
+V3.3S
B12
XDP_RSVD_16
update R70 to R0402
许沐锌 0900917
XDP_RSVD_17
C11
Y30
XDP_RSVD_17
DPL_REFCLKINP
DREFCLK
6
Y29
DPL_REFCLKINN
DREFCLK#
6
AA30
DPL_REFSSCLKINP
DREFSSCLK
6
AA31
DPL_REFSSCLKINN
DREFSSCLK#
6
R35
R35
R36
R36
2.2K
2.2K
2.2K
2.2K
L11
RSVD_L11
R0402
R0402
R0402
R0402
CRT_DDC_DATA
3
3
OF 6
OF 6
R33R33
00
R0402R0402
K29
注意这一点的命名
PNV_22MM_REV1P10
PNV_22MM_REV1P10
PM_EXTTS#_1/DPRSLPVR
PM_DPRSLPVR
15
? ?
CRT_DDC_CLK
J30
C
PM_EXTTS#_0
PM_EXTTS0#
13
许沐锌 090514
C
R51R51
00
R0402R0402
L5
PWROK
IMVP_PWRGD
15,22,32
R64R64
00
R0402R0402
AA3
RSTINB
BUF_PLT_RST#
14,15,17,18,22,23
W8
HPL_CLKINN
CLK_MCH_BCLK#
6
W9
HPL_CLKINP
CLK_MCH_BCLK
6
AA7
RSVD_TP_AA7
AA6
RSVD_TP_AA6
R54
R54
150,1%
150,1%
R0402
R0402
CRT_BLUE
R5
RSVD_TP_R5
R6
RSVD_TP_R6
R60R60
150,1%150,1%
R0402R0402
CRT_GREEN
AA21
RSVD_TP_AA21
R48R48
150,1%150,1%
R0402R0402
CRT_RED
W21
RSVD_TP_W21
T21
RSVD_TP_T21
V21
150ohm电阻到GMCH
RSVD_TP_V21
走线阻抗37.5ohm
R240R240
1K,1%1K,1% R0402R0402 nsns XDP_RSVD_5
150ohm电阻到VGA口
R256R256
1K,1%1K,1% R0402R0402
XDP_RSVD_9
走线阻抗50ohm
R239R239
1K,1%1K,1% R0402R0402 nsns XDP_RSVD_11
B
B
R237R237
1K,1%1K,1% R0402R0402 nsns XDP_RSVD_17
PLACE 150 OHM
RESISTORS CLOSE TO
GMCH
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Swain Xu(许沐锌)
A
A
Page Name
Page Name
Page Name
Calistoga(HOST)
Calistoga(HOST)
Calistoga(HOST)
Size
Size
Size
Project Name
Project Name
Project Name
Rev
Rev
Rev
B
B
B
X01
X01
X01
B
B
B
Date:
Date:
Date:
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Sheet
Sheet
Sheet
9
9
9
of
of
of
39
39
39
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
1
MISC
MISC
VGA
VGA

7

4

3

6

8

5

9

2

1

3
4

6
7

8

5

9

1
2

GND

GND

4

7

3

6

8

9

5

2

1

3
4

6
7

8

9

5

1
2

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,Y5V

1uF/10V,Y5V

1uF/10V,Y5V

1uF/10V,Y5V

5

4

3

2

1

D

C

1uF/10V,Y5V 1uF/10V,Y5V 1uF/10V,Y5V 5 4 3 2 1 D C B A D C B A

B

A

D

C

1uF/10V,Y5V 1uF/10V,Y5V 1uF/10V,Y5V 5 4 3 2 1 D C B A D C B A

B

A

U3F

U3F

PINEVIEW_M

PINEVIEW_M

?

?

+V3.3S

6,7,9,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32

A4

VSS

VSS

VSS

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

RSVD_NCTF

VSS

VSS

RSVD_NCTF

RSVD_NCTF

VSS

RSVD_NCTF

RSVD_NCTF

VSS

VSS

RSVD_NCTF

VSS

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

VSS

VSS

VSS

VSS

VSS

RSVD_NCTF

RSVD_NCTF

VSS

VSS

RSVD_NCTF

VSS

VSS

VSS

VSS

RSVD_NCTF

VSS

RSVD_NCTF

VSS

VSS

VSS

VSS

VSS

VSS

VSS

PNV_22MM_REV1P10

PNV_22MM_REV1P10

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

M3

+V0.89S

+VCC_CORE

REV = 1.1

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

REV = 1.1

F24

U3E U3E ? ? +V1.8 8,13,27,28,29,30,31 PINEVIEW_M PINEVIEW_M +V1.05S 6,7,15,16,20,21,28,29,31 REV = 1.1 REV =
U3E
U3E
? ?
+V1.8
8,13,27,28,29,30,31
PINEVIEW_M
PINEVIEW_M
+V1.05S
6,7,15,16,20,21,28,29,31
REV = 1.1
REV = 1.1
A23
VCC
+V1.5S
14,16,17,18,28,29,31
+V0.89S
A25
VCC
+VCC_CORE
29,32
C247
C247
C257
C257
C246
C246
C248
C248
C256
C256
A27
4A
VCC
+V0.89S
28,31
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
B23
VCC
+V1.8S
14,30
T13
B24
VCCGFX
VCC
1.38A
T14
B25
VCCGFX
VCC
T16
B26
VCCGFX
VCC
T18
B27
VCCGFX
VCC
T19
C24
VCCGFX
VCC
+V0.89S
V13
C26
VCCGFX
VCC
V19
D23
VCCGFX
VCC
W14
D24
VCCGFX
VCC
+VCC_CORE
W16
D26
VCCGFX
VCC
W18
D28
VCCGFX
VCC
C250
C250
C254
C254
C255
C255
W19
E22
VCCGFX
VCC
C0402
C0402
C0402
C0402
E24
VCC
C0603
C0603
C234
C234
C231
C231
C230
C230
C240
C240
C364
C364
C363
C363
E27
VCC
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0805
C0805
C0805
C0805
F21
VCC
F22
VCC
F25
VCC
G19
VCC
G21
VCC
G24
VCC
H17
VCC
H19
VCC
+V1.8
H22
VCC
5
5
OF 6
OF 6
H24
PNV_22MM_REV1P10
PNV_22MM_REV1P10
VCC
C271
C271
C276
C276
C269
C269
C277
C277
C275
C275
? ?
J17
VCC
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
AK13
J19
Totol:
VCCSM
VCC
ns
ns
AK19
J21
VCCSM
VCC
AK9
J22
+VCC_CORE: 4A
VCCSM
VCC
AL11
K15
VCCSM
VCC
AL16
K17
VCCSM
VCC
AL21
K21
VCCSM
VCC
AL25
L14
VCCSM
VCC
L16
VCC
+V0.89S : 1.38A
+V1.05S: 2.2A
+V1.5S: 0.15A
L19
VCC
+V1.8共2.3A
L21
+V1.8:
2.3A
VCC
+V1.8
N14
VCC
N16
+V1.8S: 0.3A
VCC
R283R28300
R0805R0805
AK7
N19
VCCCK_DDR
VCC
AL7
N21
VCCCK_DDR
VCC
C272
C272
C274
C274
C0805
C0805
C0402
C0402
U10
VCCA_DDR
ns
ns
U5
VCCA_DDR
U6
VCCA_DDR
U7
Layout Note: VCCSENSE
and VSSSENSE lines
should be of equal
length
VCCA_DDR
U8
VCCA_DDR
U9
VCCA_DDR
C229
C229
C242
C242
C153
C153
V2
VCCA_DDR
C0805
C0805
C0805
C0805
C0805
C0805
C253
C253
V3
VCCA_DDR
Route VCCSENSE and VSSSENSE
traces at 27.4 Ohms with 50
mil spacing
C0402
C0402
V4
VCCA_DDR
+VCC_CORE
W10
VCCA_DDR
W11
VCCA_DDR
+V1.05S
R16
R16
100,1%R0402
100,1%R0402
C29
VCCSENSE
1.4A
R18
R18
100,1%
100,1%
R0402
R0402
AA10
B29
0.08A
VCCACK_DDR
VSSSENSE
R65
R65
AA11
Y2
VCCACK_DDR
VCCA
+V1.05S
C43
C43
0.01uF/16V,X7R
0.01uF/16V,X7R
C228
C228
C244
C244
D4
VCC
C0402
C0402
C0402
C0402
C0402
C0402
R280
R280
B4
VCCP
0
0
ns
ns
ns
ns
B3
VCCP
R0402
R0402
AA19
VCCD_AB_DPL
V11
VCCD_HMPLL
+V1.8S
FB6
FB6
R75R75
00
R0805R0805
0.06A
C37
C37
C38
C38
AC31
VCCSFR_AB_DPL
C0402
C0402
C0402
C0402
V30
1
2
VCCALVD
C54
C54
1uF/10V,X5R
1uF/10V,X5R
C56
C56
1uF/10V,X5R
1uF/10V,X5R
ns
ns
W31
+V1.8S
VCCDLVD
+V1.8S
C0402
C0402
C0402
C0402
C47
C47
C51
C51
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
L1
L1
C0805
C0805
C0402
C0402
FB0805
FB0805
ns
ns
1
2
T30
VCCACRTDAC
10uF/6.3V,X5R
10uF/6.3V,X5R
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
C41
C41
1uF/10V,X5R
1uF/10V,X5R
+V3.3S
FB0805
FB0805
C0402
C0402
VCCA_DMI
T31
T1
VCC_GIO
VCCA_DMI
J31
T2
0.48A
VCCRING_EAST
VCCA_DMI
+V1.05S
C3
T3
VCCRING_WEST
VCCA_DMI
+V1.05S
0.35A
B2
VCCRING_WEST
T8T8
ICTPICTP
nsns
C2
P2
VCCRING_WEST
RSVD
A21
AA1
+V1.8S
VCC_LGI_VID
VCCSFR_DMIHMPLL
C48
C48
E2
+V1.05S
0.104A
VCCP
C243
C243
C233
C233
C263
C263
C249
C249
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
Demo 1.0版把P2pin 变成NC
许沐锌 090605
1uF/10V,X5R
1uF/10V,X5R
4.7uF/10V,X5R
4.7uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
2.2UF/10V,X5R
2.2UF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
10uF/6.3V,X5R
10uF/6.3V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
10uF/6.3V,X5R
10uF/6.3V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
10uF/6.3V,X5R
10uF/6.3V,X5R
1uF/10V,X5R
1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
GFX/MCH
GFX/MCH
DDR
DDR
EXP\CRT\PLL
EXP\CRT\PLL
POWER
POWER
DMI
DMI
LVDS
LVDS
CPU
CPU
1uF/10V,Y5V
1uF/10V,Y5V
1uF/10V,Y5V
1uF/10V,Y5V
1uF/10V,Y5V
1uF/10V,Y5V
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,Y5V
1uF/10V,Y5V
10uF/6.3V,X5R
10uF/6.3V,X5R
10uF/6.3V,X5R
10uF/6.3V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R
1uF/10V,X5R

+V1.8

+V1.05S

+V1.8S

0

0

R58

VCCA_DMI R58

A11

A16

A19

A29

A3

A30

AA13

AA14

AA16

AA18

AA2

AA22

AA25

AA26

AA29

AA8

AB19

AB21

AB28

AB29

AB30

AC10

AC11

AC19

AC2

AC21

AC28

AC30

AD26

AD5

AE1

AE11

AE13

AE15

AE17

AE22

AE31

AF11

AF17

AF21

AF24

AF28

AG10

AG3

AH18

AH23

AH28

AH4

AH6

AH8

AJ1

AJ16

AJ31

AK1

AK2

AK23

AK30

AK31

AL13

AL19

AL2

AL23

AL29

AL3

AL30

AL9

B13

B16

B19

B22

B30

B31

B5

B9

C1

C12

C21

C22

C25

C31

D22

E1

E10

E19

E21

E25

E8

F17

F19

F28

F4

G15

G17

G22

G27

G31

H11

H15

H2

H21

H25

H8

J11

J13

J15

J4

K11

K13

K19

K26

K27

K28

K30

K4

K8

L1

L13

L18

L22

L24

L25

L29

M28

N1

N13

N18

N24

N25

N28

N5

N4

N8

P13

P14

P16

P18

P19

P21

P3

P4

R25

R7

R8

T11

U22

U23

U24

U27

V14

V16

V18

V28

V29

W13

W2

W23

W25

W26

W28

W30

W4

W5

W6

W7

Y28

Y4

Y3

T29

6 6

HCPU1

HCPU1

CPU_HOLE

CPU_HOLE

ns

ns

OF 6

OF 6

? ?

HCPU2

HCPU2

CPU_HOLE

CPU_HOLE

ns

ns

+V1.5S

R0402

R0402

+V1.05S

0

0

R0603

R0603

CPU_HOLE ns ns +V1.5S R0402 R0402 +V1.05S 0 0 R0603 R0603 TOPSTAR TECHNOLOGY TOPSTAR TECHNOLOGY TOPSTAR

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Swain Xu(许沐锌)

Swain Xu(许沐锌)

Swain Xu(许沐锌)

Page Name

Page Name

Page Name

Calistoga(Graphic)

Calistoga(Graphic)

Calistoga(Graphic)

Size

Size

Size

A3

A3

A3

Project Name

Project Name

Project Name

X01

X01

X01

Rev

Rev

Rev

B B

B

Date:

Date:

Date:

Tuesday, September 29, 2009

Tuesday, September 29, 2009

Tuesday, September 29, 2009

Sheet

Sheet

Sheet

10 10

10

of

of

of

39

39

39

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

1

5 4 3 2 1 12,14,16,19,20,22,28,30,31,32 +V5S 6,7,9,10,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32
5
4
3
2
1
12,14,16,19,20,22,28,30,31,32
+V5S
6,7,9,10,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32
+V3.3S
Cross moat place
D
D
Cross moat
+V5S
+V5_VGA
place
D3
D3
FB2
FB2
1
2
1
2
GND_VGA
+V3.3S
+V3.3S
1N5819HW-F
1N5819HW-F
120ohm@100MHz,500mA
120ohm@100MHz,500mA
FB5
FB5
SOD123
SOD123
FB0603
FB0603
C258
C258
R264
R264
47ohm@100MHz,500mA
47ohm@100MHz,500mA
0.1uF/10V,X5R
0.1uF/10V,X5R
100K
100K
C0402
C0402
R0402
R0402
VGA
VGA
FB0603
FB0603
ROUT
VGADMF
VGADMF
R276
R276
R265
R265
1
2
9
CRT_RED
CONNECTOR TOP VIEW
1K
1K
1K
1K
Update FB2 to 500mA
许沐锌 090713
GND_VGA
GND
GND
R0402
R0402
R0402
R0402
6
R63
R63
D8
D8
ROUT
GND_VGA
NC
NC
ns
ns
ns
ns
1
R
R
11
C44
C44
C45
C45
150,1%
150,1%
BAT54S
BAT54S
7
GND
GND
5.6pF/50V NPO
5.6pF/50V NPO
5.6pF/50V NPO
5.6pF/50V NPO
R0402
R0402
SOT23
SOT23
GOUT
SDA
SDA
5VDDCDA
2
G
G
12
C0402
C0402
C0402
C0402
8
GND
GND
BOUT
3
B
B
HSYNC
HSYNC
CRT_HSYNC
13
CRT_HSYNC
9
FB4
FB4
9
NC
NC
47ohm@100MHz,500mA
47ohm@100MHz,500mA
GND_VGA
NC
VSYNC
VSYNC
CRT_VSYNC
4
NC
14
CRT_VSYNC
9
GND_VGA
+V3.3S
FB0603
FB0603
10
GND
GND
GOUT
GND
GND
CLK
CLK
5VDDCCK
1
2
5
15
9
CRT_GREEN
shell
shell
shell shell
R47
R47
C29
C29
C30
C30
150,1%
150,1%
D7
D7
C10518-11505-L
C10518-11505-L
C252
C252
C239
C239
C235
C235
C227
C227
5.6pF/50V NPO
5.6pF/50V NPO
5.6pF/50V NPO
5.6pF/50V NPO
R0402
R0402
BAT54S
BAT54S
15PF/50V,NPO
15PF/50V,NPO
15PF/50V,NPO
15PF/50V,NPO
15PF/50V,NPO
15PF/50V,NPO
15PF/50V,NPO
15PF/50V,NPO
C0402
C0402
C0402
C0402
SOT23
SOT23
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C
ns
ns
ns
ns
C
FB3
FB3
GND_VGA
47ohm@100MHz,500mA
47ohm@100MHz,500mA
GND_VGA
+V3.3S
GND_VGA
FB0603
FB0603
BOUT
VGA 公用M12,S46 connector
许沐锌 090713
GND_VGA
1
2
9
CRT_BLUE
R32
R32
No external level shifter for HSync & VSync at PINEVIEW
许沐锌 090605
C24
C24
C25
C25
150,1%
150,1%
D4
D4
5.6pF/50V NPO
5.6pF/50V NPO
5.6pF/50V NPO
5.6pF/50V NPO
R0402
R0402
BAT54S
BAT54S
C0402
C0402
C0402
C0402
SOT23
SOT23
150ohm电阻前
GND_VGA
+V3.3S
+V3.3S
+V5_VGA
走线阻抗50ohm
GND_VGA
R267
R267
R263
R263
2.2K
2.2K
Q17
Q17
2.2K
2.2K
R0402
R0402
BSS138
BSS138
R0402
R0402
5VDDCCK
2
3
9 CRT_DDC_CLK
+V3.3S
D26
D26
+V3.3S
+V3.3S
+V3.3S
+V5_VGA
BAT54S
BAT54S
B
B
SOT23
SOT23
D28
D28
D27
D27
2
C241
C241
R281
R281
R282
R282
2
CRT_HSYNC
0.1uF/10V,X5R
0.1uF/10V,X5R
2.2K
2.2K
Q18
Q18
2.2K
2.2K
+V5_VGA
3
C0402
C0402
CRT_VSYNC
C237
C237
R0402
R0402
BSS138
BSS138
R0402
R0402
GND_VGA
3
0.1uF/10V,X5R
0.1uF/10V,X5R
1
C0402
C0402
5VDDCDA
1
2
3
9 CRT_DDC_DATA
BAT54S
BAT54S
SOT23
SOT23
GND_VGA
BAT54S
BAT54S
SOT23
SOT23
GND_VGA
+V3.3S
D29
D29
BAT54S
BAT54S
SOT23
SOT23
+V5_VGA
GND_VGA
+V5_VGA
+V3.3S
C23
C23
C49
C49
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C0402
C0402
A
A
GND_VGA
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
GND_VGA
Add C323 for EMI issue
许沐锌 081222
Swain Xu(许沐锌)
Swain Xu(许沐锌)
Swain Xu(许沐锌)
GND_VGA
Connect GND to GND_VGA for EMI requirement
Swain 080724
Page Name
Page Name
Page Name
CRT CONN & S TV OUT & LIDR SWITCH
CRT CONN & S TV OUT & LIDR SWITCH
CRT CONN & S TV OUT & LIDR SWITCH
Size
Size
Size
Project Name
Project Name
Project Name
Rev
Rev
Rev
A3
A3
A3
X01
X01
X01
B
B
B
Date:
Date:
Date:
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Tuesday, September 29, 2009
Sheet
Sheet
Sheet
11
11
11
of
of
of
39
39
39
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information conf