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www.thinklabs.in Page 26 11101.

22V (V BG )11110V (GND) ADCSRA Bit 7 ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning theADC off while a conversion is in progress, will terminate this conversion. Bit 6 ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, writethis bit to one to start the first conversion. The first conversion after ADSC has been written after theADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADCclock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC willread as one as long as a conversion is in progress. When the conversion is complete, it returns to zero.Writing zero to this bit has no effect. Bit 5 ADFR: ADC Free Running Select When this bit is set (one) the ADC operates in Free Running mode. In this mode, the ADC samples andupdates the Data Registers continuously. Clearing this bit (zero) will terminate Free Running mode. Bit 4 ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The ADCConversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared byhardware when executing the corresponding interrupt Handling Vector. Alternatively, ADIF is cleared bywriting a logical one to the flag. Beware that if doing a Read-Modify- Write on ADCSRA; a pendinginterrupt can be disabled. Bit 3 ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt isactivated. Bits 2:0 ADPS2:0: ADC Prescaler Select Bits

www.thinklabs.in Page 27 These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADC Prescaler SelectionsADPS2 ADPS1 ADPS0Division Factor 0 0 020 0 120 1 040 1 181 0 0161 0 1321 1 0641 1 1128 ADC Data Register ADCH & ADCL

www.thinklabs.in Page 28 When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in twos complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to readADCH. Otherwise, ADCL must be read first, then ADCH.The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read fromthe registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the resultis right adjusted.