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CMOS Describe the working of NMOS ,PMOS & its regions of operations?

What is the significance of cutoff, linear and saturation region? what is pinch off? What causes pinch off? Which region would you consider for the operation of transistor if it is to be used as an amplifier and why? Why is the substrate in NMOS connected to Ground and in PMOS to VDD? What is the fundamental difference between a MOSFET and BJT ? Which transistor has higher gain. BJT or MOS and why? In CMOS digital design, why do we design the size of PMOS larger than that of NMOS ? Why PMOS and NMOS are sized equally in a Transmission Gates? What is threshold voltage & factors that influence threshold voltage? Second Order Effects What is latch up? What design challenge do you see here? What is Body Effect? Can it be avoided? If yes How? If no why? What is channel length modulation and its significance? What is drain punch through? Inverter Describe the operation of inverter? Given VDD 1.8v Vthn = Vthp = 0 .39v what is the range of operating voltage for which PMOS & NMOS would remain on? Explain the different regions of operations of an inverter, what is the significance of each? What is drive strength; explain the concept considering inverter as an example? Explain sizing of the inverter? Why do we gradually increase the size of inverters in buffer design when trying to drive a high capacitive load? Why not give the output of a circuit to one large inverter? General Questions On Layouts How do you come up with Source and Drain sharing strategy while drawing layouts for a design? What drives this strategy? Give a layout example Do you know transistor folding or what are transistor fingers, where did you use it and why ? How will you reduce the resistance of transistor if you have to while drawing layouts? Would you have the authority to change transistor parameters once design is freezed? What are the various techniques you know that could reduce parasitics in the layout, what are the measures you will consider to balance IR drop while drawing layouts? What are the general Layout guidelines you would stick to while drawing layouts for digital circuits and how are they different for analog circuits? Why are transistor orientations important? Do you know how to draw layouts for a resistor, capacitor, diode & bjt apart from pmos and nmos? Given a layout can you reverse engineer the schematic? Given a netlist can you arrive at the schematic? DRC LVS AND TECHNOLOGY/PROCESS RELATED QUESTIONS Explain the DRC & LVS flow describing the inputs and outputs of DRC & LVS and the structure of its reporting format. Importance of DRC rules, their intent, illustrate with some specific examples.

Categorically what are the basic DRC rules that can exist for any technology node? Why are DRC rules for low voltage transistors different from high voltage transistors? How different would be layouts for Lvt & Hvt devices? If different do you expect any extra layers to be a part of it, would DRC rules be different here? Sight some specific examples. Before you get started with the layout design what are the relevant aspects of the schematic you should know? Foundry Document, layers that exist, their purpose, do tape out layers necessarily mean they are send to the mask shop, or are they only the part of the GDS, why do non tape out layers exist? Layout and cross section view of all the devices What are the different measures & ideas that you would employ to reduce the parasitics in the layout? What are the routing challenges you have faced? What is an offgird error? What is the importance of it? How many devices does your 180nm/90nm process supports? How many metal layers supported? What are derived layers, marking layers, drawing layers? what is the importance of non-tapeout layer?