VLSI

VLSI
Channel Length Modulation:
0 < V
gs
< V
th
When V
gs
= 0, I
ds
= 0 therefore the channel not formed, but when V
gs
is
increase, channel gradually formed and increasing linearly and when V
gs
is
max i.e. V
gs
= V
DD
, The channel length is max:
When V
gs
> V
DD
, Reverse current start flowing (Reverse saturation current).
Channel length gradually decrease and becomes zero this is called Channel
Length Modulation.
The voltage at which Reverse Saturation current start flowing is called Pinch
off voltage.
The Operation of MOSFET is { }
V to V
th p
i.e. V
th
= Threshold voltage, VP =Pinch Off Voltage
Any Device works in this Range Only i.e. 0 < V
gs
< V
ds
NMOS Characteristics
1) Cutoff Region :
Case 1) V
gs
=0; V
gd
> V
gs
V
gd
Controlling Voltage
I
ds
= 0, V
ds
= 0
Cutoff Region Off Region

kT
V
t
q

Case 2) V
gs
<V
th,
V
gd
> Vgs
V
thn
= NMOS = 0.2V
I
ds
= nAmp
V
ds
= v 0
Page 1
VLSI
sub- threshold region
2) Linear Region:
Case 1) V
gs
> V
th
; V
gd
= V
gs
[V
gs
= 0.2v to 0.5v]
I
ds
= Amp
V
ds
= mv 0
Case 2) V
gs
> V
th
; V
gd
< V
gs
[V
gs
= 0.5v to 1.2v]
0 < Vds < (V
gs
- V
th
)
Ids = k ( )
2
2
V
ds
V V V
gs th ds



' ;


V
ds
=
( )
( )
2
2
&
V
ds
K V V V
gs th ds
Non Linear I V
ds ds



' ;

E55555555555555555F
0< V
ds
< (V
gs
V
th
)
[i.e. V
gs
- V
th
= 1.2v 0.2v =1v]
V
ds
< 1v
x (0,1)
x > x
2
V
ds
> V
ds
2
;
2
2
V
ds
V
ds
>>

( )
2
2
V
ds
I K V V V
ds gs th ds



' ;

( ) { }
I K V V V
ds gs th ds
Linear

E55555555555555555F
y = m x
Page 2
VLSI
I
ds
V
gs
= V
ary
V
ds
Voltage controlled device
3) Saturation Region :
V
gs
>> V
th
; V
gd
< V
th
V
ds
> (V
gs
- V
th
)
( )
2
2
K
I V Vth
ds gs

& I V
ds ds
are independents
2
I V
ds gs
(parabolic relationship)
i.e.
I
ds
is Saturation Region
Page 3
VLSI
I-V Characteristics
Page 4
V
gs
= 2v
V
gs
= 1v
V
gs
= 0v
Saturation Region
Saturation region
for FET in NMOS
I
ds
V
ds
Vds
In CRO
I
ds
VLSI
Low Saturation Region = Class A Amplifier = 50 %
Middle Saturation Region= Class B Amplifier = 78.51 %
High Saturation Region = Class C Amplifier = 91%
Having thermal runway problem. Because max power dissipation :
For this graphs using we draw the load line characteristics
And decide the voltage Amp are current Amp.
,
If V Ve
gs
I Ve
ds
V Ve So take mirror image
ds



If V
gs
. We get the | V
p
|
V
gs
0- v
dd
When R current high, Voltage is high
In MOSFET we can avoid B.D. Region
Page 5
V
gs
= 3v
V
gs
= 2v
V
gs
= 1v
V
gs
= 0v
Saturation Region
V
ds
I
ds
Cutoff
Region
Linear Region
Vth
Mirror Image
I
ds
V
ds
VLSI
Summary
1) Cutoff Region I
ds
= 0 ; V
ds
= 0
2) Linear Region I
ds
& V
ds
increase linearly
3) Saturation Region : Large change in V
ds
; Small change in I
ds
4) Breakdown Region Large change in I
ds
; Small change in V
ds
PMOS Characteristics :
Page 6
Breakdown Region
D
G
S
Cutoff Region
Large I
ds
Small I
ds
I
ds
V
ds V
ds

Large Small
V
ds
V
gs
= 2v
V
gs
= 1v
V
gs
= 0v
Saturation
region
-ve
+ve
+ve
-ve
VLSI
1)
0.2 V V or V V
th tp tp

2)
, , , I V V V
ds ds gs gd
To understand CMOS characteristics the common area PMOS & NMOS must be
consider
Transformation on PMOS
Page 7
Cutoff
Region
V
ds
I
ds
Linear
Saturation Region
V
gs
= V
gs
+ V
dd
VLSI
Analysis of CMOS Inverter
Logic diagram
CMOS Circuit diagram
Page 8
Right Shift
Vds
Vgs = 2v
Vgs = 1v
Vgs = 0v
Ids
Vds
Ids
Vds
Vgs = 2v
Vgs = 1v
Vgs = 0v
+5v
Vtp = -0.2v
0v
In PMOS only
Names PMOS
C S
L L
S C
VLSI
I/
P
NMO
S
PM
OS
0 OFF ON
1 ON OFF
Practically Invertors
0 x
0 1
1 1 Device fail
1 0 for (1,0) will not seen for reducing we are going for (NMOS
and PMOS)
Page 9
d
i/p
Vdd(O)
S
O/P
VLSI
NMOS PMOS
Cutoff Sat
Linear Sat
Sat Sat C3
Sat Linear
Sat Cutoff
Symmetric CMOS circuit will have condition 3 (set- (e3) set) so avoid
designing of symmetric CMOS circuit.
Asymmetric CMOS circuit. Where V
th
is not equal to
V
tp
[V
th
V
tp
] i.e. V
tp
= - 0.2 V
Transistor size of compare to another transistor so that V
th
is increase. So both
transistor are not ON at a time.
Page 10
I
ds
Vds
Vgs = 2v
Vgs = 1v
Vgs = 0v
Vtp=-0.2v
0v
Vgs = 2v
Vgs = 1v Vgs
Linear (PMOS)
Vgs = 0v
NMOS
Linear
Vtp=0.2v
NMOS
cutoff
Saturation(NMOS)
Saturation (PMOS
NMOS is continuous saturation region
where as PMOS goes to Saturation to linear
& after cutoff region
VLSI
It increase the size of PMOS transistor so that condition 3 avoided.
The size of PMOS transistor increase in such away that cutoff occupies linear,
linear occupies lower set. After middle set & after higher set. Hence C3 is
avoided leads to the power circuit.
Constrained limit of on size of NMOS. So that we cant increase the size of
NMOS.
Buffer :
Transistor = 1 Buffer Circuit.
O
NMOS O/P = V
gs
PMOS O/P = V
dd
- V
gs
Supply Bounce ground Bounce
The performance of NMOS circuit when there are connect to supply. Hence they
are called weak ones
The produce accurate O/P. When they are connect to ground. Hence called
Strong Zeros
PMOS circuits are called strong ones & weak zeros.
Page 11
n
2T 2T
n
d
i/p
O/p
Vd
d
1
O
O/p
= Vgs- Vth
= Vgs
=0V
Vdd
Vgs =0
Vgs = 0

5
VLSI
Note : Always connect NMOS to ground, PMOS to supply
Because PMOS connect to supply it takes extra energy from supply and response
an same as NMOS. Hence O/P is synchronizing. Therefore increase the size of
PMOS transistor.
If increaser the transistor NMOS. We should connect V
dd
to NMOS. NMOS
should not accept ones cause NMOS ones are weak. So that we are increase the
size of PMOS and apply extra energy to PMOS.
Application of CMOS
Power Dissipation
Total Power = Dynamic + static + leakage + SIC
PT = Pdy + PSTA + Ple + PSLC
Dynamic power (py) = f V
DD
2
C
L

Transition Activity
f Operating Frequency
V
DD
Supply voltage
C
L
Load Capacity
E = CV
2
E = CV
2
P = E/T = f.E = FCV
2
But for is no of cycles
P = (, f) CV
2
P= (, f) CV
2
If pdy , then f (x cant change) , C VDD (x cant change)
Page 12
VLSI
x
To Reduce dynamic power Transition activity() must be reduced.
is also called Hamming Distance i/p pattern.
= 8
1 0 1 1 0 1 1 ; = 4
1 1 1 1 1 ; = 0
If , dy also
Static Power :
P static = Static. V
DD
[static= DC current (Every Transistor have point from point]
Static technology is sinking static power decreases. S D
Distance , V
DD
so Q point (static also decreases)
Transistor size is , V
DD
, Q source to destination is small
Short Circuit Power :
Page 13
System
i/p
o/p

power
ENCODE System Decode

S1 S2 S3
O/P
S > S1 + S2 + S3
VLSI
1) |V
th
| = -0.32V
V
thn
= 0.2V
2) Bp = 2.5 Bn
Bp = Size of PMOS
Bp = Size of NMOS
NMOS general PMOS transistor is 8 times of NMOS transistors
i.e. Bp = 3 Bn
Leakage Power :
With sinking technology leakage current increase. Therefore leakage power increase.
65 nm V
DD
: 0. 9 V
V
DD
> V
DD
2
0.9 > 0.8
V
DD
= 10 V V
DD
2
= 100
V
DD
= 11 V V
DD
2
= 125
Page 14
I/p
V
DD
O/p
Conductor
L2
VLSI
V
DD
= 12 V V
DD
2
= 150
V
DD
= 13 V V
DD
2
= 225
V
DD
= 3V 9
V
DD
= 2V 4
To make V
DD
= 0. Connect adiabatic circuit
All Medical (Commented) applications are lower power and low speed
All Military Applications (-55 to 125c) are high power and high speed.
Dynamic power is high at higher technologies the technology shrinking dynamic
power reduces.
At lower technologys short circuit & leakage power can increase. Because the
channel length is small.
Pdy + Pstat + Ple + Pslc
Higher technology Lower Technology
PDy+Pst dominates PLe & PSlc dominates
High Speed Circuit
RC Circuit:
Page 15
SPEED
Low Speed
< 800 MHz
1. Capacitor
2. RL Circuit
High Speed
> 800 MHz
1. Inductive
2. RLC Circuit
VLSI
t 50% = 0.693 RC
T = RC
If R = 5, C = 5
t50% = K (RC)
= K (25)
T = 1 + 1 + 1 + 1 + 1
= 5
t50% = K(5)
= t 50% , delay , speed
= l , R , T speed
Longer wire having p , speed
Short wire having p , speed
Longer inter connects have larger delays. So therefore low speed & low power
Shorter inter connects have small delays. So high speed & high power.
RLC Circuit :
Page 16
R
V
C
VLSI
For RLC circuit T is not defined (Undefined)
Delay is always lower than time Unit
If XL = C Resistive. So T is not defined
t50% spice
Depletion Mode MOSFET (MOS capacitor)
Source and drain are Equally Doped where as Enhance mode mosFET source is
higher than drain
Oxide thickness, gate & substite thickness cannot be neglected.
The device is in the S.S. Region. In L.L. region v=0 & = constant.
Steppers are insulating material to avoids Recombination of substrate holes and
Electrons of source and drain.
Page 17
R
C
L
V=
0
- 0
x
S D
P-Substrate
VLSI
Stappers are used near source junction and drain junction.
C =
0
A/d(t
ox
); Q = CV;
If (t
ox
) ,
C=
0
A/d
So C
Depletion mode threshold voltage is Ve
Q = CV
Q = Constant
C = V
V = 0 V < 0
V = -0.52 V (Si)
V = -0.89V(Ge)
Threshold of mosFET
Depletion Region or Accumulation:
Conversion Region
Flate band region current constant S & D are etui potential
When V
gs
= 0V. The all
-1
are accumulated at source.
A Small no. of e
-
push towards the drain and they are recombine with
holes of gate As a result e
-
occupies the channel then form the (-Ve) plate.
There for mosFET act as capacitor in accumulation region.
Page 18
t
ox
tg

t
ox Both
tg
are
suffix
t
ox

tg
VLSI
Enhancement Mode Depletion Mode
1. Source is highly Dopped than drain
1. Source & Drain equally
Dopped
2. Oxide, gate, subscribe thickness are
neglected
2. All are consider
3. Threshold is (+Ve) 3. Threshold is (-Ve)
4. Applications:
Switch, sometimes Amplifier Capacitor
4. Breakdown Region Occurs
When (V
gs
>> V
DD
)
4. Breakdown does not occur
Fabrication Principles :
Basic Steps :
They are 10 steps
1) Water fabrication
2) Oxidation Dry
Wet
3) Masking, patterning or photolithography
4) Diffusion Pre diffusion
Drive In
5) Ion Implication
6) Deporition
7) Metalization
8) Passivation
9) Annealing
10) Clean chip
Semi Conductor : (Si/Ge)
1) SiO
2
Sand 80% Si + 20% Impure
Graphite 10% Si + 90 % impure
Page 19
VLSI
2) SiO
2
1500
0
C - 2000
0
C Rixe the temp 1500
0
C Oxide partials are removed Si in the
water state is consider by cooling down the temp Ingot is formed.
3) It is a cylindered shape or Clone shape.
Oxidation :
O
2
vapour is layered on wafer
To avoide varying component current oxidation or oxide layer is used.
Patterning on masking or Photolithography
Page 20
disk
Add
Wafer
P and n
type
Dry Wet
O
2
(1500-200
0
c) vapour
H
2
O
(1500-2000c)
H
2
Components are removed
pure O
2
vapour
Oxidatio
n
U,V Rays
Substrate
VLSI
If photo rays are used to remove the oxide layer then the process is called
photolithography
Diffusion:
1) Pre Diffusion
2) Drive In
Pre Diffusion :
The left over oxide partial in step3, are removed in pre diffusion states.
With 1
st
Cl Steps counteraction of substrate might decrease by adding Extra i on
concentration can be gained back.
Deposition :
1 Deposite n-type material at source & drain p-type material at gate.
2 At deposition stage exact source, gate & drain formed.
Metalization
A1 < 1994
Widely used Cu <1994
Best metrical is gold and Silver. But very cost so not used.
Page 21
Substrate
U,V Rays
P-Substrate
VLSI
Al 5 metal layer
Cu 8 metal layer
But Iron have more than 8 metal layer. But Iron have some disadvantage.
Diagonal routing is not possible.
Passivation :
Bringing down the temperature to room temperature is called as Passivation
GDSS
RTL GDS2
RTL - Silicon
For every VLSC components have another GDSS (Graphic Data System Stream)
Annealing :
If any radio activity nature exists that radio activity nature can be removed.
From 1
st
step on wards we are making a high temperature only.
Clean Chip:
The edges of course, gate and drain are sharply cut.
Enhancement Mode
(In terms of fabrication)
Depletion Mode
(In terms of fabrication)
1. Water fabrication made at 10m 1. 40-6010m
2. Oxidation is same 2. Same
3. Patterning is same 3. Same
4. Diffusion
Pre diffusion
Drive-In
4. Diffusion is same
5. Room Temperature are same 5. Same
6. Deposition 6. Deposition
7. Remaining all are same 7. Same
Region of Operation :
Page 22
VLSI
Various Pull-ups :
pull up N/W is S.C>
Page 23
Vgs< Vtn
Cutoff
Vgs > (Vgs-Vtn)
Vdl (Vgs-Vtn) linear Vdl (Vgs-Vtn)
saturation
Vgs, Vtn, Vds
i/p
VDD
p-mos
n-mos
p-mos pullup N/W
N-mos pull down. N/W
PUN
PDN
i/p o/p
P-mos
Parallel series
n-mos
Series
parallel
VLSI
Case 1)
PUN SLC
O/P V
ds
Disadvantage :
High power dissipation at o/p
Drain may be damaged.
Case 2) For control the current put a resistor
PUN = Resistor
O/P = V
DD
I
D
R
D
Disadvantage :
Device mis match, Hence fabrics is very difficult
Page 24
G
+Vgs
D
V
DD
O/p
V
ds
S
C
i/p
D
V
DD
O/p
I
D
R
D

VLSI
Case 3)
Depletion mode :
Disadvantage : Device mis match, power units (text is not visible in original format)
more high power defray patches.
Hence current always flower. Therefore high power dissipation circuits.
Case 4)
PUN = PMOS & Best Design
PUN is ON and OFF depends on i/p. Hence low power Circuit.
Q) Find the VCn or m1
Vt1 = 0.5v ; Vt2 = 2.55V
Page 25
C
i/p
l
O/p
V
DD
O/p
Act as resistor
PUN always on
i/p
O/p
V
DD
This is the best
N/W
Vgs
= 3v
O/p = 5V
V
DD
= 5v
M2
In PUN is
always vgs = 0
M1
VLSI
Transistor m1
V
gs

= 3V
V
ds
= 5V
V
gs
= 0.5V
V
ds
1 > (V
gs
1 vt1)
5 > ( 3 - 0.5 )
Set
Transistor m2
Vgs2 = 0
Vt2 = -2.55
V
ds
2
= 3V ( 8-5)
V
gs
2
V
t
= 2.55 V
V
gs
2
> (V
gs
2
-V
t
2
)
Set
Q) Find the Ratio x of Size of Transistor
Because of Both are saturation region. So I
ds1
=I
ds2
Note : Use current (text is not visible in original format) to calculate the
sizes of transistors always.
( )
( )
( )
( )
2
1
1 1 1
2
2
2 2 2
2
1 2.5
2
2 2.55
I K V V
ds gs t
I K V V
ds gs t
K
Suffix
K

'

K1 = 1.04 K2
PUN size is always greater than PDNN i.e. P-mos circuit always > the N-mos
circuit.
According to problem that values are not valid.
Page 26
VLSI
V
t1
= 0.5 V ; V
t2
= - 0.5 V
M1 : V
ds
< (V
gs1
-V
t1
)
V
ds
< (9 -0.5)
Linear
M2 : V
ds2
> (V
gs2
V
t2
)
Set
Q) For m1 be the saturation region what must be the range of i/p
0 4.5
1
V
gs
<
R) Find the ratios of transistor sizes
( )
( )
2
1
1 1 1
2
2
2 2
I K V V
ds gs t
K V V
gs t


Actual V
gs1
= 9V. But if get the saturation region take max i/p value xD take 4.5V
V
gs1
= 4.5V
( )
( )
2
4.0 0.5
1
2
2
4.5 0.5
1 0.016 2
K
K
k K

2 62.5
1
K K
w
K parameter as K nCox
L

,
For N-mos
Some times k can also be called as rate of conductance.
Page 27
Vgs
= 9v
O/p = 5V
VDD = 10V
VLSI
MOS capacitor C-V chart :
Vfb V flat Band
Vt Threshold Voltage
IR Conversion Reason
AR Active Reason
DR Depletion Reason
Tox = oxide thick ness
Page 28
IR ut dr vfb AR
tox
VLSI
( )
0.5
ox
ox
t A
c
d t
c
Q cv
c v
v

Tox mm m2 (text is not visible in original format)

Oxide Capacitance
2 ox
f
C
m

Oxide capacitance is =
2
capacitence f
unit area m

O/P Current :
( )
2
2
ds
ds n gs ds n
V
I K V Vt V K


' ;

2
2
n
n
n
n
K nCox
w
K nCox
l
Aml
K
V
Aml
K
V

_


,

Designing of CMOS Circuit

CMOS = NMOS + P MOS
(Circuit is parallel) Circuit is in series
Page 29
CMOS
NMOS PMOS
Parallel
Series
PDN
series
parallel
PUN
VLSI
NMOS circuit design very easy compared to PMOS
Designed AND gate
All CMOS circuit must be express in complemt form
If they are not in complement form express in complement form.
f = (AB)
NOR gate:
f = (A+B)
1
Page 30
V
DD
Parallel
V
DD
Serial
V
DD
A
B
A B
AB means serial
connection for
complements parallel
o/p : (AB)
1
VLSI
F = (AB + CD)
8 transistors are there to design given problem.
No. of i/ps into 2 = no. of transistors in this is not correct in all cases. So design
is must
f = AB
1
+ A
1
B
= (AB + A
1
B
1`
)
1
Page 31
V
DD
A B
(A+B)
A
B
A+B = Parallel
A B
C D
A
C
B
D
o/p
VLSI
Here NMOS = 4+1+1 = 6
PMOS = 4+ 1+ 1=6
f = AB + A
1
B
1
= A
1
B +AB
1
NAND & NOR & NOT are Basic gates in CMOS
Q) Consider a prosses technology L
min
= 0.4m
t
ox
= 8 nm ,
2
450
.sec
cm
n
v

, Vt =0.7
Find Cox Kn
Page 32
A B
C D
A
C
B
D
o/p
A

B
A B
A
A
B
B
o/p=A
1
B+AB
1
VLSI

m
m
l
w

8 . 0
8

calculate the values of V

gs
& V
ds
min need to operate the transistor
is in saturation region with C
D
=100

A
Fine the values of V
gs
reserved to cause the device to operate as a 1000 resistors.
co
w
K x
n n
l

_


,
m x
m
9
10 8

2
3
10 1 . 1
m
f
x

2
1 . 1
m
mF

w
K cox
n n
l

_


,
=450 x 1.1 x 10
-3
x
6
6
10 8 . 0
10 8

x
x

' Kn n con
=450*1.1 x 10
-3

( )
2
2
Kn
iD V V
gs th

( )
2
. *
2
cox w
n
iD V V
gs th
l

_


,
( )
2 2 3
2
450 10 10 1.1 10 10
6
100 10 0.7
2
x x x x x
X V
gs

Vgs = 0.52v
V
ds
min = V
gs
V
th
= 133 0.7 = 0.6
In saturation region
V
ds
r
d
i
d

small V
gs
1000
100
V
ds
A

6
1000 100 10 0.1 V V
ds


Page 33
V
ds
<(V
gs
V
th
) (V
gs
V
th
) V
ds

Linear Saturation
VLSI
V
gs
= V
th
+ V
ds
= 0.7+0.1 = 0.8v
Q) For 0.8

m process technology for which t

ox
=15Nm,
2
550
.sec
cm
n
v

find Cox
and Kn

-12
8.854 10
0
0.6
-9 2
0 15 10
X x mF
Cox
x
x m

.
w
Kn cox
n
l

l
w
Kn Kn '
Ln general W=6 to 10 times or L
W = (6 10) L
= 6L 10L
Unsidering max width W = 10L = 8

m
Kn=550x 10
-2
x10
-2
x0.6x10
-3
x8
Find sheet resistance after MOS FET over the range V
gs
= 1.5v-4v
2
215
.sec
cm
n
v

.
2
3
2
f F
Cox
m

, Vth = 1V,
m
m
L
W

3 . 0
3

Note: Sheet resistance of MOSFET can be calculated in linear region (Tride Region)
( )
.
W
I Cox V V V
d n gs th ds
L

Sheet Resistance R
( )
1
6
3 10
4 15
215 10 2.3 10 1.5 1
6
0.3 10
x
x

R
15
4.04 10
R
14
6.74 10 4 for V V
gs

Q) Find the regions of operation for following circuits, V
th
= 0.2V
Page 34
Process technology=0.8m
W.
L
L= 0.8 m
VLSI
V
gs
<V
th
Into if
V
ds
(V
gs
V
th
) Linear
V
ds
(V
gs
V
th
) Saturation
Q) For a process technology of a CMOS t
ox
=13 nm,
2
285
sec
m
n
V

,Vt=0.5v
Find 1. Cox & Kn
2. Resion or operations
Cox
2 9
12
68 . 0
10 13
10 854 . 8
m
MF
x
x
tox
Eox

Kn=x Cox
= 285 x10
-2
x10
-2
x0.68x10
-3
Page 35
1.5v
0.25
75
5
W m
l m

1
v Linear
1.5v
1V
50
5
m
_

,
2
0v
Linear
1.5v
2V 3
0v
Sat
1.5v
0.25V 4
0v
V
gs
=1.5v
V
ds
= 0.25v
V
th
= 0.2v
VLSI
=19.4
2

v
A
If Vgs -5V and o/p current = 20mA find the region of operation

take
L
W
10
V
ds
<(5 0.5
( )
2
.
2
V W
ds
I n Cox V V V
ds gs th dt
L

' ;


By using this is we can justify whether saturation can linear
For linear
I
ds
=
( ) { }
.
W
Cox V Vt V V V
n gs ds ds gs
L
<
( ) { }
.
W
n Cox V Vt V
gs ds
L

For saturation
( )
t gs
ox n
V V
L
W
.
2
C
ds I

Region of operation is saturation

Page 36
( ) ( )
.
2
V W
ds
I n Cox V Vt V Vt
ds gs gs
L

' ;

V V Vt
ds gs

103
VLSI
Page 37