------Roll Number: Thapar University Patiala Computer Science & Engineering Department B.E.

(COE) End Semester Test UCS401: Computer System Architecture May. 26 th , 2011 Time: 03 Hours; MM: 50 Name of Faculty: Karun Verma, Anju Bala Instruction to Students: Attempt all questions. Assume any missing data. Use ofcalculator is strictly not allowed. Q1. A two-way set associative cache memory uses blocks of fOUI words. The cache can accommodate a total of 2048 words from main memory. The main memory size is 128K x 32. a) Formulate all pertinent information required to construct the cache memory. 3 b) What is the size of cache memory? 1 c) Compare Write through and Write back operations. 2 Q2. A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The 5 computer system needs 4K bytes of RAM, 4K bytes of ROM. List the memory address map and indicate what size of decoders are needed. Draw neat diagram to show the memory connection to Cpu. Q3. a) What is an associative memory? 1 b) Obtain the match logic function of one word in an associative memory. 3 Q4. The logical address space in computer system consists of 128 segments. Each 2 segment can have upto 32 pages of 4K words in each. Physical memory consists of

4K blocks of 4K words in each. Formulate the logical and physical address formats. Q5. Two signed numbers A and B represented in signed 2's complement form are '5" compared by subtracting A-B. Status bits S, Z, and V are set or cleared depending on the result of the operation. Taking all possible cases, show that the relative magnitude of A and B can be determined from inspection of status bits as specified below. Relation Condition of Status bits A>B (S EB V)=O and Z=O A~B (S EB V)=O A<B (S EB V)=l A::;B (S EB V)=O or Z= 1 A=B 2=1 AtB Z=O 'r Q6. A digital computer has a memory capacity of 16384 x 40. There are a total of 45 4different instructions in the digital computer. Two instructions are packed in one memory word, and a 40-bit Instruction Register (IR) is available in the control unit. Formulate a procedure for fetching and executing instructions for this computer. Q7. Make the following changes to the basic computer 1. Add a register to the bus system CTR (count register) to be selected with 4 S2S1S0=000. 2. Replace the ISZ instruction with an instruction that loads a number into CTR. LDC Address CTR ~M[Addressl (36' 3. Add a register reference instruction ICSZ: Increment CTR and skip next

instruction if zero. 4. Discuss the advantage of this change. Q8. Write stack based instructions that compute the following function. 2 (A - B + C * (D * E - F))/ (G +H * K) Q9. Discuss Timing and Control unit of a basic computer in detail. 4 QlO. Design an arithmetic circuit with one selection variable S and two n-bit data inputs 4 A and B. The circuit generates the following four arithmetic operations in conjunction with the input carry Cin Draw the logical diagram for the first two stages. Qll. A two word inst.ruction is stored in memory at an address designated by symbol 4 2502. The address field of the instruction is stored in next memory word. The operand used during the execution of the instruction is stored at address symbolized by EAF. An index register contains the value 2521. State how E.AF is calculated from other addresses if the addressing mode of the instruction is i. Direct ii, Indirect Iii. Relative iv. Indexed Q12. Show the contents on hexadecimal of registers PC, AR, DR, IR, SC and AC of the 6 basic computer, when an instruction EA9F is fetched and executed from memory (PC=7FF) . M[A9F]=OC35, M[C35J=FFFF . Give the answer in a table with five columns one for each register and a row for each timing signal. Show the contents of the register after positive transitions of each clock pulse .