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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4013B flip-flops Dual D-type flip-flop


Product specication File under Integrated Circuits, IC04 January 1995

Philips Semiconductors

Product specication

Dual D-type ip-op


DESCRIPTION The HEF4013B is a dual D-type flip-flop which features independent set direct (SD), clear direct (CD), clock inputs (CP) and outputs (O, O). Data is accepted when CP is LOW and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) are independent and override the D or CP inputs. The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FUNCTION TABLES INPUTS SD H L H CD L H H CP X X X D X X X

HEF4013B ip-ops

OUTPUTS O H L H O L H H

INPUTS SD L L Notes CD L L CP D L H

OUTPUTS On + 1 L H On + 1 H L

1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition On + 1 = state after clock positive transition PINNING D CP SD CD O O data inputs clock input (L to H edge-triggered) asynchronous set-direct input (active HIGH) asynchronous clear-direct input (active HIGH) true output complement output

Fig.1 Functional diagram.

HEF4013BP(N): HEF4013BD(F): HEF4013BT(D):

14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1)

( ): Package Designator North America FAMILY DATA, IDD LIMITS category FLIP-FLOPS Fig.2 Pinning diagram. See Family Specifications

January 1995

Philips Semiconductors

Product specication

Dual D-type ip-op

HEF4013B ip-ops

January 1995

Fig.3 Logic diagram (one flip-flop).

Philips Semiconductors

Product specication

Dual D-type ip-op


AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP O, O HIGH to LOW 5 10 15 5 LOW to HIGH SD O HIGH to LOW SD O LOW to HIGH CD O HIGH to LOW CD O LOW to HIGH 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL tPLH tPHL tPLH tPHL 110 45 30 95 40 30 100 40 30 75 35 25 100 40 30 60 30 20 60 30 20 60 30 20 220 90 60 190 80 60 200 80 60 150 70 50 200 80 60 120 60 40 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX.

HEF4013B ip-ops

TYPICAL EXTRAPOLATION FORMULA 83 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 48 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 33 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL

January 1995

Philips Semiconductors

Product specication

Dual D-type ip-op


AC CHARACTERISTI CS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Set-up time D CP Hold time D CP Minimum clock pulse width; LOW Minimum SD pulse width; HIGH Minimum CD pulse width; HIGH Recovery time for SD Recovery time for CD Maximum clock pulse frequency 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRCD tRSD tWCDH tWSDH tWCPL thold tsu SYMBOL MIN. 40 25 15 20 20 15 60 30 20 50 24 20 50 24 20 15 15 15 40 25 25 7 14 20 TYP. 20 10 5 0 0 0 30 15 10 25 12 10 25 12 10 5 0 0 25 10 10 14 28 40 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz

HEF4013B ip-ops

see also waveforms Figs 4 and 5

VDD V Dynamic power dissipation per package (P) 5 10 15

TYPICAL FORMULA FOR P (W) 850 fi + (foCL) VDD 2 3 600 fi + (foCL) VDD 2 9 000 fi + (foCL) VDD
2

where fi = input freq. (MHz) fo = output freq. (MHz) CL = total load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V)

January 1995

Philips Semiconductors

Product specication

Dual D-type ip-op

HEF4013B ip-ops

Fig.4

Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values.

Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths.

January 1995

Philips Semiconductors

Product specication

Dual D-type ip-op


APPLICATION INFORMATION Some examples of applications for the HEF4013B are: Counters/dividers Registers Toggle flip-flops

HEF4013B ip-ops

Fig.6 Typical application of the HEF4013B in an n-stage shift register.

Fig.7 Typical application of the HEF4013B in a binary ripple up-counter; divide-by-2n.

Fig.8 Typical application of the HEF4013B in a modified ring counter; divide-by-(n + 1).

January 1995