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FEATURES
Qualified for Automotive Applications AEC-Q100 Test Guidance With the Following Results: Device Temperature Grade 3: 40C to 85C Ambient Operating Temperature Range Device HBM ESD Classification Level H2 Device CDM ESD Classification Level C3B 24-Bit Delta-Sigma Stereo A/D Converter High Performance: Dynamic Range: 112 dB (Typical) SNR: 111 dB (Typical) THD+N: 102 dB (Typical) High-Performance Linear Phase Antialias Digital Filter: Pass-Band Ripple: 0.005 dB Stop-Band Attenuation: 100 dB Fully Differential Analog Input: 2.5 V Audio Interface: Master- or Slave-Mode Selectable Data Formats: Left-Justified, I2S, Standard 24Bit, and DSD Function: Peak Detection High-Pass Filter (HPF): 3 dB at 1 Hz, fS = 48 kHz Sampling Rate up to 192 kHz System Clock: 128 fS, 256 fS, 384 fS, 512 fS, or 768 fS
23
Dual Power Supplies: 5 V for Analog 3.3 V for Digital Power Dissipation: 225 mW Small 28-Pin SSOP DSD Output: 1 Bit, 64 fS
APPLICATIONS
AV Amplifier MD Player Digital VTR Digital Mixer Digital Recorder
DESCRIPTION
The PCM1804-Q1 device is a high-performance, single-chip stereo A/D converter with fully differential analog voltage input which uses a precision deltasigma modulator and includes a linear-phase antialias digital filter and high-pass filter (HPF) that removes DC offset from the input signal. The PCM1804-Q1 device is suitable for a wide variety of mid- to highgrade consumer and professional applications, where excellent performance and 5-V analog supply and 3.3-V digital power-supply operation are required. The PCM1804-Q1 device can achieve both PCM audio and DSD format due to the precision deltasigma modulator. The PCM1804-Q1 device is fabricated using an advanced CMOS process and is available in a small 28-pin SSOP package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners.
Copyright 2012, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TA 40C to 85C PACKAGE SSOP - DB Reel of 2000 ORDERABLE PART NUMBER PCM1804S1IDBRQ1 TOP-SIDE MARKING PCM1804Q
HPF
HPF
Power Supply
RST
VCC AGND
DGND
VDD
B0029-01
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
PIN ASSIGNMENTS
PCM1804 PACKAGE (TOP VIEW)
VREFL AGNDL VCOML VINL+ VINL FMT0 FMT1 S/M OSR0 OSR1 OSR2 BYPAS DGND VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VREFR AGNDR VCOMR VINR+ VINR AGND VCC OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL DATA/DSDR
P0007-02
Pin Functions
PIN NAME AGND AGNDL AGNDR BCK/DSDL BYPAS DATA/DSDR DGND FMT0 FMT1 LRCK/DSDBCK OSR0 OSR1 OSR2 OVFL OVFR RST SCKI S/M VCC VCOML VCOMR VDD VINL VINL+ VINR (1) (2) (3) PIN 23 2 27 16 12 15 13 6 7 17 9 10 11 21 20 19 18 8 22 3 26 14 5 4 24 I/O I O I I I I I O O I I I I I I Analog ground Analog ground for VREFL Analog ground for VREFR
(1)
DESCRIPTIONS
I/O Bit clock input/output in PCM mode. Left-channel audio data output in DSD mode. HPF bypass control. High: HPF disabled. Low: HPF enabled.
(1)
Left-channel and right-channel audio data output in PCM mode. Right-channel audio data output in DSD mode. (DSD output, when in DSD mode) Digital ground Audio data format 0. See Table 5. Audio data format 1. See Table 5.
(2) (2) (1)
I/O Sampling clock input/output in PCM and DSD modes. Oversampling ratio 0. See Table 1 and Table 2. Oversampling ratio 1. See Table 1 and Table 2. Oversampling ratio 2. See Table 1 and Table 2.
(2) (2) (2)
Overflow signal of left-channel in PCM mode. This is available in PCM mode only. Overflow signal of right-channel in PCM mode. This is available in PCM mode only. Reset, power-down input, active-low
(2) (3)
System clock input; 128 fS, 256 fS, 384 fS, 512 fS, or 768 fS. Slave or master mode selection. See Table 4. Analog power supply Left-channel analog common-mode voltage (2.5 V) Right-channel analog common-mode voltage (2.5 V) Digital power supply Left-channel analog input, negative pin Left-channel analog input, positive pin Right-channel analog input, negative pin
(2)
Schmitt-trigger input Schmitt-trigger input with internal pulldown (51 k typically), 5-V tolerant. Schmitt-trigger input, 5-V tolerant. 3
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (IR reflow, peak) ESD Rating (1) Human Body Model (HBM) AEC-Q100 Classification Level H2 Charged Device Model (CDM) AEC-Q100 750 V Classification Level C3B
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
UNIT V V Vpp
4.75 3
36.864 192 10 70
MHz kHz pF C
If the VCC drops below the minimum recommended operating condition of 4.75 V, to avoid a brown out condition the VCC power must be cycled to 0 V and then to > 4.75 V to ensure continued device functionality.
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted.
PARAMETER Resolution DATA FORMAT Audio data interface format Audio data bit length Audio data format DIGITAL INPUT/OUTPUT Logic family
(1) (2)
TEST CONDITIONS
PCM1804DB MIN TYP 24 Standard, I2S, left-justified 24 MSB first, 2s-complement, DSD TTL compatible 2 2 5.5 VDD 0.8 65 100 10 100 10 50 2.4 0.4 32 192 12.288 18.432 24.576 36.864 24.576 36.864 24.576 36.864 MAX
UNIT Bits
Bits
VDC VDC A
VIN = VDD VIN = VDD VIN = VDD IIL VOH VOL fS Low-level input current High-level output voltage Low-level output voltage Sampling frequency VIN = 0 V VIN = 0 V
IOH = 1 mA IOL = 1 mA
(4)
CLOCK FREQUENCY 256 fS, single rate 384 fS, single rate 512 fS, single rate System clock frequency 768 fS, single rate 256 fS, dual rate 384 fS, dual rate 128 fS, quad rate 192 fS, quad rate DC ACCURACY Gain mismatch, channelto-channel Gain error (VIN = 0.5 dB) Bipolar zero error (1) (2) (3) (4) (5) (6) (7) HPF bypass 0.2 3 4 % of FSR % of FSR % of FSR
(5) (5) (5) (5)
MHz
Pins 611, 19: FMT0, FMT1, S/M, OSR0, OSR1, OSR2, RST (Schmitt-trigger input with internal pulldown (51 k typically), 5-V tolerant) Pin 18: SCKI (Schmitt-trigger input, 5-V tolerant) Pins 12, 1617: BYPAS, BCK/DSDL, LRCK/DSDBCK (in slave mode, Schmitt-trigger input) Pins 1517, 20, and 21: DATA/DSDR, BCK/DSDL, LRCK/DSDBCK (in master mode), OVFR, OVFL Single rate, fS = 48 kHz Dual rate, fS = 96 kHz Quad rate, fS = 192 kHz
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
TEST CONDITIONS
PCM1804DB MIN TYP 102 49 101 47 101 47 100 106 112 112 112 112 105 111 111 111 111 97 109 107 107 2.5 2.5 10 0.453 fS 0.547 fS 0.005 100 0.375 fS 0.49 fS 0.77 fS 0.005 135 37/fS 9.5/fS fS/48000 MAX 95
UNIT
VIN = 0.5 dB VIN = 60 dB VIN = 0.5 dB THD+N Total harmonic distortion plus noise VIN = 60 dB VIN = 0.5 dB VIN = 60 dB
fS = 48 kHz, system clock = 256 fS fS = 96 kHz, system clock = 256 fS fS = 192 kHz, system clock = 128 fS
dB
VIN = 0.5 dB DSD mode fS = 48 kHz, system clock = 256 fS Dynamic range (Aweighted) VIN = 60 dB DSD mode fS = 48 kHz, system clock = 256 fS SNR (A-weighted) fS = 96 kHz, system clock = 256 fS fS = 192 kHz, system clock = 128 fS DSD mode fS = 48 kHz, system clock = 256 fS Channel separation ANALOG INPUT Input voltage Center voltage Input impedance DIGITAL FILTER PERFORMANCE Pass-band edge Stop-band edge Pass-band ripple Stop-band attenuation Pass-band edge (0.005 dB) Pass-band edge (3 dB) Stop-band edge Pass-band ripple Stop-band attenuation Group delay Group delay HPF frequency response (8) Single rate, dual rate Single rate, dual rate Single rate, dual rate Single rate, dual rate Quad rate Quad rate Quad rate Quad rate Quad rate Single rate, dual rate Quad rate 3 dB Single-ended Differential input fS = 96 kHz, system clock = 256 fS fS = 192 kHz, system clock = 128 fS fS = 96 kHz, system clock = 256 fS fS = 192 kHz, system clock = 128 fS
dB
dB
dB
V VDC k Hz Hz dB dB Hz Hz Hz dB dB s s Hz
The fIN = 1 kHz, using System Two audio measurement system by Audio Precision in RMS mode, with 20-kHz LPF and 400-Hz HPF in calculation for single rate, or with 40-kHz LPF in calculation for dual and quad rates .
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
TEST CONDITIONS
PCM1804DB MIN 4.75 3 TYP 5 3.3 35 15 27 18 225 265 235 5 10 100 70 290 MAX 5.25 3.6 45 20
UNIT
VDC
mA
Operation, VCC = 5 V, VDD = 3.3 V PD Power dissipation Operation, VCC = 5 V, VDD = 3.3 V Operation, VCC = 5 V, VDD = 3.3 V
mW
Power down, VCC = 5 V, VDD = 3.3 V TEMPERATURE RANGE Operation temperature JA (9) (10) (11) (12) Thermal resistance Single rate, fS = 48 kHz Dual rate, fS = 96 kHz Quad rate, fS = 192 kHz Minimum load on DATA/DSDR (pin 15)
C C/W
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
95
40
100 0.5 dB
45
110
SNR
105
60 dB
50
105
110 20
55 0 20 40 60 80 T Temperature C
100 20
20
40
60
80
G002
G001
T Temperature C
95
40
100 0.5 dB
45
110
SNR
105
60 dB
50
105
110 4.50
100 4.50
4.75
5.00
5.25
5.50
G004
G003
Figure 3.
Figure 4.
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
95
40
100
0.5 dB
45
110
SNR
105
60 dB
50
105
55
100 32 44.1 48
G006
G005
Figure 6.
20
40
60
80
100
120 100
80
60
40
20
0
G009
Signal Level dB
Figure 7.
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
AMPLITUDE vs FREQUENCY
0
24000
12000 f Frequency Hz
24000
G008
Figure 8.
Figure 9.
AMPLITUDE vs FREQUENCY
0 20 40 Amplitude dB fS = 96 kHz, System Clock = 256 fS
24000 f Frequency Hz
48000
G010
24000 f Frequency Hz
48000
G011
Figure 10.
Figure 11.
10
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
AMPLITUDE vs FREQUENCY
0 fS = 192 kHz, System Clock = 128 fS
20 40 Amplitude dB
96000
48000 f Frequency Hz
96000
G013
Figure 12.
Figure 13.
AMPLITUDE vs FREQUENCY
0 20 40 Amplitude dB 60 80 100 120 140 160 22050 0 11025 f Frequency Hz
G015
22050
Figure 14.
Figure 15.
11
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Single Rate
OVERALL CHARACTERISTICS FOR SINGLE-RATE FILTER
50 fS = 48 kHz 0
Amplitude dB
50
100
150
Amplitude dB
200 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
G016
150 0.00
0.25
0.50
0.75
1.00
G017
Normalized Frequency y fS
Normalized Frequency y fS
Amplitude dB
0.02
0.04
6.04 dB at 0.5 fS
0.06
0.08
0.1
0.2
0.3
0.4
0.5
0.6
G018
0.47
0.49
0.51
0.53
0.55
G019
Normalized Frequency y fS
Normalized Frequency y fS
Figure 18.
Figure 19.
12
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Dual Rate
OVERALL CHARACTERISTICS FOR DUAL-RATE FILTER
50 fS = 96 kHz 0
Amplitude dB
50
100
150
Amplitude dB
200 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Normalized Frequency y fS
G020
150 0.00
0.25
0.50
0.75
1.00
G021
Normalized Frequency y fS
Amplitude dB
0.02
0.04
6.02 dB at 0.5 fS
0.06
0.08
0.1
0.2
0.3
0.4
0.5
0.6
G022
0.47
0.49
0.51
0.53
0.55
G023
Normalized Frequency y fS
Normalized Frequency y fS
Figure 22.
Figure 23.
13
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Quad Rate
OVERALL CHARACTERISTICS FOR QUAD-RATE FILTER
50 fS = 192 kHz 0 0 10 20 30 40 Amplitude dB 50 Amplitude dB 50 60 70 80 90 100 110 150 120 130 140 200 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Normalized Frequency y fS
G024
100
150 0.00
0.25
0.50
0.75
1.00
G025
Normalized Frequency y fS
0.00
Amplitude dB
0.02
0.04
0.06
0.08
0.10 0.0
0.1
0.2
0.3
0.4
0.5
0.6
G026
10 0.45
0.47
0.49
0.51
0.53
0.55
G027
Normalized Frequency y fS
Normalized Frequency y fS
Figure 26.
Figure 27.
14
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) HIGH-PASS FILTER (HPF) FREQUENCY RESPONSE
STOP-BAND CHARACTERISTICS
0 10 20 30 Amplitude dB 40 50 60 70 80 90 100 0.0 1.0 0.0 Amplitude dB 0.0 0.2
PASS-BAND CHARACTERISTICS
0.2
0.4
0.6
0.8
0.1
0.2
0.3
0.4
G028
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
G029
Figure 28.
Figure 29.
15
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
HPF
HPF
Power Supply
RST
VCC AGND
DGND
VDD
B0029-01
0
Quad-Rate Filter
20 40 Amplitude dB
Dual-Rate Filter
SingleRate Filter
Modulator
144
192
16
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
tw(SCKH) tw(SCKL)
PARAMETER System clock pulse duration, HIGH System clock pulse duration, LOW
MIN 11 11
UNIT ns ns
POWER-DOWN FUNCTION
The PCM1804-Q1 device has a power-down feature that is controlled by RST (pin 19). Entering the power-down mode is done by keeping the RST input level low for more than 65536 / fS. In the master mode, the SCKI (pin 18) is used as the clock signal for the power-down counter. While in the slave mode, SCKI (pin 18) and LRCK (pin 17) are used as the clock signal. The clock(s) must be supplied until the power-down sequence completes. As soon as RST goes high, the PCM1804-Q1 device starts the reset-release sequence described in the PowerOn and Reset Functions section.
OVERSAMPLING RATIO
The oversampling ratio is selected by OSR2 (pin 11), OSR1 (pin 10), and OSR0 (pin 9) as shown in Table 1 and Table 2. The PCM1804-Q1 device needs RST to equal low when logic levels on the OSR2, OSR1, and OSR0 pins are changed.
17
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
Only available in master mode at the quad rate Modulator is running at 128 fS. Modulator is running at 64 fS. Modulator is running at 32 fS.
18
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
VCC, VDD
Reset Removal
System Clock
T0014-07
RST t(RST) RST Pulse Duration (t(RST)) = 40 ns (Min) Reset Internal Reset 1/fS (Max) System Clock
T0015-05
Reset Removal
Reset Removal
Internal Reset
Reset 1116/fS
Ready / Operation
Data(1)
Zero Data
Converted Data(2)
T0051-01
(1) (2)
In the DSD mode, DSDL is also controlled like DSDR. The HPF transient response appears initially.
Figure 35. ADC Digital Output for Power-On-Reset and RST Control
19
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
INTERFACE MODE
The PCM1804-Q1 device supports master mode and slave mode as interface modes, which are selected by S/M (pin 8) as shown in Table 4. In master mode, the PCM1804-Q1 device provides the timing of the serial audio data communications between the PCM1804-Q1 device and the digital audio processor or external circuit. While in slave mode, the PCM1804-Q1 device receives the timing for data transfer from an external controller. Slave mode is not available for DSD. Table 4. Interface Mode
S/M Low High MODE Master mode Slave mode
DATA FORMAT
The PCM1804-Q1 device supports four audio data formats in both master and slave modes, and these data formats are selected by FMT0 (pin 6) and FMT1 (pin 7) as shown in Table 5. Table 5. Data Format
FMT1 Low Low High High FMT0 Low High Low High
2
FORMAT PCM, left-justified, 24-bit PCM, I S, 24-bit PCM, standard, 24-bit DSD
20
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
L-Channel
R-Channel
NOTE: LRCK and BCK work as outputs in master mode and as inputs in slave mode.
21
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
0.5 VDD
DATA
0.5 VDD
T0018-03
PARAMETERS t(BCKP) tw(BCKH) tw(BCKL) t(CKLR) t(LRCP) t(CKDO) t(LRDO) tr tf (1) (2) (3) BCK period BCK pulse duration, HIGH BCK pulse duration, LOW Delay time, BCK falling edge to LRCK valid LRCK period Delay time, BCK falling edge to DATA valid Delay time, LRCK edge to DATA valid Rising time of all signals Falling time of all signals Rising and falling times are measured from 10% to 90% of IN/OUT signal swing. The load capacitance of all signals is 10 pF. The t(BCKP) is fixed at 1 / (64 fS) in case of master mode.
MIN 32 32 5
MAX
UNIT ns ns
15 1 / fS 15 15 10 10
ns ns ns ns ns
5 5
Figure 37. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs)
22
PCM1804-Q1
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t(LRCP) LRCK tw(BCKL) tw(BCKH) t(LRHD) 1.4 V t(BCKP) t(CKDO) t(LRDO) t(LRSU) 1.4 V
BCK
DATA
0.5 VDD
T0017-03
PARAMETERS t(BCKP) tw(BCKH) tw(BCKL) t(LRSU) t(LRHD) t(LRCP) t(CKDO) t(LRDO) tr tf (1) (2) BCK period BCK pulse duration, HIGH BCK pulse duration, LOW LRCK setup time to BCK rising edge LRCK hold time to BCK rising edge LRCK period Delay time, BCK falling edge to DATA valid Delay time, LRCK edge to DATA valid Rising time of all signals Falling time of all signals Rising and falling times are measured from 10% to 90% of IN/OUT signals swing. The load capacitance of the DATA /DSDR signal is 10 pF.
TYP
UNIT ns ns ns ns
1 / fS 5 5 25 25 10 10 ns ns ns ns
Figure 38. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs)
DSDR
Dn3
Dn2
Dn1
Dn
Dn+1
Dn+2
Dn+3
T005201
23
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
tw(BCKH)
tw(BCKL)
t(CKDO)
DSDBCK t(BCKP)
0.5 VDD
DSDL DSDR
0.5 VDD
T005301
PARAMETERS t(BCKP) tw(BCKH) tw(BCKL) t(CKDO) tr tf (1) (2) DSDBCK period DSDBCK pulse duration, HIGH DSDBCK pulse duration, LOW Delay time DSDBCK falling edge to DSDL, DSDR valid Rising time of all signals Falling time of all signals Rising and falling times are measured from 10% to 90% of IN/OUT signal swing. The load capacitance of the DSDBCK, DSDL, and DSDR signal is 10 pF.
MIN
MAX
UNIT ns ns ns
15 10 10
ns ns ns
Figure 40. Audio Data Interface Timing for DSD (Master Mode Only)
24
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
State of Synchronization
Synchronous
Asynchronous
Synchronous
(1) (2)
Applies only for slave mode; the loss of synchronization never occurs in master mode. The HPF transient response appears initially.
Figure 41. ADC Digital Output for Loss of Synchronization and Resynchronization
25
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
S0058-01
A. B.
C1, C2, C5, and C6: Bypass capacitors, 0.1-F ceramic and 10-F tantalum, depending on layout and power supply C3, C4: Bypass capacitor, 0.1-F tantalum, depending on layout and power supply
26
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
Figure 43 shows a typical circuit connection diagram in the DSD data format operation.
PCM1804 C1 + 1 2 AGNDL C3 + 3 VCOML 4 + L-Channel In 6 FMT0 Format [1:0] 7 FMT1 8 Master/Slave 9 Control Oversampling Ratio [2:0] 10 11 12 HPF Bypass 13 3.3 V C5 + 14 VDD DATA/DSDR S/M OSR0 OSR1 OSR2 BYPAS DGND OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL VCC AGND 5 VINL+ VINL VINR+ VINR VCOMR AGNDR VREFL VREFR C2 28 + 27 C4 26 + 25 + 24 23 C6 22 21 20 19 Reset 18 17 Data Clock 16 L-Channel Data Out 15 R-Channel Data Out Audio Data Processor System Clock Overflow 5V + R-Channel In
S0058-02
A. B.
C1, C2, C5, and C6: Bypass capacitors, 0.1-F ceramic and 10-F tantalum, depending on layout and power supply C3 and C4: Bypass capacitors, 0.1-F tantalum, depending on layout and power supply
27
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
28
PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
R3 = 1 k 4.7 k 4.7 k Analog In _ + OPA2134 1/2 10 F + + OPA2134 1/2 VCOM 0.1 F R4 = 1 k C(1) 10 F + + OPA2134 1/2
S0059-01
0.01 F
R2 = 3.3 k
R6 = 47
VIN+
(1)
A capacitor value of 1800 pF is recommended, unless an input signal greater than 6 dBFS at 100 kHz or higher is applied in the DSD mode. In that case, 3300 pF is recommended.
VIN+ VIN
Modulator
_ BGR +
VCOM
VREF
_ +
S0060-01
29
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
REVISION HISTORY
Changes from Original (June 2012) to Revision A Page
Changed part number from PCM1804-ME to PCM1804-Q1. ............................................................................................... 1 Added table note under recommended operating conditions table. ..................................................................................... 4
30
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5-Nov-2012
PACKAGING INFORMATION
Orderable Device PCM1804S1IDBRQ1
(1)
Status
(1)
Eco Plan
(2)
Samples
(Requires Login)
ACTIVE
TBD
Call TI
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF PCM1804-Q1 :
Catalog: PCM1804
NOTE: Qualified Version Definitions:
Addendum-Page 1
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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