Introduction - Chapter 1

Text Book:

Silicon VLSI Technology Fundamentals Practice and Fundamentals, Modeling

Authors: J. J D D. Plummer Plummer, M M. D D. Deal Deal,

and P. B. Griffin

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

INTRODUCTION - Chapter 1
This course is basically about silicon chip fabrication fabrication, the technologies used to manufacture ICs. We will place a special emphasis on computer simulation tools to help understand these processes and as design tools tools. These simulation tools are more sophisticated in some technology areas than in others, but in all areas they have made tremendous progress in recent years.
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Evolution of IC Fabrication

1960 and d 1990 i integrated t t d circuits. i it Progress due to: Feature size reduction - 0.7X/3 years (Moores Law). Increasing chip size - 16% per year. Creativity y in implementing p g functions.
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Semiconductor Progress
Decreasing: feature size (line widths widths, line spacing spacing, layer depth, layer-to-layer tolerances), power per active component, operating voltage Increasing: chip size, wafer size, circuit density, circuit complexity complexity, speed speed, and reliability Economics: virtuous economic and development cycle

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Feature Size 100m

Device Scaling Over Time

Era of Simple Scaling

Introduction - Chapter 1

10m

Cell dimensions

1m 130 nm in 2002 0.1m

Scaling + Innovation (ITRS)

18 nm in 2018

Invention
Atomic dimensions

10nm

Transition Region Quantum Effects Dominate Atomic Dimensions 1960 1980 2000

1nm 0.1nm

2020

2040

Year

The era of easy scaling is over. We are now in a period where technology and device innovations are required. Beyond 2020, new currently unknown inventions will be required.
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Year of Production Technology Node (half pitch) MPU Printed Gate Length DRAM Bits/Chip (Sampling) MPU Transistors/Chip (x106) Min Supply Voltage (volts)

1998

2000 100 nm

2002 130 nm 70 nm 1G 1.2-1.5 1.2 1.5

2004 90 nm 53 nm 4G 550 0.9-1.2 0.9 1.2

2007 65 nm 35 nm 16G 1100 0.8-1.1 0.8 1.1

2010 45 nm 25 nm 32G 2200 0.7-1-0 0.7 10

2013 32 nm 18 nm 64G 4400 06-0.9 06 0.9

2016 22 nm 13 nm 128G 8800 0.5-0.8 0.5 0.8

2018 18 nm 10 nm 128G 14,000 0.5-0.7 0.5 0.7

250 nm 180 nm 256M 1.8-2.5 1.8 2.5 512M 1.5-1.8 1.5 1.8

ITRS at http://public.itrs.net/ (2003 version + 2004 update) on class website.

Assumes CMOS technology gy dominates over entire roadmap. p 2 year cycle moving to 3 years (scaling + innovation now required).

1990 IBM demo of scale lithography. Technology appears to be capable of making structures much smaller than currently known device limits.
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Intel From Sand to Silicon

http://www.intel.com/pressroom/kits/chipmaking/
A quick video of IC fabrication

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Linewidth vs. Fab Cost

100000
Fab Cost ($M) Linewidth (nm)

10

10000

1000

100

01 0.1
10
100mm 150mm 200mm 300mm 450mm

1 0.01 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025

Advantages and Challenges Associated with the Introduction of 450mm Wafers :A position paper report submitted by y the ITRS Starting g Materials Sub-TWG, , June 2005. http://public.itrs.net/papers.html
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

Linewidth (um) )
2000 by Prentice Hall Upper Saddle River NJ

Fab Cost ($M) )

Introduction - Chapter 1

Moores Law
On April 19, 1965 Electronics Magazine published a paper by Gordon Moore in which he made a prediction about the semiconductor i d industry i d that h has h become b the h stuff ff of f legend. l d The number of transistors incorporated in a chip will approximately pp y double every y 24 months. Known as Moore's Law, his prediction has enabled widespread proliferation of technology worldwide, and today h become has b shorthand h th d for f rapid id technological t h l i l change. h

http://www.intel.com/pressroom/kits/events/moores_law_40th/index.htm?iid=tech_mooreslaw+body_presskit
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Historical Perspective
Invention of the bipolar transistor - 1947, Bell Labs. Shockleys creative failure methodology

N P N

N P N

Grown junction transistor technology of the 1950s

N P N
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

History
Bardeen, Brattain and Shockley
Point Contact Transistor in 1947 at Bell Laboratory Followed by the bipolar transistor

Integrated Circuit Development

Jack Kilby demonstrated in 1958
Texas Instruments

Robert Noyce similar time frame with Silicon

Fairchild Semiconductor

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Physical Devices
NPN and d PNP Bi Bipolar l J Junction ti T Transistors i t Field Effect Transistors (FET)
Metal Metal-Oxide-Semiconductor Oxide Semiconductor FET (MOSFET) Junction FET (JFET)

Others:
PN Junction Resistor Capacitor p Photo-Diode and Photo-Transistor

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1
In

In

Alloy junction technology of the 1950s.

P N

N N P N P N P N N P N

Double diffused transistor technology of the 1950s.

N

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Si O2 N P

N P N

The planar process (Hoerni Fairchild, late 1950s). First passivated junctions.

P N

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Photolithography g p y
Basic lithography process
Apply pp y p photoresist Patterned exposure Remove photoresist regions Etch wafer Strip remaining photoresist
Photoresist Deposited Film Substrate Film deposition Etch mask Photoresist application Exposure

Light Mask

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

Development
15

Etching

Resist removal
2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Planar Integrated Circuit

Patterning of multiple photoresist patterns and processing steps create a planar integrated circuit
P regions N regions Metal Contact Holes Metal Pattern

Analog BJT

Vsource Base Collector

P N P N

Ground Emitter

Resistor
N
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

Resistor

16

2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Planar Digital IC
Complimentary Metal-Oxide-Semiconductor (CMOS)
N-channel MOS Field Effect Transistors NMOS P-channel P channel MOS Field Effect Transistors PMOS
Mask Layers: P-well ll N-well P+ N+ G Gate Contact L1 L1-L2 via L2 L2-L3 via L3

P+

P+

N+

N+

N Well

P Well

PMOS

NMOS

Thickness Substrate: Subst ate: >500 500 um u Active Layer: < 1 um

2000 by Prentice Hall Upper Saddle River NJ

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

P 17

Introduction - Chapter 1

Multiple Metal Layers

Metal Planarization required i df for multiple lti l metal layers
Metal Deposition p Patterning Fill Dielectric Planarization Contact vias Contact Deposition

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

Silicon Technology Leadership and the New Scaling Paradigm Mark Bohr, Intel Senior Fellow, Logic Technology Development April 18, 2007 19

2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Computer Simulation Tools (TCAD)

Most of the basic technologies in silicon chip manufacturing can now be simulated. Simulation is now used for:
Designing new processes and devices. Exploring the limits of semiconductor devices and technology gy ( (R&D). ) Centering manufacturing processes. Solving manufacturing problems (what-if?)

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Simulation of an advanced local oxidation process.

Simulation of photoresist exposure.

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

NEXT TIME: BASIC DEVICE PHYSICS

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Challenges For The Future

Introduction - Chapter 1

Having a roadmap suggests that the future is well defined and there are few challenges to making it happen happen. The truth is that there are enormous technical hurdles to actually achieving the forecasts of the roadmap. Scaling is no longer enough. 3 stages for future development: Technology Performance Boosters
Sili id Silicide Sidewall Spacer Poly Gate Silicide Source S/D Ext Rchan S/D Ext Drain

Invention

Gate

Gate Di l t i Dielectric

Source

Drain

???

Substrate

Spin-based devices Molecular M l l devices d i Rapid single flux quantum Quantum cellular automata Resonant tunneling devices g electron devices Single

Materials/process innovations NOW

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

Beyond Si CMOS IN 15 YEARS?? Device innovations IN 5-15 YEARS 23

2000 by Prentice Hall Upper Saddle River NJ

Broader Impact of Silicon Technology

Introduction - Chapter 1

Tip on Stage

Individual Actuator
00 0.0

Part of 12 x 12 array
Cornell University -0.5V 0 5V -0.75V -1V 1.25 V -1.5V -1.75V -2V -2.25V -2.5V Stanford, Cornell

Source SiO2 Gate

Drain
Ids(A)

-0.5 -1.0 -1.5 -2.0 -2.5 25 -3.0x10

-6

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 Many other applications e.g. MEMs and many new device structures e.g. carbon D(V) nanotube t b devices, d i all ll use basic b i silicon ili technology t h l for f fabrication. f Vb i ti
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ

Introduction - Chapter 1

Summary of Key Ideas

ICs are widely regarded as one of the key components of the information age. Basic inventions between 1945 and 1970 laid the foundation for today's silicon industry. For more than 40 years, "Moore's Law" (a doubling of chip complexity every 2-3 years) has held true. CMOS has become the dominant circuit technology because of its low DC power consumption, high performance and flexible design options. Future projections suggest these trends will continue at least 15 more years. Silicon technology has become a basic toolset for many areas of science and engineering. Computer simulation tools have been widely used for device, circuit and system design for many years. CAD tools are now being used for technology design. Chapter 1 also contains some review information on semiconductor materials semiconductor i d t devices. d i These Th topics t i will ill be b useful f l in i later l t chapters h t of f the th text. t t
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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2000 by Prentice Hall Upper Saddle River NJ