OFDM

Implementation of OFDM Transmitter and Receiver
CHAPTER 1: INTRODUCTION
Dept. of E & C J.S.S.A.T.E .B lore.
INTRODUCTION
1.1 Introduction :
Orthogonal frequency-division multiplexing (OFDM), essentially
identical to coded OFDM (COFDM), is a frequency-division multiplexing (FDM) scheme utilized as a digital multi-carrier modulation method. A large number of closely-spaced orthogonal sub-carriers are used to carry data. The data is divided into several parallel data streams or channels, one for each sub-carrier. Each sub-carrier is modulated with a conventional modulation scheme (such as quadrature amplitude modulation or phase-shift keying) at a low symbol rate, maintaining total data rates similar to conventional single-carrier modulation schemes in the same bandwidth. With the rapid growth of digital communication in recent years, the need for high-speed data transmission has been increased. The mobile telecommunications industry faces the problem of providing the technology that can be able to support a variety of services ranging from voice communication with a bit rate of a few kbps to wireless multimedia in which bit rate up to 2 Mbps. Many systems have been proposed and OFDM system has gained much attention for different reasons. Although OFDM was first developed in the 1960s, only in recent years, it has been recognized as an outstanding method for high-speed cellular data communication where its implementation relies on very highspeed digital signal processing. This method has recently become available with reasonable prices versus performance of hardware implementation. During the past 15 years, Orthogonal Frequency Division Multiplexing (OFDM) has been gaining year its after data year rate a well-deserved robustness reputation, to wireless demonstrating high and
environment capabilities. In the multipath environment, broadband communications will suffer from frequency selective fading.
The primary advantage of OFDM over single-carrier schemes is its ability to cope with severe channel conditions (for example, attenuation of high frequencies in a long copper wire, narrowband interference and frequency-selective fading due to multipath) without complex equalization filters. Channel equalization is simplified because OFDM may be viewed as using many slowly-modulated narrowband signals rather than one rapidly-modulated wideband signal. The low symbol rate makes the use of a guard interval between symbols affordable, making it possible to handle time-spreading and eliminate intersymbol interference (ISI). This mechanism also facilitates the design of single frequency networks (SFNs), where several adjacent transmitters send the same signal simultaneously at the same frequency, as the signals from multiple distant transmitters may be combined constructively, rather than interfering as would typically occur as in a traditional single-carrier system. Since OFDM is carried out in the digital domain, there are several methods to implement the system. One of the methods to implement the system is using ASIC (Application Specific Integrated Circuit). ASICs are the fastest, smallest and lowest power way to implement OFDM into hardware. The main problem using this method is inflexibility of design process involved and the longer time to market . Another method that can be used to implement OFDM is general purpose Microprocessor or Micro Controller. Power PC 7400 and DSP Processor is an example of microprocessor that is capable to implement fast vector operations. This processor is highly programmable and flexible in term of changing the OFDM design into the system. The disadvantages of using this hardware are, it needs memory and other peripheral chips to support the operation. Beside that, it uses the most power usage and memory space, and would be the slowest in term of time to produce the output compared to other hardware.
1.2 Motivation:
With the rapid growth of digital wireless communication in recent years, the need for high-speed mobile data transmission has increased. However, since power line was not originally designed to transmit data, the channel environment is very severe. Frequent turning on/off of surrounding devices generates numerous noises of large amplitude; on the other hand, the time-variant characteristics and multiple branches give rise to multipath during transmission of high-frequency signals.Consequently several kinds of fading were brought in, including frequency selective fading and fading due to Intersymbol Interference (ISI) . The existence of severe fading and noises combined has resulted in a high BER on the receiver end. New modulation techniques are being implemented to keep up with the desire of more communication capacity. Processing power has increased to a point where OFDM has become feasible and economical. Since many wireless communication systems being developed use OFDM, it is a worthwhile research topic. Some examples of current applications using OFDM include DAB (Digital Audio Broadcasting), HDTV broadcasting, IEEE 802.11 (wireless networking standard). Operating in an indoor environment, wireless networks face severe multipath and shadowing effects which can cause significant degradations in bit error rate (BER). OFDM is a good candidate for wireless networks because it performs well in combating interference and hence allows uncoordinated co-existence of wireless networks in the presence of noise from appliances. OFDM has been shown to behave efficiently in the indoor as well as outdoor environment with fading. OFDM is an attractive modulation scheme used in broadband wireless systems that encounter large delay spreads. OFDM avoids temporal equalization altogether, using a cyclic prefix technique with a small penalty in channel capacity.
1.3 Objectives:
The main objectives of the research are: To design and implement OFDM Transmitter and Receiver for wireless networks and to work on the described report that involves design of all the sub modules and testing their respective logics in modelsim To synthesize the codes using Xlinx with meeting all the constraints and generating the netlist and the constraints files.
1.4a Problem statement:

Implementation of OFDM Transmitter and Receiver (Orthogonal Frequency Division Multiplexing) for wireless networks .
1.4b Problem definition:

The aim of this project is to Design and Implementation of Orthogonal Frequency division multiplexing which satisfies high throughput, low transmission power, overcome the indoor as well as outdoor multi-path effects and are minimize the effect of harsh channel conditions. The design specifications are obtained from Literature Review and Software reference model. The VHDL coding is carried for the design to be implemented on FPGA (Up to synthesis level).
1.4c Analysis of the problem statement:

Wireless communication systems have to be designed to integrate features such as high data rates, high quality of service and multimedia in the existing communication framework.
1.4d Problems are solved by:

OFDM provides better spectrum flexibility by overlapping the signals on orthogonal frequencies. It is less noise sensitive than a single-carrier system. And the ISI problem is solved with the insertion of guard interval and the cyclic prefix. OFDM is a promising technique for wireless networks because it performs well in combating interference and hence allows networks in the presence of noise and other disturbances.
1.5 Methodology Adopted :

To review the literature on OFDM transmitter and receiver. To develop and simulate software reference model for OFDM Transceiver to meet derived specification. To analyze the performance of the algorithm from software model and choose an algorithm and architecture feasible and suitable for hardware implementation. To design and simulate hardware module of the OFDM transceiver to meet derived specification. To implement and verify the OFDM transceiver on FPGA.
1.6 Tools and languages used : 1.6a Tools used:

1. Modelsim Software Version 6.4b: used for simulation of codes. 2. Xilinx ISE version 10.1: used for synthesis of codes.
1.6b Language used:

VHDL it is easy for designing complex circuits Advantages of VHDL over VERILOG: There are now two industry standard hardware description languages, VHDL and Verilog. The complexity of ASIC and FPGA designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and mega cells written in either VHDL or Verilog. As a result, it is important that designers know both VHDL and Verilog and that EDA tools vendors provide tools that provide an environment allowing both languages to be used in unison. For example, a designer might have a model of a PCI bus interface written in VHDL, but wants to use it in a design with macros written in Verilog.
1.7 Project Workflow:

Literature review on algorithms and architecture for OFDM transmitter and receiver. Design specification of OFDM transceiver was formulated based on application and reviewed literature. Suitable algorithm and architecture for OFDM transceiver was identified as per the specifications and reviewed literature. Modules and Sub-modules of the OFDM transceiver were designed and modeled in VHDL and simulated using MODELSIM.
Test bench for verification of the complete OFDM transceiver was developed in VHDL. Modules and Sub-modules of the OFDM transceiver were synthesized using XILINX tool . Computational results obtained from simulations of software and hardware models were verified. OFDM transreceiver was implemented in FPGA. Documentation and report writing.
1.8 Design specifications:

The design specifications of OFDM transreceiver (according to IEEE 802.11b protocol) are: The transmitting frequency of the design is 600MHz which is done by modulating the transmitted signal of OFDM transceiver again with 600MHz. the data transmission rate are up to 11Mbyte/sec. Parameter Operating Frequency Band Symbol F Value 470862MHz
Transmitting Frequency Total Band width Number of Channels Band width per Channel Radio Coverage Range
TX BW N bw R
600 MHz 75MHz 8 20-40MHz 10M
1.9 Organisation of the thesis:

In this project report, the documentation is organized with a total of 6 chapters.
Chapter 1 : This chapter discusses the general idea of the project which covers the introduction, motivation, problem definition , objective of the project and an overview of project flow. Chapter 2 : Chapter 2 shows the literature review of the OFDM system, basic principles of OFDM system, advantages and disadvantages of OFDM system, and lastly is the application of the OFDM in recent technology. Chapter 3 : 3rd chapter describes the methodology of the project. The project is divided into several stages which basically include study relevant topics, design stage, implementation stage and testing stage. Further description will cover in this chapter. Chapter 4 : 4th Chapter explains the hardware design which is developed from mathematical equations. The chapter also includes on the theoretical part of FFT and IFFT and describes until the hardware design. Design and implementation of hardware model of OFDM along with the functional simulation of the design is also covered in this chapter. Chapter 5 : Design and implementation of hardware model of OFDM algorithm along with functional simulation of the design and testing of the design. This chapter enlightens the software design process involved in the project. This part basically discussed on the works involved to download the modules into FPGA board. Besides that, development of test vector which is used to test the modules will be carried out in this chapter. Chapter 6 : The conclusions drawn based on the implementation of this project and recommendations for future work.This chapter shows the results obtained from the FPGA hardware. The results obtained are captured and show in the figure as an examples.
CHAPTER 2: LITERATURE SURVEY
2.1 Concept:
With the rapid growth of digital communication in recent years, the need for high-speed data transmission has increased. The mobile telecommunications industry faces the problem of providing the technology that can be able to support a variety of services ranging from voice communication with a bit rate of a few kbps to wireless multimedia in which bit rate is up to 2 Mbps. Many systems have been proposed and OFDM system has gained much attention for different reasons. Although OFDM was first developed in the 1960s, only recently it has been recognized as an outstanding method for high-speed
cellular data communication where its implementation relies on very high-speed digital signal processing. During the past 15 years, Orthogonal Frequency Division Multiplexing (OFDM) has been gaining year after year a well-deserved reputation, demonstrating its high data rate and robustness to wireless environments capabilities. In the multipath environment, broadband communications will suffer from frequency selective fading. OFDM is an attractive modulation scheme used in broadband wireless systems that encounter large delay spreads. OFDM avoids temporal equalization altogether, using a cyclic prefix technique with a small penalty in channel capacity. Where Line-of-Sight (LoS) cannot be achieved, there is likely to be significant multipath dispersion, which could limit the maximum data rate. Technologies like OFDM are probably best placed to overcome these, allowing nearly arbitrary data rates on dispersive channels.
2.2 Multichannel Transmission:

OFDM started in the mid 60s, Chang [17] proposed a method to synthesis band limited signals for multi channel transmission. The idea is to transmit signals simultaneously through a linear band limited channel without inter channel (ICI) an inter symbol interference (ISI). After that, Saltzberg performed an analysis based on Changs work and he concluded that the focus to design a multi channel transmission must concentrate on reducing crosstalk between adjacent channels rather than on perfecting the individual signals. In 1971, Weinstein and Ebert made an important contribution to OFDM. Discrete Fourier transform (DFT) method was proposed to perform the base band modulation and demodulation. DFT is an efficient signal processing algorithm. It eliminates the banks of sub carrier oscillators. They used guard space between symbols to combat ICI and ISI problem. This system did not obtain perfect orthogonality between sub carriers over a dispersive channel. It was Peled and Ruiz in 1980 who introduced cyclic prefix [4] that solves the orthogonality issue. They filled the guard space with a cyclic extension of the OFDM symbol. It is assumed that the CP is longer than impulse response of the channel.
2.3 Basic Principles of OFDM:
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With standard single carrier transmitters, the signal is spread into multiple transmission paths, multiple frequencies. Because of the environment (buildings, cars, distance), the signal becomes less powerful and distorted. This phenomenon, called fading , appears when signals are reflected on the buildings for example. The reflected signals arrive to the receiver later than the main signal, which results in distortions. These distortions are a major problem when establishing secured high speed data transfer like used on the 3G UMTS cell phones. OFDM settles this distortion problem. It is not avoiding reflections but itscharacteristics make a transmission safer, in the meaning that data packets are always present by permiting to send multiple signals by a single radio channel. OFDM is a multi-carrier transmitter/receiver, i.e. it can send/receive signals to/from several users. Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier transmission technique, which divides the available spectrum into many carriers, each one being modulated by a low rate data stream. OFDM is similar to FDMA in which the multiple user access is achieved by subdividing the available bandwidth into multiple channels that are then allocated to users . However, OFDM uses the 10 spectrum much more efficiently by spacing the channels much closer together. This is achieved by making all the carriers orthogonal to one another, preventing interference between the closely spaced carriers.
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Fig 2.1 FDMA[ 8]
An OFDM signal consists of N subcarriers spaced by the frequency distance f thus, the total system bandwidth B is divided into N equidistant subchannels.On each subcarrier, the symbol duration Ts = 1/f is N times as large as in the case of a single carrier transmission system covering the same bandwidth.
Fig. 2.2 Bandwidth divided into N subchannels[8 ] OFDM is a multi-carrier transmission technology. It utilizes N subcarriers to divide the whole channel into N subchannels and a high-speed serial data stream is transformed into multiple low-speed data streams in parallel [16], as is shown in Fig. 2.2. Consequently, this multi-channel transmission elongates the duration period of the signal to be transmitted, thus alleviates the ISI caused by multipath propagation. When the total number of subchannels is sufficient, every subchannel can be considered as a one without ISI, thus the receiver end can enable a non-ISI transmission without complicated equalization techniques. In addition, OFDM provides strong resistance against frequency-selective fading. Each subchannel can choose different modulation methods in
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response to channel characteristics, which maximizes the influence of the channels that have low Signal to Noise Ratio (SNR) to other channels [24]. The system performance in transmission is then ensured.
2.4 Orthogonality Defined:

In OFDM modulation, the interval between two adjacent subcarrier waves is required to meet the orthogonality, namely, the product of two subcarrier waves is zero during a symbol period. Normally, we set the interval to be equal to the reciprocal of one symbol period, as is shown in Fig. 2.3. We can find that the peak of each subcarrier wave is located at the zero point of other subcarrier waves, thus the othogonality is satisfied.
Fig 2.3 The structure of OFDM modulator[5]
In OFDM, the sub-carrier frequencies are chosen so that the sub-carriers are orthogonal to each other, meaning that cross-talk between the sub-channels is eliminated and intercarrier guard bands are not required. This greatly simplifies the design of both the transmitter and the receiver; unlike conventional FDM, a separate filter for each subchannel is not required. The orthogonality requires that the sub-carrier spacing is Hertz, where TU seconds is the useful symbol duration (the receiver side window size), and k is a positive
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integer, typically equal to 1. Therefore, with N sub-carriers, the total passband bandwidth will be B Nf (Hz). The orthogonality also allows high spectral efficiency, with a total symbol rate near the Nyquist rate for the equivalent baseband signal (i.e. near half the Nyquist rate for the double-side band physical passband signal). Almost the whole available frequency band can be utilized. OFDM generally has a nearly 'white' spectrum, giving it electromagnetic interference properties with respect to other co-channel users. A simple example: A useful symbol duration TU = 1 ms would require a subcarrier spacing of (or an integer multiple of that) for orthogonality. N = 1,000 sub-carriers would result in a total passband bandwidth of Nf = 1 MHz. For this symbol time, the required bandwidth in theory according to Nyquist is N/2TU = 0.5 MHz (i.e., half of the achieved bandwidth required by our scheme). If a guard interval is applied, Nyquist bandwidth requirement would be even lower. The FFT would result in N = 1,000 samples per symbol. If no guard interval was applied, this would result in a base band complex valued signal with a sample rate of 1 MHz, which would require a baseband bandwidth of 0.5 MHz according to Nyquist. However, the passband RF signal is produced by multiplying the baseband signal with a carrier waveform (i.e., double-sideband quadrature amplitude-modulation) resulting in a passband bandwidth of 1 MHz. A single-side band (SSB) or vestigial sideband (VSB) modulation scheme would achieve almost half that bandwidth for the same symbol rate (i.e., twice as high spectral efficiency for the same symbol alphabet length). It is however more sensitive to multipath interference. Orthogonality is defined for both real and complex valued functions. The functions (m)t and (n)t are said to be orthogonal with respest each other over the interval a< t <b if they satisfy the condition:
OFDM splits the available bandwidth into many narrowband channels (typically 1008000), each with its own sub-carrier. These sub-carriers are made orthogonal to one
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another, meaning that each one has an integer number of cycles over a symbol period. Thus the spectrum of each sub-carrier has a null at the centre frequency of each of the other sub-carriers in the system, as demonstrated in Figure 2.4 below. This results in no interference between the sub-carriers, allowing them to be spaced as close as theoretically possible. Because of this, there is no great need of the channel to be timemultiplexed, and there is no overhead associated with switching between users. This overcomes the problem of overhead carrier spacing required in FDMA.
2.4 Orthogonality of sub-carrier[7]
2.5 OFDM Carriers:

As fore mentioned, OFDM is a special form of Multi Carrier Modulation (MCM) and the OFDM time domain waveforms are chosen such that mutual orthogonality is ensured even though sub-carrier spectra may over-lap. With respect to OFDM, it can be stated that orthogonality is an implication of a definite and fixed relationship between all carriers in the collection. It means that each carrier is positioned such that it occurs at the
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zero energy frequency point of all other carriers. Actually, FDM systems have been common for many decades. However, in FDM, the carriers are all independent of each other. There is a guard period in between them and no overlap whatsoever. This works well because in FDM system each carrier carries data meant for a different user or application. FM radio is an FDM system. FDM systems are not ideal for what we want for wideband systems. Using FDM would waste too much bandwidth. This is where OFDM makes sense. In OFDM, subcarriers overlap. They are orthogonal because the peak of one subcarrier occurs when other subcarriers are at zero. This is achieved by realizing all the subcarriers together using Inverse Fast Fourier Transform (IFFT).
Fig 2.5 OFDM Sub Carrier Spacing[ 8 ] The demodulator at the receiver parallel channels from an FFT block. Note that each subcarrier can still be modulated independently. This orthogonality is represented in Figure 2.5. Ultimately ISI is conquered. Provided that orthogonality is maintained, OFDM systems perform better than single carrier systems particularly in frequency
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selective channels. Each subcarrier is multiplied by a complex transfer function of the channel and equalising this is quite simple.
2.6.Guard Period:
An OFDM system can experience fades just as any other system. Thus coding is required for all subcarriers. We do get frequency diversity gain because not all subcarriers experience fading at the same time. Thus a combination of coding and interleaving gives us better performance in a fading channel. Higher performance is achieved by adding more subcarriers but this is not always possible. Adding more subcarriers could lead to random FM noise resulting in a form of time-selective fading. Practical limitations of transceiver equipment and spectrum availability mean that alternatives have to be considered. One alternative is to add a guard band in the time domain to allow for multipath delay spread. Thus, symbols arriving late will not interfere with the subsequent symbols. This guard time is a pure system overhead. The guard time must be designed to be larger than the expected delay spread. Reducing ISI from multipath delay spread thus leads to deciding on the number of subcarriers and the length of the guard period. Frequency-selective fading of the channel is converted to frequency-flat fading on the subcarriers. Since orthogonality is important for OFDM systems, synchronization in frequency and time must be extremely good. Once orthogonality is lost we experience inter-carrier interference (ICI). This is the interference from one subcarrier to another. There is another reason for ICI. Adding the guard time with no transmission causes problems for IFFT and FFT, which results in ICI. One of the most important properties of OFDM transmission is its robustness against multi path delay. This is especially important if the signals sub-carriers retain their orthogonality through the transmission process. The addition of a guard period between transmitted symbols can be used to accomplish this. The guard period allows time for multipath signals from the previous symbol to dissipate before information from the current symbol is recorded. The most effective guard period is a cyclic prefix, which is appended at the front of every OFDM symbol and is equal or greater than the maximum delay spread of the channel. Although the insertion of the cyclic prefix imposes a penalty on bandwidth efficiency, it is often the best compromise between performances and efficiency in the presence of inter-symbol interference. A delayed version of one subcarrier can interfere with another subcarrier in the next symbol period. This is avoided by extending the symbol into the guard period that
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precedes it.Cyclic prefix ensures that delayed symbols will have integer number of cycles within the FFT integration interval. This removes ICI so long as the delay spread is less than the guard period. We should note that FFT integration period excludes the guard period.
Fig 2.6 Implementation of Cyclic Prefix[7]
2.7Advanced Techniques:
Although subcarriers are orthogonal, a rectangular pulse shaping gives rise to a sinc shape in the frequency domain. Side lobes delay slowly producing out-of-band interference. If frequency synchronization error is significant, this can result in further degradation of performance due to these side lobes. The idea of soft pulse shaping has been studied such as using Gaussian functions. Although signal decays rapidly from the carrier frequency, the problem is that orthogonality is lost. ISI and ICI can occur over a few symbols. Therefore equalization must be performed. There are two advantages equalization gives diversity gain and soft impulse shaping results in more robustness to synchronization errors. However, diverisy gain can be obtained with proper coding and out-of-band interference can be limited by filtering. Thus, the technique of channel estimation and equalization seems unnecessary for OFDM systems [2].
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Fig 2.7 fu is the sub-carrier spacing OFDM sub carriers in the frequency domain[7]
Frame and time synchronization could be achieved using zero blocks (no transmission). Training blocks could be used. Periodic symbols of known patterns could be used. These serve to provide a rough estimate of frame timing. The guard period could be used to provide more exact synchronization. Frequency synchronization is important to minimize ICI. Pilot symbols are used to provide an estimate of offsets and correct for the same. Pilot symbols are used where fast synchronization is needed on short frames. For systems with continuous transmission, synchronization without pilot symbols may be acceptable if there is no hurry to get synchronized.
One of the problems of OFDM is a high peak-to-average ratio. This causes difficulties to power amplifiers. They generally have to be operated at a large back off to avoid out-of-band interference. If this interference is to be lower than 40 dB below the power density in the OFDM band, an input back off of more than 7.5 dB is required [2]. Crest factor is defined as the ratio of peak amplitude to RMS amplitude. Crest factor reduction (CFR) techniques exist so that designers are able to use a cheaper PA for the same performance. Some approaches to CFR are described briefly below: Only a subset of OFDM blocks that are below an amplitude threshold are selected for transmission. Symbols outside this set are converted to the suitable set by adding redundancy. These redundant bits could also be used for error correction. In practice, this is method is practical only for a few subcarriers. Each data sequence can be represented in more than one way. The transmitter chooses one that minimizes the amplitude. The receiver is indicated of the choice.
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Clipping is another technique. Used with oversampling, it causes out-of-band interference which is generally removed by FIR filters. These filters are needed anyway to remove the side lobes due to rectangular pulse shaping. The filter causes new peaks (passband ripples) but still peak-to-average power ratio is reduced. Correcting functions are applied to the OFDM signal where peaks are seen while keep out-of-band interference to a minimum. If many peaks are to be corrected, then entire signal has to be attenuated and therefore performance cannot be improved beyond a certain limit. A similar correction can be done by using a additive function (rather than multiplicative) with different results.
One of the problems of filtering an OFDM signal is the passband ripple. It is well-known in filter design theory that if we want to minimize this ripple, the number of taps on the filter should be increased. The trade-off is between performance and cost-complexity. A higher ripple leads to higher BER. Ripple has a worse effect in OFDM systems because some subcarriers get amplified and others get attenuated. One way to combat this is to equalize the SNR across all subcarriers using what is called digital pre-distortion (DPD). Applying DPD before filtering increases the signal power and hence out-of-band interference. The latter must be limited by using a higher attenuation outside the passband as compared to a system without predistortion.
2.8 Generation of OFDM Signals:

To implement the OFDM transmission scheme, the message signal must first be digitally modulated. The carrier is then split into lower-frequency sub-carriers that are orthogonal to one another. This is achieved by making use of a series of digital signal processing operations. The message signal is first modulated using a scheme such as BPSK, QPSK or some form of QAM (16QAM or 64QAM for example). In BPSK, each data symbol modulates the phase of a higher frequency carrier. Figure 2.8 shows the time-domain representation of 8 symbols (01011101) modulated within a carrier using BPSK. In the frequency domain, the effect of the phase shifts in the carrier is to expand the bandwidth occupied by the BPSK signal to a sinc function. The zeros (or nulls) of the sinc frequency occur at intervals of the symbol frequency.
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2.8. Binary Phase-Shift Key (BPSK) representation of 0101101[7]
Originally, multi-carrier systems were implemented through the use of separate local oscillator . This was both efficient and costly. With the advent of cheap powerful processors, the sub-carriers can now is that the FFT can keep tones orthogonal to one another if the tones have an integer number of cycles in a symbol period. In the example figure 2.9, we see signals to generate each individual sub-carrier can be now generated using Fast Fourier Transforms (FFT). The FFT is used to calculate the spectral content of the signal. It moves a signal from the time domain where it is expressed as a series of time events to the frequency domain where it is expressed as the amplitude and phase of a particular frequency. The inverse FFT (IFFT) performs the reciprocal operation.
Figure 2.9: A set of orthogonal signals[7]
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To convert the sub-carriers to a set of orthogonal signals, the data is first combined into frames of a suitable size for an FFT or IFFT. A FFT should be always in the length of 2N (where N is an integer). Next, an N-point IFFT is performed and the data stream is the output of the transmitter. Thus when the signals of the IFFT output are transmitted sequentially, each of the N channel bits appears at a different sub-carrier frequency. By using an IFFT process, the spacing of the sub carriers is chosen in such a way that at the frequency where the received signal is evaluated, all other signals is zero. In order for this orthogonality, the receiver and the transmitter must be perfectly synchronized. This means they both must assume exactly the same modulation frequency and the same time-scale for transmission. At the receiver, the ions are performed to recover the data. Since the FFT is performed in this stage, the data is back in the frequency domain. It is then demodulated according to the block diagram .
Fig 2.10: OFDM Transceiver System[7]
2.9 More Details on Cyclic Perfix:
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An OFDM signal consists of N subcarriers spaced by the frequency distance f thus, the total system bandwidth B is divided into N equidistant subchannels.On each subcarrier, the symbol duration Ts = 1/ f is N times as large as in the case of a single carrier transmission system covering the same bandwidth. Additionally, each subcarrier signal is extended by a guard interval called cyclic prefix with the length Tg. All subcarriers are mutually orthogonal within the symbol duration Ts. For each subcarrier a rectangular pulse shaping is applied. The guard interval or cyclic extension is added to the subcarrier signal in order to avoid Inter-Symbol Interference (ISI), which occurs in multipath channels. At each Receiver the cyclic prefix is removed and only the time interval [0, Ts ] is evaluated. The total OFDM block duration is T = Ts + Tg. Each subcarrier can be modulated independently. The spectra of the subcarriers overlap, but the subcarrier signals are mutually orthogonal, and the modulation symbol can be recovered by a simple correlation.
Fig. 2.10 Cyclic Extension[4]
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Fig.2.11 OFDM subcarriers representation[4] In a practical application, the OFDM signal is generated in a first step as a discrete-time signal in the digital signal processing part of the Transmitter. As the bandwidth of an OFDM system is B = N_f , the signal must be sampled with sampling time t = 1/B = 1/N_f . The samples of the signal can be calculated by an Inverse DFT (IDFT) which is typically implemented as an Inverse FFT (IFFT). The subcarrier orthogonality is not affected at the output of a frequency selective radio channel; therefore, the received signal can be separated into the orthogonal subcarrier signals by a correlation technique. Alternatively, the correlation at Receiver can be done as a Discrete Fourier Transform (DFT) or a Fast Fourier Transform (FFT) respectively. If the subcarrier spacing _f is chosen to be much smaller than the coherence bandwidth, and if the symbol duration T is much smaller than the coherence time of the channel, then the transfer function of the radio channel can be considered constant within the bandwidth of each subcarrier and the duration of each modulation symbol. In this case, the effect of the radio channel is only a multiplication of each subcarrier signal by a gain factor. Also channel coding plays an important role in OFDM systems. Due to the narrowband subcarriers and the appropriate cyclic prefix, OFDM systems suffer from flat fading. In this situation, efficient channel coding leads to a very high coding gain, especially if soft decision decoding is applied. For this reason , OFDM systems will always have to make use of channel coding. OFDM signals have a large peak-to-average power ratio (PAPR) due to the superposition of all subcarrier signals. Therefore, in each Transmitter the power amplifier will limit the OFDM signal by its maximal output power. This also disturbs the orthogonality between subcarriers, leading to both intercarrier and out-of-band interferences, which is unacceptable.
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Although the principle of OFDM communication has been around for several decades, it was only in the last decade that it started to be used in commercial systems. The most important wireless applications that make use of OFDM are Digital Audio Broadcast (DAB), DVB, WLAN.
2.10 Digital Modulation Methods:

Modern cellular systems use digital modulation methods, as this has several advantages over analogue transmission, including the possibility to apply advanced signal processing, such as error correction coding, security and diversity.
Example of popular narrowband modulation methods are:
Binary Phase Shift Keying (BPSK) o BPSK with pulse shaping

o
BER of BPSK in mobile cellular channel
Quadrature Phase Shift Keying (QPSK) QAM (PDF slides on implementation) Continuous Phase Shift Keying
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G-MSK, for instance used in GSM
Other methods are : Multi-Carrier Transmission, in particular OFDM and multi-carrier CDMA . Direct Sequence CDMA .
2.11 What Modulation Suits the Channel?

Multipath reception and user mobility lead to channel behavior that is time and frequency dependent. In the following frequency-time diagrams, we depict where in frequency and when in time most of the bit energy is located. It is important to select a modulation scheme that is appropriate for the Doppler spread and the delay spread
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of the channel. It is seen from the channel scatter function or from samples of the channel that:

Doppler leads to time variations of the channel, and broadening of signals bandwidth. Delay spreads lead to intersymbol interference and frequency selective fading
. Fig: 2.11
Frequency Time plot[ 9] In the frequency-time plot, every tile represents one bit. In spread-spectrum transmission one bit is often transmitted in multiple 'chips'. Below, one such chip is plotted as a tile. One bit is spread over multiple tiles. In narrowband communication (NB), the occupied bandwidth is small and the bit duration is long. The bit energy footprint is stretched in vertical direction. Intersymbol interference is neglectable in the bit duration , say, ten times or more longer than the delay spread. However, due to multipath the entire signal (bandwidth) may vanish in a deep fade. If fading is very fast, the channel may change during a bit transmission. This can occur if the Doppler spread is large compared to the transmit bandwidth. In wideband transmission (WB), i.e., transmission at high bit rate, the signal is unlikely to vanish completely in a deep fade, because its bandwidth is so wide that some components will be present at frequencies where the channel is good. Such frequency selective fading, however, leads to intersymbol interference, which must be handled, for instance by an adaptive equalizer.
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In OFDM or multicarrier systems, multiple bits are transmitted in parallel over multiple subcarriers. If one subcarrier is in a fade, the other may not. Error correction coding can be used to correct bit errors on faded subcarriers. Rapid fading (Doppler) may erode the orthogonality of closely spaced subcarriers. Direct sequence intentionally broadens the transmit spectrum by multiplying user bits with a fast random sequence. The wideband signal is unlikely to fade completely. If frequency selective fading occurs, the receiver sees a series of time-shifted versions of the chipped bit. A receiver can separate the individual resolvable paths.
Frequency hopping: The carrier frequency is shifted frequently, to avoid fades or narrowband interference. While the signal may vanish during one hop to a particular frequency, most likely other hops are at frequencies in which the channel is good. Error correction is applied to correct bits lost at faded frequencies. Slow and fast hopping methods differ in the relative duration spent at one frequency, compared to the user bit duration. Orthogonal multicarrier spread spectrum is a spectrum-spreading method to exploits advantages of OFDM and DS-CDMA where each user bit is transmitted simultaneously and in parallel over multiple subcarriers. This corresponds to a 90 degree rotation of a bit energy map in the frequency-time plane. While the signal may loose some subcarriers, reliable communication is ensured through appropriate combining of energy from various subcarriers, taking into account the signalto-interference ratios. In an interference-free environment, maximum ratio diversity combining is the preferred receive strategy. Signal pulse shapes usually are chosen to satisfy the following requirements :

Bandwidth limitations (e.g. sinc shaped pulses) Zero crossings of one pulse coincide with sample moments of other pulses (e.g. sinc pulses or raised cosines) Rapid decrease of pulse energy outside the main bit interval (e.g. raised cosine) Appropriate to use with matched filters (e.q. Nyquist pulses)
2.12 OFDM Advantages and Disadvantages:

The major advantage of OFDM is its robustness against multi path propagation. Thus, it is suitable to be implemented in wireless environments. The introduction of cyclic prefix made OFDM system resistance to time dispersion. OFDM symbol rate is low because a data stream is divided into several parallel streams before transmission. This makes the
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fading slow enough for the channel to be considered as constant during one OFDM symbol interval. Cyclic prefix is a crucial feature of OFDM used to combat the inter-symbol interference (ISI) and inter-channel-interference (ICI) introduced by the multi-path channel through which the signal is propagated. The basic idea is to replicate part of the OFDM timedomain waveform from the back to the front to create a guard period. The duration of the guard period Tg should be longer than the worst-case delay spread of the target multipath environment. The use of a cyclic prefix instead of a plain guard interval, simplifies the channel equalization in the demodulator. In wire system, OFDM system can offer an efficient bit loading technique. It enables a system to allocate different number of bits to different sub channels based on their individual SNR. Hence, an efficient transmission can be achieved. One of the major disadvantages of OFDM is its requirement for high peak-to average- power ratio. This put high demand on linearity in amplifiers. Second, the synchronization error can destroy the orthogonality and cause interference. Phase noise error and Doppler shift can cause degradation to OFDM system. A lot of effort is required to design accurate frequency synchronizers for OFDM.
2.13 OFDM Applications:

Initially, OFDM applications are scarce because of their implementation complexity. Now, OFDM has been adopted as the new European digital audio broadcasting (DAB) standard and for terrestrial digital video broadcasting (DVB) [6]. In fixed-wire applications, OFDM is employed in asynchronous digital subscriber line (ADSL) and high bit-rate digital subscriber line (HDSL) systems. It has been proposed for power line communications systems as well due to its resilience to dispersive channel and narrow band interference. Here is a brief discussion on 4 applications that has incorporated OFDM technique [7]: Digital Audio Broadcasting (DAB) DAB is the first standard to use OFDM. DAB network is efficient in handling multipath delay spread. As a result, improved CD quality sound, new data services and higher spectrum efficiency can be achieved.
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Terrestrial Digital Video Broadcasting (DVB) DVB was created by a pan-broadcasting-industry group in 1993. DVB defined a set of specifications for delivery of digital television over cable, DSL, and satellite. In 1997, Digital Terrestrial Television Broadcasting (DTTB) was standardized. It utilizes OFDM system in the 2000 and 8000 sub carrier modes. Magic WAND Magic WAND (Wireless ATM Network Demonstrator) is a wireless OFDM based ATM network. This system operates in 5 GHz band is gaining acceptance for OFDM in highrate wireless communications. It also acts as basis for HiperLAN2. IEEE802.11a/HiperLAN2 and MMAC Wireless LAN All the above system operates in 5GHz band. 802.11a is selected by IEEE to be used in US targeting a range of data rates up to 54 Mbps. ETSI BRAN in Europe is working on 3 extensions for OFDM in HiperLAN standard: (i) HiperLAN2, a wireless indoor LAN with a Quos provision; (ii) Hyperlink, a wireless indoor backbone; and (iii) HiperAccess, an outdoor fixed wireless network providing access to a wired infrastructure. MMAC is developed by Japan. It is a standard similar to IEEE and ETSI BRAN.
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CHAPTER 3: OFDM DETAILS
3.1 Aim of the Project and its Importance:

The main aim of the project is to give an idea of what is an OFDM system, its implementation and the analysis of the obtained results of the simulations and the hardware testing. This OFDM system is able to support different modulation schemes. This project will focus on Orthogonal Frequency Division Multiplexing (OFDM) research, simulation, and implementation. OFDM is a modulation technique especially suitable for wireless communication due to its resistance to inter-symbol interference (ISI). After researching OFDM, simulation in MATLAB will be completed. The main part of this project will be using the simulation results as a guide to implement OFDM on a FPGA board.
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Depending on the FPGA hardware used, the MATLAB code will need to be converted to either C or Simulink. This makes our code compatible with the software tool for that particular FPGA board. To test the FPGA code, we will verify that the input and output vectors of the MATLAB simulation and FPGA implementation correspond.
Importance:
With the rapid growth of digital wireless communication in recent years, the need for high-speed mobile data transmission has increased. New modulation techniques are being implemented to keep up with the desire communication capacity. Processing power has increased to a point where OFDM has become feasible and economical. Since many wireless communication systems being developed, OFDM is a worthwhile research topic. Some examples of current applications using OFDM include DAB (Digital Audio Broadcasting), HDTV broadcasting, IEEE 802.11 (wireless networking standard).
3.2 More about OFDM:

Orthogonal frequency division multiplexing (OFDM) has become a popular technique for transmission of signals over wireless channels. OFDM is being pursued for dedicated short range communications (DSRC) for road side to vehicle communications and as a potential candidate for the fourth generation (4G) mobile wireless systems. OFDM converts a frequency selective channel into a parallel collection of frequency flat sub-channels. The subcarriers have the minimum frequency separation required to maintain orthogonality of their corresponding time domain waveforms, yet the signal spectra corresponding to the different subcarriers overlap in frequency. Hence, the available bandwidth is used very efficiently. If knowledge of the channel is available at the transmitter, then the OFDM transmitter can adapt its signaling strategy to match the channel. Due to the fact that OFDM uses a large collection of narrowly spaced subchannels, these adaptive strategies can approach the ideal water pouring capacity of a frequency selective channel. In practice this is achieved by using adaptive bit loading techniques, where different sized signal constellations are transmitted on the subcarriers. OFDM is a block modulation scheme where a block of N information symbols is transmitted in parallel on N subcarriers. The time duration of an OFDM symbol is N times larger than that of a single carrier system. An OFDM modulator can be implemented as an inverse discrete Fourier transform (IDFT) on a block of N information symbols followed by an analog to digital converter (ADC). To mitigate the effects of intersymbol interference (ISI) caused by channel time spread, each block of N
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IDFT coefficients is typically preceded by a cyclic prefix (CP) or a guard interval consisting of G samples, such that the length of the CP is at least equal to the channel length, M. Under this condition, a linear convolution of the transmitted sequence and the channel is converted to a circular convolution. As a result, the effects of the ISI are easily and completely eliminated. Moreover, the approach enables the receiver to use fast signal processing transforms such as a fast Fourier transform (FFT) for OFDM implementation [3].Similar techniques can be employed in single carrier systems as well, by preceding each transmitted data block of length N by a cyclic prefix of length G, while using frequency domain equalization at the receiver.
3.3 OFDM and IEEE 802.11 :

IEEE 802.11 is a set of standards for implementing wireless local area network (WLAN) computer communication in the 2.4, 3.6 and 5 GHz frequency bands. They are created and maintained by the IEEE LAN/MAN Standards Committee (IEEE 802). The base current version of the standard is IEEE 802.11-2007. These standards provide the basis for Wi-Fi wireless networks. The 802.11 family consists of a series of over-the-air modulation techniques that use the same basic protocol. The most popular are those defined by the 802.11b and 802.11g protocols, which are amendments to the original standard. 802.11-1997 was the first wireless networking standard, but 802.11b was the first widely accepted one, followed by 802.11g and 802.11n. Security was originally purposefully weak due to export requirements of some governments,[1] and was later enhanced via the 802.11i amendment after governmental and legislative changes. 802.11n is a new multistreaming modulation technique. Other standards in the family (cf, h, j) are service amendments and extensions or corrections to the previous specifications. OFDM has been adopted in the IEEE802.11a LAN and IEEE802.16a LAN standards. OFDM is also being considered in IEEE802.20a, a standard-in-the-making for maintaining high-bandwidth connections to users moving at speeds up to 60 mph. The IEEE802.11a LAN standard operates at raw data rates up to 54 Mb/s (channel conditions permitting) with a 20 MHz channel spacing, thus yielding a bandwidth efficiency of 2.7 bits/s/Hz. The actual throughput is highly dependent on the medium access control (MAC) protocol.Likewise, IEEE802.16a operates in many modes depending on channel conditions with a data rate ranging from 4.20 Mb/s to 22.91 Mb/s in a typical bandwidth of 6 MHz, translating into a bandwidth efficiency of 0.7 to 3.82 bits/s/Hz.
3.4 Main blocks in an OFDM system:

OFDM distributes the data over a large number of carriers at different frequencies. This spacing provides the orthogonality which prevents the receivers to see wrong frequencies. In opposite to other multi-carriers techniques, like CDMA, OFDM prevents
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the Inter Symbol Interference (ISI) by adding a cyclic prefix, which is explained in section Inter-Symbol Interferences. One of the key features of OFDM is the IFFT/FFT pair. These two mathematical tools are used hereto transform several signals on different carriers from the frequency-domain to the time-domain in the IFFT (or FFT1) and from the time-domain to the frequencydomain in the FFT . Figure 3.1, with the main parts of an OFDM system.
Fig 3.1: Block Diagram of OFDM
3.5 OFDM Transmitter:

The model considered for the implementation of the OFDM transmitter is the shown in the Fig. 3.2 and basically consist of the following blocks:
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Fig 3.2 Simplified OFDM Transmitter
Serial to parallel converter. Constellation modulator The IFFT block Parallel to serial converter The serial to parallel converter receive the M serial bits to be transmitted, and those bits are divided into N subblocks of mn bits each subblock. Those N subblocks will be mapped by the constellation modulator using Gray codification, this way an + jbn values are obtained in the constellation of the modulator. The M-QAM encoder converts input data into complex valued constellation points, according to a given constellation, 4QAM, 16-QAM, 32-QAM and so on. The amount of data transmitted on each subcarrier depends on the constellation, 4QAM and 16QAM transmit two and four data bits per subcarrier, respectively. Which constellation to use depends on the quality of the communications channel. In a channel with high interference a small modulation scheme like BPSK is favorable, since the required signal to noise ratio (SNR) in the receiver is low, whereas in a interference free channel a larger constellation is more beneficial due to the higher bit rate. It is necessary to specify how the constellation will be mapped to implement that block. However, independently of the format of the constellation, the block encoder can be
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made by consulting a conversion table, implemented with a LUT that exists in LCs of FPGAs. It is important to notice that in that mapping block, bits are converted into complex symbols (phasors) having the information of the constellation in its I, Q components. The Inverse Fast Fourier Transform (IFFT) transforms the signals from the frequency domain to the time domain, an IFFT converts a number of complex data points, of length that is power of 2, into the same number of points but in the time domain. The number of subcarriers determines how many sub-bands the available spectrum is split into. The CP is a copy of the last N samples from the IFFT, which are placed at the beginning of the OFDM frame. There are two reasons to insert a CP. Assuming that the CP is longer than the channels impulse response, the convolution between the data and the channel impulse response will act like a circular convolution and interference from the previous symbol will only affect the CP. The CP is then discarded in the receiver and the circular convolution makes equalization in the receiver easier. However, if the number of samples in the CP is large, the data transmission rate will decrease significantly, since the CP does not carry any useful data. Thus, it is important to choose the minimum necessary CP to maximize the efficiency of the system.
3.6 OFDM Receiver:

The blocks of the OFDM Receiver are shown in the Fig 3.3, and those blocks are: Serial to parallel converter. Cyclic prefix removal. The FFT block. M-QAM decoder. Parallel to serial converter.
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Fig 3.3 Simplified OFDM Receiver The received symbol is in time domain and it can be distorted due to the effect of the channel. The received signal goes through a serial to parallel converter and cyclic prefix removal. After the cyclic prefix removal, the signals are passed through an N-point fast Fourier transform to convert the signal to frequency domain. The output of the FFT is formed from the first M samples of the output. The demodulation can be made by DFT, or better, by FFT, that is it efficient implementation that can be used reducing the time of processing and the used hardware. FFT calculates DFT with a great reduction in the amount of operations, leaving several existent redundancies in the direct calculation of DFT. At the decoder, a mapped symbol (point) of the transmitted constellation may have changed due to the additive noise in the communications channel, a misadjustment in the sampling time at the receiver, or several other unwanted causes.Therefore, it is necessary to define a threshold to facilitate the decision making in the receiver constellation. That is the function of the M-QAM decoder.
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CHAPTER 4: METHODOLOGY
4.1 Overview:
A common problem found in high-speed communication is inter-symbol interference (ISI). ISI occurs when a transmission interferes with itself and the receiver cannot decode the transmission correctly. For example, in a wireless communication system such as that shown in Figure 4.1, the same transmission is sent in all directions.
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4.1 Multipath Demonstration Because the signal reflects from large objects such as mountains or buildings, the receiver sees more than one copy of the signal. In communication terminology, this is called multipath. Since the indirect paths take more time to travel to the receiver, the delayed copies of the signal interfere with the direct signal, causing ISI. OFDM is especially suitable for high-speed communication due to its resistance to ISI. As communication systems increase their information transfer speed, the time for each transmission necessarily becomes shorter. Since the delay time caused by multipath remains constant, ISI becomes a limitation in high-data-rate communication [1]. OFDM avoids this problem by sending many low speed transmissions simultaneously. For example, Figure 4.2 shows two ways to transmit the same four pieces of binary data.
Fig 4.2 Traditional vs. OFDM Communication Suppose that this transmission takes four seconds. Then, each piece of data in the left picture has a duration of one second. On the other hand, OFDM would send the four
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pieces simultaneously as shown on the right. In this case, each piece of data has a duration of four seconds. This longer 3 duration leads to fewer problems with ISI. Another reason to consider OFDM is low-complexity implementation for high-speed systems compared to traditional single carrier techniques [2].
4.2 Design Methodology:

The design of OFDM Transceiver for wireless Networks is mainly done in 2 stages .That being 1. Verifying the logics and implementation of the codes in MODELSIM. 2. Synthesis of the same codes using XILINX This work involved from the design of the core processing block using 8 point Fast Fourier Transform (FFT) for receiver and 8 point Inverse Fast Fourier Transform (IFFT).The design also includes mapping block, serial to parallel and parallel to serial block set. All design need to be verified to ensure that VHDL programming should be error free before being simulated. The project was done up to simulation level using ModelSim software and it only consists of FFT and IFFT processing module. Some of the problem encountered by the design of FFT and IFFT is that it does not easily fit to FPGA hardware . The design uses a large number of gates and causes this problem to arise. Logic gates are greatly consumed if the number of multiplier and divider are increase. One method to overcome this problem is by decreasing the number of multiplier and divider in the VHDL design. Beside that, the design does not include control signal which causes difficulties in controlling the data processing in FFT or IFFT module. The control signal is use to select the process executed for each computation process during VHDL design. As a result, the design is not applicable for hardware implementation in the FPGA development board. New design is required to overcome this problem. Since the design is not possible to use, this project will concentrate on designing the FFT and IFFT module which can be implement in the dedicated FPGA board. To ensure that the program can be implemented, the number of gates used in the design must be small or at least less than the hardware can support. Otherwise the design module is not able to implement into the dedicated board.
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4.3 Transmitter/Receiver Design Model:

In order to use multiple sub-carriers to transmit an individual channel, an OFDM communications system must perform several steps, described in the figure below.
4.4 a Serial to Parallel Converter:
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The aim of the serial to parallel converter is to receive the data that is going to be transmitted. The serial to parallel converter receive the M serial bits to be transmitted, and those bits will be divided into N subblocks of mn bits each subbolck called symbols. The amount of bit of each channel can be different. Those N subblocks will be mapped by the constellation modulator using Gray codification, this way an + jbn values are obtained in the constellation of the modulator. The serial to parallel converter at the receiver has the function to receive the data that is going to be demodulated, with the same structure as it was at the transmitter. To store the M bits a buffer that will contain all the input data into different memory positions is needed. To obtain the M data bits at the output well need the buffer to stop reading data, another option is that the amount of data stored at the buffer is 2M, this way is not necessary to stop the reading, this way can read continuously the constellation of the modulator. In an OFDM system, each channel can be broken into various sub-carriers. The use of sub-carriers makes optimal use out of the frequency spectrum but also requires additional processing by the transmitter and receiver. This additional processing is necessary to convert a serial bitstream into several parallel bitstreams to be divided among the individual carriers. Once the bitstream has been divided among the individual sub-carriers, each sub-carrier is modulated as if it was an individual channel before all channels are combined back together and transmitted as a whole. The receiver performs the reverse process to divide the incoming signal into appropriate sub-carriers and then demodulating these individually before reconstructing the original bitstream.
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4.4b Parallel to Serial converter:
The parallel to serial converter is only the opposite function of the serial to parallel converter, and it is placed just before sending the data through the channel by the digital to analog converter, at the transmitter, and just the last block before obtaining the final data at the receiver.
4.4c Basic Concept of Modulation:

In electronics, modulation is the process of varying one or more properties of high frequency periodic waveform, called the carrier signal, with respect to a modulating signal. The three key parameters of a periodic waveform are its amplitude, its phase ("timing") and its frequency ("pitch"), all of which can be modified in accordance with a low frequency signal to obtain the modulated signal. Typically a highfrequency sinusoid waveform is used as carrier signal, but a square wave pulse train may also occur. 4.4.1c Digital modulation techniques: The aim of digital modulation is to transfer a digital bit stream over an analog passband channel, for example over the public switched telephone network (where a bandpass filter limits the frequency range to between 300 and 3400 Hz), or over a limited radio frequency band.
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In digital modulation, an analog carrier signal is modulated by a digital bit stream. Digital modulation methods can be considered as digital-to-analog conversion, and the corresponding demodulation or detection as analog-to-digital conversion. The changes in the carrier signal are chosen from a finite number of M alternative symbols (the modulation alphabet). The main function of modulator and the demodulator is to minimize the degrading effects of the channel on the signal and maximize the information rate and accuracy. In digital communication system the channel accepts electrical/electromagnetic signals, and the resultant output is distorted version of the input due to the non-ideal nature of the communication channel. Unpredictable noise also adds to the informationbearing signal which introduces errors in the information being transmitted and limits the rate at which information is to be communicated from the source to the destination. The probability of incorrectly decoding a message symbol at the receiver is often used as a measure of performance of digital communication systems. In digital modulation, information signals to be modulated is digital. Therefore, digital information modulates an analog carrier and hence called as digital modulation. These are the general steps used by the modulator to transmit data: 1. Group the incoming data bits into codeword, one for each symbol that will be transmitted. 2. Map the codeword to attributes, for example amplitudes of the I and Q signals (the equivalent low pass signal), or frequency or phase values.
3. Adapt pulse shaping or some other filtering to limit the bandwidth and form the
spectrum of the equivalent low pass signal, typically using digital signal processing.
4. Perform digital-to-analog conversion (DAC) of the I and Q signals (since today
all of the above is normally achieved using digital signal processing, DSP).
5. Generate a high-frequency sine wave carrier waveform, and perhaps also a cosine
quadrature component. Carry out the modulation, for example by multiplying the sine and cosine wave form with the I and Q signals, resulting in that the equivalent low pass signal is frequency shifted into a modulated passband signal or RF signal. Sometimes this is achieved using DSP technology, for example direct digital synthesis using a waveform table, instead of analog signal processing. In that case the above DAC step should be done after this step.
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6. Amplification and analog bandpass filtering to avoid harmonic distortion and periodic spectrum At the receiver side, the demodulator typically performs: 1. Bandpass filtering.
2. Automatic gain control, AGC (to compensate for attenuation, for
example fading).
3. Frequency shifting of the RF signal to the equivalent baseband I and Q signals, or
to an intermediate frequency (IF) signal, by multiplying the RF signal with a local oscillator sinewave and cosine wave frequency .Sampling and analog-todigital conversion (ADC) (Sometimes before or instead of the above point, for example by means of undersampling).
4. Equalization filtering, for example a matched filter, compensation for multipath
propagation, time spreading, phase distortion and frequency selective fading, to avoid intersymbol interference and symbol distortion. 5. Detection of the amplitudes of the I and Q signals, or the frequency or phase of the IF signal. 6. Quantization of the amplitudes, frequencies or phases to the nearest allowed symbol values. 7. Mapping of the quantized amplitudes, frequencies or phases to codewords (bit groups). 8. Parallel-to-serial conversion of the codewords into a bit stream. 9. Pass the resultant bit stream on for further processing such as removal of any error-correcting codes. There are basically three types of digital modulation techniques. Amplitude Shift Keying (ASK) Frequency Shift Keying (FSK) Phase Shift Keying (PSK)
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Amplitude shift keying (On-Off Keying):- Digital information alters the amplitude of the carrier between two distinct levels. This digital modulation method is also referred to as ON-OFF keying. The ON state is represented by 1 and the OFF state is represented as 0. Non-coherent method of detection is employed at the receiving end. The Fig2.7 shows the amplitude shift keying. The output is expressed as A (t)=A cos (wct+) for binary 1 (4.1)
Equation 2.1 gives the expression for ASK modulated wave.
Fig : Amplitude shift keying [8]
Frequency shift keying:- Frequency shift keying modulation incorporates two carrier frequencies for the transmission of two bits of binary data. Carrier frequency f1 corresponds to bit 1, and the carrier frequency f2 corresponds to bit 0, where the frequency f1 > frequency f2. The FSK waveform is expressed as F (t) = A cos w1t for binary 1 F(t) = A cos w2 t for binary 0 (4.2) (4.3)
Equation 4.2 and equation 4.3 gives the expression for FSK modulated wave. Frequency shift keying is shown in Fig.
Fig :Frequency shift keying [8] Phase shift keying:- This modulation technique is most used in present digital communication systems. In PSK modulation, the phase of the carrier is altered in
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accordance with the input binary coded information. The PSK is further subdivided 5 types. BPSK (Binary Phase Shift Keying): The modulated signal has 2 different phases. Constellation diagram of BPSK and BPSK modulated signal is shown in Fig
Fig :Constellation diagram for BPSK and BPSK modulated signal [9] QPSK (Quadrature Phase Shift Keying): The Modulated signal has four different phases. We can transmit two bits at a time in this type of modulation. Constellation diagram for QPSK and QPSK modulated Signal is shown in Fig
Fig :Constellation diagram for QPSK and QPSK modulated signal [9] DPSK (Differential Phase shift Keying): In DPSK modulation each bit is represented by one and a half cycle of sine wave. 8-PSK (8 Phase Shift Keying): The Modulated signal has eight different phases. We can transmit three bits at a time in this type of modulation. Constellation diagram of 8-PSK is shown in Fig
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Fig 17: Constellation diagram for 8-PSK[9] 16-PSK (16 Phase Shift Keying): The Modulated signal has sixteen different phases. We can transmit four bits at a time in this type of modulation. Constellation diagram of 16-PSK is shown in Fig
Fig :Constellation diagram for 16-PSK [9]
4.4.2c Different modulation technique stating data rates and coding rates :
Data Rates (Mbps) 6 9 12 18 24 36 48
Modulation Technique BPSK BPSK QPSK QPSK 16 QAM 16 QAM 64 QAM
Coding Rate 2/3
Coded bits/Sub carrier 1 1 2 2 4 4 6
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59
64 QAM
Table : Different modulation technique stating data rates and coding rates are listed in Table 4.4.3c Implementation Of QPSK: The implementation of QPSK is more general than that of BPSK and also indicates the implementation of higher-order PSK. Writing the symbols in the constellation diagram in terms of the sine and cosine waves used to transmit them:
This yields the four phases /4, 3/4, 5/4 and 7/4 as needed. This results in a two-dimensional signal space with unit basis functions.
The first basis function is used as the in-phase component of the signal . The second as the quadrature component of the signal. Hence, the signal constellation consists of the signal-space 4 points
The factors of 1/2 indicate that the total power is split equally between the two carriers. Comparing these basis functions with that for BPSK shows clearly how QPSK can be viewed as two independent BPSK signals. Note that the signal-space points for BPSK do not need to split the symbol (bit) energy over the two carriers in the scheme shown in the BPSK constellation diagram. QPSK systems can be implemented in a number of ways. An illustration of the major components of the transmitter and receiver structure are shown below.
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Fig Conceptual Transmitter Structure for QPSK
4.4.4c Conceptual transmitter structure for QPSK: The binary data stream is split into the in-phase and quadrature-phase components. These are then separately modulated onto two orthogonal basis functions. In this implementation, two sinusoids are used. Afterwards, the two signals are superimposed, and the resulting signal is the QPSK signal. The encoders can be placed before for binary data source, but have been placed after to illustrate the conceptual difference between digital and analog signals involved with digital modulation.
4.4.5c Bit error rate: Although QPSK can be viewed as a quaternary modulation, it is easier to see it as two independently modulated quadrature carriers. With this interpretation, the even (or odd) bits are used to modulate the in-phase component of the carrier, while the odd (or even) bits are used to modulate the quadrature-phase component of the carrier. BPSK is used on both carriers and they can be independently demodulated. As a result, the probability of bit-error for QPSK is the same as for BPSK:
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However, in order to achieve the same bit-error probability as BPSK, QPSK uses twice the power (since two bits are transmitted simultaneously).
The symbol error rate is given by:
. If the signal-to-noise ratio is high (as is necessary for practical QPSK systems) the probability of symbol error may be approximated:
4.4.4c QPSK signal in the time domain: The modulated signal is shown below for a short segment of a random binary datastream. The two carrier waves are a cosine wave and a sine wave, as indicated by the signal-space analysis above. Here, the odd-numbered bits have been assigned to the inphase component and the even-numbered bits to the quadrature component (taking the first bit as number 1). The total signal the sum of the two components is shown at the bottom.
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Fig Time Domain Representation of QPSK
Timing diagram for QPSK is shown . The binary data stream is shown beneath the time axis. The two signal components with their bit assignments are shown the top and the total, combined signal at the bottom. Note the abrupt changes in phase at some of the bitperiod boundaries. The binary data that is conveyed by this waveform is: 1 1 0 0 0 1 1 0.
The odd bits, highlighted here, contribute to the in-phase component: 11000110
The even bits, highlighted here, contribute to the quadrature-phase component: 11000110
4.5 FFT and IFFT:

All the different OFDM basic system blocks are introduced in this project. However, special attention is paid to the processing block of the OFDM system, composed by the Fast Fourier Transform (FFT) block and the Inverse Fast Fourier Transform (IFFT). These blocks are introduced theoretically, to know what is behind them, and also is shown the implementation and configuration of each block. The idea behind the implementation of OFDM can be extended to the digital domain by using the discrete Fourier Transform (DFT) and its counterpart, the inverse discrete Fourier Transform (IDFT). These mathematical operations are widely used for transforming data between the time-domain and frequency-domain. These transforms are interesting from the OFDM perspective because they can be viewed as mapping data onto orthogonal subcarriers. For example, the IDFT is used to take in frequency-domain data and convert it to timedomain data. In order to perform that operation, the IDFT correlates the frequencydomain input data with its orthogonal basis functions, which are sinusoids at certain frequencies. This correlation is equivalent to mapping .
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Fig: OFDM MODULATOR In practice, OFDM systems are implemented using a combination of fast Fourier Transform (FFT) and inverse fast Fourier Transform (IFFT) blocks that are mathematically equivalent versions of the DFT and IDFT, respectively, but more efficient to implement. An OFDM system treats the source symbols (e.g., the QPSK or QAM symbols that would be present in a single carrier system) at the transmitter as though they are in the frequency-domain. These symbols are used as the inputs to an IFFT block that brings the signal into the time-domain. The IFFT takes in N symbols at a time where N is the number of subcarriers in the system. Each of these N input symbols has a symbol period of T seconds. Recall that the basis functions for an IFFT are N orthogonal sinusoids. These sinusoids each have a different frequency and the lowest frequency is DC. Each input symbol acts like a complex weight for the corresponding sinusoidal basis function. Since the input symbols are complex, the value of the symbol determines both the amplitude and phase of the sinusoid for that subcarrier. The the input data onto the sinusoidal basis functions. The IFFT output is the summation of all N sinusoids. Thus, the IFFT block provides a simple way to modulate data onto N orthogonal subcarriers. The block of N output samples from the IFFT make up a single OFDM symbol. The length of the OFDM symbol is NT where T is the IFFT input symbol period mentioned above. After some additional processing, the time-domain signal that results from the IFFT is transmitted across the channel. At the receiver, an FFT block is used to process the received signal and bring it into the frequency-domain. Ideally, the FFT output will be the original symbols that were sent to the IFFT at the transmitter. When plotted in the complex plane, the FFT output samples will form a constellation, such as 16-QAM. However, there is no notion of a constellation for the time-domain signal. When plotted
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on the complex plane, the time-domain signal forms a scatter plot with no regular shape. Thus, any receiver processing that uses the concept of a constellation (such as symbol slicing) must occur in the frequency-domain.
CHAPTER 5 IMPLEMENTATION OF AN OFDM
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5.1 Implementation Flow chart:

Fig.5.1 Transmitter Flow Chart.
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Fig 5.2 Receiver Flowchart:
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5.2 IMPLEMENTATION OF AN OFDM TRANSMITTER AND RECEIVER BASED ON 8-POINTS INVERSE FAST FOURIER TRANSFORM (IFFT):
Before going further to discus on the FFT and IFFT design, it is good to explain a bit on the Fast Fourier Transform and Inverse Fast Fourier Transform operation. The Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) are derived from the main function which is called Discrete Fourier Transform (DFT). The idea of using FFT/IFFT instead of DFT is that the computation of the function can be made faster where this is the main criteria for implementation in the digital signal processing. In DFT the computation for N-point of the DFT will calculate one by one for each point. While for FFT/IFFT, the computation is done simultaneously and this method saves quite a lot of time.
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The FFT/IFFT operates on finite sequences. Waveforms which are analog in nature must be sampled at discrete points before the FFT/IFFT algorithm can be applied. The Discrete Fourier Transform (DFT) operates on sample time domain signal which is periodic. The equation for DFT is:
X(k) represent the DFT frequency output at the k-the spectral point where k ranges from 0 to N-1. The quantity N represents the number of sample points in the DFT data frame. The quantity x(n) represents the n-th time sample, where n also ranges from 0 to N-1. In general equation, x(n) can be real or complex. The corresponding inverse discrete Fourier transform (IDFT) of the sequence X(k) gives a sequence x(n) defined only on the interval from 0 to N-1 as follows:
The equation is a summation from 0 to N-1 for each output value x(n), X(k).e j.2.k.pi.n / N is summed from k=0 to k=N-1. For example, for x(2) the sum would be: x(2) = X(0) e j.0.2.pi.2 / N + X(1) e j.1.2.pi.2 / N + X(2) e j.2.2.pi.2 / N + X(3) e j.3.2.pi.2 / N + X(4) e j.4.2.pi.2 /
N
+ .......... (1)
Examination of the first equation reveals that the computation of each point of DFT requires the following computation. (N-1) complex multiplication, (N-1) complex addition (first term in sum involves ej0=1). Thus, to compute N points in DFT require N(N-1) complex multiplication and N(N-1) complex addition. As the N increases, the number of multiplications and additions required is significant because the multiplication function requires a relatively large amount of processing time even using computer. Thus, many methods for reducing the number of multiplications have been investigated over the last 50 years [12]. The next section discussed in detail one of the method made popular by Cooley and Turkey. The twiddle factor is the sine and cosine basis functions. By taking the advantage of the symmetry and periodicity of the twiddle factors as shown:
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The quantity WN is defined as:
Here is where the secret lies between DFT and FFT/IFFT where the function above is called Twiddle Factor. This factor is calculated and put in a table in order to make the computation easier and can run simultaneously. The Twiddle Factor table is depending on the number of point use. During the computation of IFFT, the factor does not to recalculate since it can refer to the Twiddle factor table thus it save time since calculation is done concurrently. The table 5.1 for 8 point of FFT for twiddle factor.
Table 5.1 Twiddle Factor Value for FFT Another important radix-2 FFT algorithm, called the decimation-in-frequency algorithm, is obtained by using the divide-and-conquer approach. To derive the algorithm, we begin by splitting the DFT formula into two summations, one of which involves the sum over the first N/2 data points and the second sum involves the last N/2 data points. Thus we obtain
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Now, let us split (decimate) X(k) into the even- and odd-numbered samples. Thus we obtain
where we have used the fact that WN2 = WN/2 The computational procedure above can be repeated through decimation of the N/2-point DFTs X(2k) and X(2k+1). The entire process involves v = log2N stages of decimation, where each stage involves N/2 butterflies of the type shown in Figure Consequently, the computation of the N-point DFT via the decimation-in-frequency FFT requires (N/2)log2N complex multiplications and Nlog2N complex additions, just as in the decimation-in-time algorithm. For illustrative purposes, the eight-point decimation-infrequency algorithm is given in Figure
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Fig 5.3 First stage of the decimation-in-frequency FFT algorithm
Fig 5.4 Basic butterfly computation in the decimation-in-frequency. The equation above shows that for FFT decimation in frequency radix 2, the input can be grouped into odd and even number. Thus, graphically the operation can be view using FFT flow graph shown in figure 5.4.
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5.3 Signal Flow Graph:
Fig 5.4 8-point FFT flow graph using decimation-in-frequency (DIF) From this figure, the FFT computation is accomplished in three stages. The X(0) until X(7) variable is denoted as the input value for FFT computation and Y(0) until Y(7) is denoted as the output. There are two operations to complete the computation in each stage. The upward arrow will execute addition operation while downward arrow will execute subtraction operation. The subtracted value is multiplied with twiddle factor value before being processed into the nest stage. This operation is done concurrently and is known as butterfly process. For second stage, there are two butterfly process with each process get reduced input variable. In the first stage the butterfly process get eight input variable while in the second stage, each butterfly process get four input variable that is from first stage computation. This process is continued until third stage. In third stage, there are four butterfly processes. Noted that each of the butterfly process is performed concurrently enable it to execute FFT computation process in a very fast technique. Mathematically, the butterfly process for each stage can be derived as the equation stated below. FFT Stage 1
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X(0) + X(4) => X(0), X(1) + X(5) => X(1), X(2) + X(6) => X(2), X(3) + X(7) => X(3), [X(0) X(4)]W0 => X(4), [X(1) X(5)]W1 => X(5), [X(2) X(6)]W2 => X(6), [X(3) X(7)]W3 => X(7), FFT Stage 2 X(0) + X(2) => X(0), X(1) + X(3) => X(1), [X(0) X(2)]W0 => X(2), [X(1) X(3)]W0 => X(3), X(4) + X(2) => X(4), X(5) + X(3) => X(5), [X(4) X(6)]W0 => X(6), [X(5) X(7)]W0 => X(7), FFT Stage 3 X(0) + X(1) => Y(0), X(1) X(5) => Y(1), X(2) + X(3) => Y(2), X(2) X(3) => Y(3), X(4) + X(5) => Y(4), X(4) X(5) => Y(5), X(6) + X(7) => Y(6), X(6) X(7) => Y(7),
5.4 FFT Scheduling Diagram :
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In the stage three, final computation is done and the result is sent to the variable Y(0) to Y(7). Equation in each stage is used to construct scheduling diagram. Scheduling diagram is part of Behavioral Modeling and Synthesis steps to translate the algorithmic description into RTL (register transfer level) in VHDL design. The scheduling diagram for stage one computation is constructed as figure 5.6.
Fig 5.6 Scheduling diagram for stage one of 8 point FFT. Base on variable XR0, XR4, and the rest is denoted as the register in FPGA. The register is name as such to ensure that each register has its own unique name. During computation, these register will hold computation value, thus it is required to be unique for easy recalling the value when needed. S0 until S3 is denoted as clock cycle. Computation in stage one requires four clock cycle to complete before moves to the next stage. In this stage, the operation takes longer clock cycles because of the multiplication of twiddle factor value. Since twiddle factor value is complex, computation need to separate real value and imaginary value. XR denoted as real value while XI is for imaginary.
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Fig 5.7Scheduling diagrams for stage two of 8 point FFT. Figure 5.7 show the scheduling diagram for stage two. The value from stage one computation is sent to this stage as input. The number of register to store computed values from stage one is same because it is already allocated to receive real and imaginary values. The situation is different for IFFT operation. This will be discussed later on IFFT topic. FFT commonly is used at the receiver to convert time domain signal into frequency domain. XR01 until XI71 denoted as the register name in stage two.
Fig 5.8 Scheduling diagrams for stage three of 8 point FFT. Figure 5.8 show the last stage of FFT computation. The register XR03 until XI73 holds output values for FFT. These register will be call upon when displaying the result during software programming.
5.5 IFFT Scheduling Diagram :
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As mention in previous chapter, Inverse Fast Fourier Transform (IFFT) is said to generate OFDM symbols. The data bits is represent as the frequency domain and since IFFT convert signal from frequency domain to time domain, it is used in transmitter to handle the process. IFFT is defined as the equation below:
Comparing this equation with the equation (1), it is shown that the same FFT algorithm can be used to find IFFT function with the changes in certain properties. The changes that implement is by adding a scaling factor of 1/N and replacing twiddle factor value (Wnk) with the complex conjugate W-nk to the equation (1). With these changes, the same FFT flow graph also can be used for the Inverse fast Fourier Transform. Below is the table show the value of twiddle factor for IFFT.
Table 5.2 Twiddle Factor value for 8 Point IFFT
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Base on the equation obtain from the signal flow graph, scheduling diagram is developed. Eight registers is required to store input value from user. These registers only accept real value as the input for IFFT operation. Below is the scheduling diagram for IFFT stage 1.
Fig 5.9 Scheduling diagrams for stage one of 8 point IFFT. For stage one, computation is accomplished in three clock cycle denoted as S0 to S2. The operation is much simpler compared with the FFT. This is because FFT processed both real and imaginary value while IFFT only real. The result from IFFT is represented in real and imaginary value because of the multiplication of twiddle factor. Twiddle factor is a constant defined by the number of point used in this transform. This scheduling diagram is derived from the equation obtain in FFTsignal flow graph.
Fig 5.10 Scheduling diagrams for stage two of 8 point IFFT.
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Fig 5.11 Scheduling diagrams for stage three of 8 point IFFT. Figures 5.10 and 5.11 shows the scheduling diagram for stage two and three
respectively. The same notation with FFT scheduling diagram is used for IFFT process. For example, referring to figure 5.11, in clock S3, the addition and subtraction operation is performed. As mention before, each clock cycle, the addition and subtraction is executed concurrently and the result is stored in the next register. In clock S4, only three operations is performed, that is multiplication of twiddle factor value. In figure figure 5.11, the resultant value is multiplied with the number 0.125. This number actually same as the division with the N point value. In this case N value is 8 for 8 point IFFT. The final result is stored in the memory and will be called upon when it is required to display the result at user interface. Signal flow graph is very important as the guided to understand the computation process especially during software programming whereby to create test vector programHardware Module
5.6 Hardware Module:

Hardware module is developed using VHDL language. The modules which developed include FFT/IFFT, serial to parallel and parallel to serial and mapping block. Each of this module function is described in following section. 5.5.1 Fast Fourier Transform (FFT):
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Fig. 5.12 FFT Module Figure 5.12 show the block diagram for FFT module. This basic module consists of only two inputs which is DataA and DataB. Opcode is used to select the operation performed by the module. Result will be delivered through Result port .Several operations are performed by this hardware where each operation executed in one clock cycle. Each operation is assigned to the unique opcode value. Referring to the source code in appendix, FFT module has eight operations involved such as addition, subtraction, multiplication, pass module and conversion from positive number to negative. 5.6.2 Inverse Fast Fourier Transform (FFT) : The same block diagram as FFT is used to develop IFFT module. Input port such as DataA, DataB and Opcode is also used as well as Result for output port. The different between FFT and IFFT is that the IFFT module needs to divide with eight at the end of the result. Additional operation to handle this process is inserted at this module. 5.6.3 Hardware Interfacing : Both FFT and IFFT need to connect to Avalon bus for data processing performed by the standard 32 type CPU module. CPU module which is call NIOS CPU is provided to manage the data processing performed by the FFT or IFFT module.
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Fig 5.13. Block diagram of the connection between IFFT or FFT module with bus system.
Figure 5.13 shows the connection between FFT or IFFT module with the Avalon bus system. Interface module is responsible to manage the communication between buses with the FFT or IFFT module. Data is inputted through write at a port and buffered in the interface module before it is sent to the FFT or IFFT. The result of computation is delivered to the wire data port and display to user through appropriate interface. For example, such a simple FFT in this case, the address indicates which data to be passed between the FFT module unit and the Avalon Bus System. In this FFT case, the FFT need 4 cycles to complete an operation. First clock cycle is used to fetch opcode (OPCODE) from Avalon bus to FFT, second clock cycle to fetch first operand (DATAa) from Avalon bus to FFT, third cycle to fetch second (DATAb) operand from Avalon bus to FFT, and the last clock cycle to fetch the operation result (RESULT) from the FFT to the Avalon Bus System.
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Fig 5.14 Transmitter module and receiver module Figure 5.14 shows the illustration for the transmitter and receiver module. The output from transmitter module which is mainly consists of IFFT is used as the input to the receiver module. Generally if the input from transmitter is real value the computation of IFFT will result real and imaginary value. While if the input is imaginary, computation will result in real value. For the IFFT design, the input only accept real value, thus imaginary result is obtained. The receiver needs to have both real and imaginary at the input to convert back to the original value. So, FFT is design to have this feature in order to process the data and display the correct result.
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CHAPTER 6: SIMULATION RESULTS
During this chapter the results obtained by testing the complete implemented OFDM system will be shown. For the simulation phase the testing is done on the PC using the System Generator tools. The implementation schemes used for the testing have already
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been introduced in the previous chapter so this section will be focused in the obtained results.
6.1 Review of Project Flow:

This project consists of research, implementation and simulation of an OFDM communication system. Figure 6.1 shows a simplified Project Flow Diagram:
Fig: 6.1 Project Flow Diagram Figure 6.2 shows a simplified flowchart of the MATLAB simulation code.
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Fig 6.2 OFDM Simulation Flowchart The transmitter first converts the input data from a serial stream to parallel sets. Each set of data contains one symbol, Si, for each subcarrier. For example, a set of four data would be [S0 S1 S2 S3]. Before performing the Inverse Fast Fourier Transform (IFFT), this example data set is arranged on the horizontal axis in the frequency domain as shown in Figure 5.3.
Fig 6.3 Frequency Domain Distribution of Symbols This symmetrical arrangement about the vertical axis is necessary for using the IFFT to manipulate this data. An inverse Fourier transform converts the frequency domain data set into samples of the corresponding time domain representation of this data. Specifically, the IFFT is useful for OFDM because it generates samples of a waveform with frequency components satisfying orthogonality conditions.
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Then, the parallel to serial block creates the OFDM signal by sequentially outputting the time domain samples. The channel simulation allows examination of common wireless channel characteristics such as noise, multipath, and clipping [5]. By adding random data to the transmitted signal, simple noise is simulated. Multipath simulation involves adding attenuated and delayed copies of the transmitted signal to the original. This simulates the problem in wireless communication when the signal propagates on many paths. For example, a receiver may see a signal via a direct path as well as a path that bounces off a building. Finally, clipping simulates the problem of amplifier saturation. This addresses a practical implementation problem in OFDM where the peak to average power ratio is high. The receiver performs the inverse of the transmitter. First, the OFDM data are split from a serial stream into parallel sets. The Fast Fourier Transform (FFT) converts the time domain samples back into a frequency domain representation. The magnitudes of the frequency components correspond to the original data. Finally, the parallel to serial block converts this parallel data into a serial stream to recover the original input data.
6.2Tool Structure and Flow OF MODELSIM:

The diagram 6.3 illustrates the structure of the ModelSim tool, and the flow of that tool as it is used to verify a design.
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Fig 6.4 Tool flow in modelsim
6.3 Simulation task details:
Table 6.1 Simulation Details
6.4 Flow Chart :
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Fig 6.5 Flowchart
6.5 Simulation Results:

Procedure for simulation.
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The clock is given first. Then reset is made low and the values are initialized. When mem_ready = 1 & Write Enable = 1, then start loading data into memory by incrementing address starting from 6b0.
Write Enable =1 Address = 6b010101
In- phase data
Q-phase data
6.5.1 Serial to Parallel Module:
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Fig 6.6 Block Diagram of Serial to parallel Module The data comes serially from the input port SERIN. The parallel data is output from DOUT port. Output port DRDY is asserted 1 when the start bit, 8 bit data and the parity bit is received. Output port PERRn is asserted 0 when the parity bit received is different from the parity generated inside the serial to parallel circuit. When parity error is detected, the serial to parallel circuit would be reset before its normal operation can be performed. This is the operation for serial to parallel module. The figure 6.6.1 shows a simulation waveform for an input data 11001001. The input data is in serial format and the conversion is started with the start bit is being asserted 1 in the SERIN input. The SERIN input receives serial data 1,1,0,0,1,0,0,1 followed by the even parity bit of value 0. After the parity bit is received, the output signal DRDY is asserted 1 in the next clock cycle. The DRDY signal is used to tell another circuit block to get the parallel data from DOUT right away. Otherwise the data may be lost when the next word comes. The DRDY and the start bit are allows to be asserted simultaneously and DOUTs value is changed right after DRDY is disserted. The old data is shifted out bit by bit. Output PERRn is not asserted since the parity error is not detected.
6.6.1 Simulation waveform of Serial to Parallel Module:
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Fig 6.7 Simulation Waveform of serial to Parallel
6.6.2 Parallel To Serial Module:
Fig 6.8 Block Diagram ofParallel to Serial Module A parallel to serial converter is a special function of shift register. The data is parallel loaded to the shift register and then shift out bit by bit also is bounded by a start bit and stop bit. In OFDM transmitter module, a parallel to serial converter is used to convert computation result which is in parallel to serial before being sent to other module for
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processing. This parallel to serial module is design such that the data to be transmit is first parallel loaded then transmitted bit by bit by a start bit of value 1. This is followed by the 8-bit data with the left bit most bit first. The converter holds the output low when the transmission is completed.Figure 6.9 Shows the data conversion from parallel to serial. When input signal PL is asserted 1, the data DIN 11000111 is parallel loaded into the parallel to serial circuit. In the next clock cycle, a start bit of 1 is outputted, followed by the data 11000111, then completed with an even parity bit of value 1. After that, the output stays at low until the PL input is asserted again. The second data is 11001111 and start bit value is 1. But during data conversion RSTn signal is asserted to 0 result that the output of SEROUT is 0. The third data is 11010111. The start bit is same followed by data and parity bit value is 1.
Fig 6.9 Simulation waveform Of Parallel to serial
6.6.3 Simulation Waveform of QPSK Modulator:

The encoder of the constellation maps the M bits of the channel in a point a + jb in the constellation of the modulator.
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A constellation mapper takes a serial bit stream as its input and segments the stream into N-bit symbols, which are mapped to coordinates in the signal constellation. The coordinates of each point in a two-dimensional signal constellation represents the baseband in-phase and quadrature (I-Q) components that modulate the orthogonal IF carrier signals.
Fig 6.10 Simulation waveform of QPSK Modulator
6.6.4.Simulation waveform of QPSK Demodulator:

Once the demapper detects the transmitted I-Q coordinates, it can output the difference between the actual constellation point and the received coordinates as an error. This information indicates the level of confidence in the decision made by the demapper, and it can also be used by other parts of the demodulator to obtain a confidence estimate. Demodulator subsystems can use this output information to compensate for channel impairments such as phase noise, carrier noise, channel dispersion.
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Fig.6.11 simulation waveform of QPSK Demodulator
6.6.5 RADIX-4 FFT WAVEFORM: Inputs: Regai: In-phase Input A Regaq: Q-phase Input A Regbi: In-phase Input B Regbq: Q-phase Input B
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Outputs: Iout: In-phase Output Qout: Q-phase Output
Fig 6.12 IFFT Simulation Waveform
6.6.6 Transmitter Simulation Waveform:
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Inputs:
Clk : Input clock Serial: Serial Input Data Reset: Active Low Reset Serial input data is loaded at every posedege of clock if reset is high. When Reset is low no data is loaded.Output data is valid only if output_enable is High.The IFFT math is now complete.It has generated an OFDM signalthat corresponds to binary data.The plot shows the signal generated by the IFFT.
Fig 6.13 Simulation Waveform of transmitter side
6.6.7 Top Module Output(Receiver Side):
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Inputs: Clk : Input clock Serial: Serial Input Data Reset: Active Low Reset Outputs: Output Enable: Data is valid when it is High Out : Output Data Serial input data is loaded at every posedege of clock if reset is high. When Reset is low no data is loaded. Output data is valid only if output_enable is High .Finally, an FFT is used to recover the dada as shown in the plot.
Fig-6.14 Simulation Waveform Of Receiver Side
6.6.8 Memory Simulation waveform:
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Inputs: Clkin Wen = Input clock = Write Enable
Addrin = Input Address Dnr Dni Outputs: Clkout = Output clock Addrout = Output Address Doutr Douti = Data Output Real = Data Output Imaginary = Data In Real = Data In Imaginary
Data Input is loaded into memory when Write enable (WEN) is high. Data output is unloaded from memory wrt clkout.
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Fig 6.14 Memory Simulation Waveform
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CHAPTER 6: RTL SCHEMATIC AND DESIGN SUMMARY
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DESIGN SUMMARY
Selected Device : 5vfx200tff1738-2
Slice Logic Utilization:
Number of Slice Registers: Number of Slice LUTs: Number used as Logic:
74 out of 122880
0%
2185 out of 122880 1% 2185 out of 122880 1%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: Number with an unused Flip Flop: Number with an unused LUT: Number of fully used LUT-FF pairs: Number of unique control sets:
2213 96% 1% 2%
2139 out of 2213 28 out of 2213 46 out of 2213 2
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IO Utilization:
Number of IOs: Number of bonded IOBs:
259 259 out of 960 26%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: Number of DSP48Es:
1 out of 32 out of
32
3% 8%
384
Timing Summary:
Speed Grade: -2 Minimum period: 1.727ns (Maximum Frequency: 579.155MHz) Minimum input arrival time before clock: 2.287ns Maximum output required time after clock: 25.292ns Maximum combinational path delay: No path found
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CHAPTER 8: CONCLUSION & FUTURE WORK
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8.1.CONCLUSION :
As mentioned in the objectives, OFDM transmitter was successfully developed using Xilinx-Vertex2Pro FPGA development board.
The output from each module was tested using appropriate software to ensure the correctness of the output result.
On the transmitter part there are four blocks which consists of mapper (modulation), serial to parallel, IFFT and parallel to serial block.Modules and Submodules of the OFDM transmitter were designed and modeled in VHDL and simulated using MODELSIM. Each of these blocks was tested during design process. This is to ensure that the hardware module was correctly working when implemented in the FPGA hardware. During the implementation stage, the operation for IFFT was tested . Since IFFT is base on mathematical operation, Matlab is the best platform to compare the computation result. The comparison result shows that IFFT module is working correctly as the Matlab computation. Some computation gives slightly different from Matlab especially in imaginary value. Thus, base on the test result, it was concluded that IFFT module was viably used in transmitter part as processing module. The same process was done at the receiver part whereby each of the modules was tested during design process. From the result shown in the results chapter, FFT module was correctly operated . The different was only that the result of the FFT computation was in decimal while Matlab provide in floating point value. Matlab result was rounded such that it can be equally compared with the FFT computation using FPGA. FFT can accept real and imaginary at the input because the data received from transmitter is in real and imaginary format.
Other modules such as serial to parallel, parallel to serial and mapping module was correctly worked. Thus, this module can be used as part of the OFDM system. The waveform result for these modules was given in Chapter 7 and the discussion
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regarding the operation of these modules was also made in that chapter 2 and 3 . The design can be further made to an improvement base on the suggestion discussed in this chapter 3 .
8.2 Proposed Future Works :

Some recommendations are suggested to overcome the problem encountered during development of this project. First is to use higher bit representation to represent the number. Instead of using 8 bit binary representation, use 16 bit or more to represent each number in binary. The reason of using this method is to make the number representation can represent in more wide range of number. Thus the risk of overflow problem will decrease. Beside that, selective code words also can be used at the input such as input is limited from 0 to 64 for positive value of 8 bit binary twos complement. Use higher fixes point representation for point value representation. Floating point format also can be considered as the solution to reduce error number representation especially for twiddle factor value which is 0.7071. Although floating point consume processing time and output latency, but it is an excellence method to overcome accuracy problem. Beside that, it is suggested to create a circuit to detect the overflow by indicating the flag or whatever way to ensure that the user know that the input given creates error to the system. The user will notice this problem and will change the input value to ensure no error occurred. In this design, the receiver module which is mainly using FFT is good at processing for the positive input value. Therefore, any imaginary value should be mapped into real value such that receiver can process the input data correctly. For the future works, it is suggested to develop other modules such as interleaving, error correction, 16 or 64 QAM modulation, cyclic prefix module and
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RF part. These modules will make a complete set of OFDM system for transmitter and receiver.
BIBLIOGRAPHY
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[1] M. Helaoui, S. Boumaiza, A. Ghazel, and F. M. Ghannouchi, On the RF/DSP design for efficiency of OFDM transmitters, IEEE Trans. Microw. Theory and Tech., vol. 53, no. 7, pp. 2355-2361, Jul. 2005. [2] P. Gilabert, G. Montoro and E. Bertran, Multiple lookup table predistortion for adaptive modulation, Proceedings of the European Microwave Association. 2005. [3] J. G. Proakis, D.G. Manolakis, Tratamiento de Seales: Principios, Algoritmos y Aplicaciones, 3 Edicin. Prentice-Hall, 1997. [4] The Cyclic Prefix of OFDM/DMT An Analysis Werner Henkel, Georg Taubock Telecommunications Research Center (ftw.) A-1220 [5] H. J. Kim, S. C. Cho, H. S. Oh and J. M. Ahn, Adaptive clipping technique for reducing PAPR on OFDM systems, in Proc. IEEE 58th Veh. Tech. Conf., VTC-2003, Orlando, Florida USA, Oct. 2003, vol. 3, pp. 1478 1481. [6] G. Zelniker, F.J. Taylor, Advanced Digital Signal Processing: Theory and Applications.Marcel Dekker Inc., 1994. [7] http://www.scribd.com/doc/15074150/DESIGN-AND-IMPLEMENTATIONOF-OFDM-TRANSMITTER-AND-RECEIVER-ON-FPGA-HARDWARE[8] Pere Lluis Gilabert AUTHOR: Francisco Martn Gutirrez TITLE: implementation of a Tx/Rx OFDM System in a FPGA. DATE: April, 30th 2009 . [9] Tsui J., Digital Techniques for Wideband Receivers, Artech Houser Inc 1995, ISBN 0-89006-808-9 [10] MathWorks Inc., La Edicin de Estudiante de Simulink. PrenticeHall,1997. [11] S. K. Mitra, Digital Signal Processing Laboratory Using Matlab, McGraw-Hill, 1999. [12] Xilinx Web site, Available Online: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryI D=1&getPagePath=10910 [13] Xilinx System Generator product datasheet , Available Online: http://www.xilinx.com/ipcenter/dsp/sysgen_prod_brief.pdf [14] STOTT, J.H., 1996. The DVB terrestrial (DVB-T) specification and its implementation in a practical modem. Proceedings of the 1996 International
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Broadcasting Convention, IEE Conference Publication No. 428, pp. 255-260, September
[15]"Coleri, S. Ergen, M. Puri, A. Bahai, A., Channel estimation techniques based on pilot arrangement in OFDM systems. IEEE Transactions on Broadcasting, Sep 2002." [16] Hoeher, P. Kaiser, S. Robertson, P. "Two-dimensional pilot-symbol-aided channel estimation by Wiener filtering". IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP-97, 1997. [17]Chang, R. W. (1966). Synthesis of band-limited orthogonal signals for multi-channel data transmission, Bell System Technical Journal 46, 1775-1796. [18]Stott, 1997 Technical presentation by J H Stott of the BBC's R&D division, delivered at the 20 International Television Symposium in 1997.
[19 ]L.D. Kabulepa, OFDM Basics for Wireless Communications, Institute of Microelectronic Systems, Darmstadt University of Technology. [20]Andreas F. Molisch (Editor), Wideband Wireless Digital Communications, Chapter 18; Pearson Education, 2001.
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APPENDIX
XILINX FLOW:
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This part explains the flow of XILINX to simulator from creating a project to simulating the results of the project. To create a new project which will target the FPGA device on the Spartan-3 Startup Kit demo board. To create a new project: 1. Select File > New Project... The New Project Wizard appears. 2. Type OFDM in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A Project Subdirectory is created automatically. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. 6. Fill in the properties in the table as shown below: Product Category: All Family: Spartan3 Device: XC3S200 Package: FT256 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: ( VHDL) or (VERILOG) Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields. When the table is complete, your project properties will look like the following : 7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete.
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Figure1 : Project Device Properties
Create an HDL Source:

In this section, we will create the top-level HDL file for your design. Determine the language . Then, continue either to the Creating a VHDL Source section below, or skip to the Creating a Verilog Source section.
Creatinga VHDLSource:
Create a VHDL source file for the project as follows: 1. Click the New Source button in the New Project Wizard. 2. Select VHDL Module as the source type. 3. Type in the file name counter.
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4. Verify that the Add to project checkbox is selected. 5. Click Next. 6. Declare the ports for the counter design by filling in the port information as shown below: 7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source file template. 8. Click Next, then Next, then Finish. The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown below: Figure2 : Define Module
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Figure 3: New Project in ISE
UsingLanguageTemplates(VHDL):
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The next step in creating the new source is to add the behavioral description for the counter. To do this use a simple counter code example from the ISE Language Templates and customize it for the counter design. 1. Place the cursor just below the begin statement within the counter architecture. 2. Open the Language Templates by selecting Edit Language Templates Note: You can tile the Language Templates and the counter file by selecting Window Tile Vertically to make them both visible. 3. Using the + symbol, browse to the following code example: VHDL Synthesis Constructs Coding Examples Counters Binary Up/Down Counters Simple Counter 4. With Simple Counter selected, select Edit Use in File, or select the Use Template in File toolbar button. This step copies the template into the counter source file. 5. Close the Language Templates.
Final Editingof the VHDLSource:

1. Add the following signal declaration to handle the feedback of the counter output below the architecture declaration and above the first begin statement: signal count_int : std_logic_vector(3 downto 0) := "0000"; 2. Customize the source file for the counter design by replacing the port and signal name placeholders with the actual ones as follows: replace all occurrences of <clock> with CLOCK replace all occurrences of <count_direction> with DIRECTION replace all occurrences of <count> with count_int
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3. Add the following line below the end process; statement: COUNT_OUT <= count_int;
4. Save the file by selecting File Save. After finishing this, the counter source file will look like the following: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitive in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end counter; architecture Behavioral of counter is signal count_int : std_logic_vector(3 downto 0) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int <= count_int + 1; else count_int <= count_int - 1; end if; end if; end process; COUNT_OUT <= count_int; end Behavioral;
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Checkingthe Syntaxof the NewCounterModule:

When the source files are complete, check the syntax of the design to find errors and types. 1. Verify that Implementation is selected from the drop-down list in the Sources window. 2. Select the counter design source in the Sources window to display the related processes in the Processes window. 3. Click the + next to the Synthesize-XST process to expand the process group. 4. Double-click the Check Syntax process. Note: Error must be corrected in the source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design. 5. Close the HDL file.
Design Simulation:
VerifyingFunctionalityusingBehavioralSimulation:
Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test
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bench. Create the test bench waveform as follows: 1. Select the counter HDL file in the Sources window. 2. Create a new test bench source by selecting Project New Source. 3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type counter_tbw in the File Name field. 4. Click Next. 5. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next. 6. The Summary page shows that the source will be added to the project, and it displays the source directory, type, and name. Click Finish. 7. we need to set the clock frequency, setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens. The requirements for this design are the following: The counter must operate correctly with an input clock frequency = 25 MHz. The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The design requirements corresponds with the values below. Fill in the fields in the Initialize Timing dialog box with the following information: Clock High Time: 20 ns.
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Clock Low Time: 20 ns. Input Setup Time: 10 ns. Output Valid Delay: 10 ns. Offset: 0 ns. Global Signals: GSR (FPGA) Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically. Initial Length of Test Bench: 1500 ns. 8. Click Finish to complete the timing initialization. 9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows: Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up. Click on the blue cell at approximately the 900 ns to assert DIRECTION low so
that the counter will count down.
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Figure 4: Initialize Timing
Figure 5: Test Bench Waveform 10. Save the waveform.
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11. In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project.
Figure 6: Behavior Simulation Selection
12.Close the test bench waveform.
SimulatingDesignFunctionality:
Verify that the counter design functions as you expect by performing behavior simulation as follows: 1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources window. 2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench. 3. To view simulation results, select the Simulation tab and zoom in on the transitions. The simulation waveform results will look like the following:
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Figure 7: Simulation Results 4. Verify that the counter is counting up and down as expected. 5. Close the simulation view. If prompted with the following message, You have an active simulation open. Are you sure you want to close it?, click Yes to continue. Now simulation is completed using the ISE Simulator.
Implementingthe Design:
1. Select the counter source file in the Sources window. 2. Open the Design Summary by double-clicking the View Design Summary process in the Processes tab. 3. Double-click the Implement Design process in the Processes tab. 4. Notice that after Implementation is complete, the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings.
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5. Locate the Performance Summary table near the bottom of the Design Summary. 6. Click the All Constraints Met link in the Timing Constraints field to view the Timing Constraints report. Verify that the design meets the specified timing requirements.
Download Design to the Spartan-3 Demo Board

This is the last step in the design verification process. This section provides simple instructions for downloading the counter design to the Spartan-3 Starter Kit demo board. 1. Connect the 5V DC power cable to the power input on the demo board (J4). 2. Connect the download cable between the PC and demo board (J7). 3. Select Implementation from the drop-down list in the Sources window 4. Select counter in the Sources window. 5. In the Process window, double-click the Configure Target Device process. 6. The Xilinx WebTalk Dialog box may open during this process. Click Decline. iMPACT opens and the Configure Devices dialog box is displayed. 7. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG). 8. Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected. 9. Click Finish.
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10. If you get a message saying that there are two devices found, click OK to continue. 11. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device in the JTAG chain, select the counter.bit file and click Open. The devices connected to the JTAG chain on the board will be detected and displayed in the iMPACT window. 12. If you get a Warning message, click OK. 13. Select Bypass to skip any remaining devices. 14. Right-click on the xc3s200 device image, and select Program... The Programming Properties dialog box opens. 15. Click OK to program the device. When programming is complete, the Program Succeeded message is displayed. On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running. 16. Close iMPACT without saving.
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Figure 8: iMPACT Welcome Dialog Box
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Figure9 : Assign New Configuration File
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Implementation of OFDM Transmitter and Receiver

Dept. of E & C J.S.S.A.T.E .B lore.

Implementation of OFDM Transmitter and Receiver

Dept. of E & C J.S.S.A.T.E .B lore.

Implementation of OFDM Transmitter and Receiver

Dept. of E & C J.S.S.A.T.E .B lore.

Implementation of OFDM Transmitter and Receiver

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1.4a Problem statement:

1.4b Problem definition:

1.4c Analysis of the problem statement:

1.4d Problems are solved by:

1.5 Methodology Adopted :

Dept. of E & C J.S.S.A.T.E .B lore.

Implementation of OFDM Transmitter and Receiver

1.6 Tools and languages used : 1.6a Tools used:

1.6b Language used:

1.7 Project Workflow:

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Implementation of OFDM Transmitter and Receiver

1.8 Design specifications:

600 MHz 75MHz 8 20-40MHz 10M

1.9 Organisation of the thesis:

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CHAPTER 2: LITERATURE SURVEY

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2.2 Multichannel Transmission:

2.3 Basic Principles of OFDM:

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Fig 2.1 FDMA[ 8]

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Implementation of OFDM Transmitter and Receiver

2.4 Orthogonality Defined:

Fig 2.3 The structure of OFDM modulator[5]

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Implementation of OFDM Transmitter and Receiver

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Implementation of OFDM Transmitter and Receiver

2.4 Orthogonality of sub-carrier[7]

2.5 OFDM Carriers:

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Implementation of OFDM Transmitter and Receiver

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Implementation of OFDM Transmitter and Receiver

Fig 2.6 Implementation of Cyclic Prefix[7]

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2.8 Generation of OFDM Signals:

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Implementation of OFDM Transmitter and Receiver

2.8. Binary Phase-Shift Key (BPSK) representation of 0101101[7]

Figure 2.9: A set of orthogonal signals[7]