Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

CMOS Mixed Signal Design

Part I: OpAmp Design

Dinesh Sharma
Microelectronics Group, EE Department IIT Bombay, Mumbai

March 21, 2006

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Linear Mode

Linear Mode of Operation

Inverter Transfer Curve V
OH

Analog circuits require the output voltage to be sensitive to the input voltage.

OL

iL

Digital logic requires the output to be insensitive to the exact input voltage.

iH

Circuits need to be biased for operation in the linear regime.

Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Linear Mode

Linear Mode of Operation

Inverter Transfer Curve V
OH

Analog circuits require the output voltage to be sensitive to the input voltage.

OL

iL

Digital logic requires the output to be insensitive to the exact input voltage.

iH

Circuits need to be biased for operation in the linear regime.

Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Linear Mode

Linear Mode of Operation

Inverter Transfer Curve V
OH

Analog circuits require the output voltage to be sensitive to the input voltage.

OL

iL

Digital logic requires the output to be insensitive to the exact input voltage.

iH

Circuits need to be biased for operation in the linear regime.

Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Linear Mode

Linear Mode of Operation

Inverter Transfer Curve V
OH

Analog circuits require the output voltage to be sensitive to the input voltage.

OL

iL

Digital logic requires the output to be insensitive to the exact input voltage.

iH

Circuits need to be biased for operation in the linear regime.

Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

A Single Transistor Amplier

I d v o v i Vg V d

dId =

Id I dVg + d dVd Vg Vd

Id = gm (Transconductance) Vg Id = go (O/P conductance) Vd

The current source load keeps the drain current constant. So dId = 0 = gm vi + go vo Hence, the voltage gain (Ao ) is vo gm Ao = = gm ro = vi go
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Transistor Characteristics
gm and go depend on the transistor characteristics. In saturation, Id K 2 (Vg VTo Vs )2

where, K is the conductivity factor given by: K =K W L Cox W L

VTo is the threshold voltage without substrate bias, and is a parameter which accounts for the effect of substrate bias V s . is weakly dependent on Vd and its value is close to 1. W and L are transistor width and length respectively. Vs is the substrate bias.
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Transconductance
Let VGT (Vg VTo Vs ) K 2 VGT Then Id = 2 K K W I VGT = So gm = d = Vg L But VGT = So gm = Also, K = 2KId = 2Id VGT
2

VGT

2Id K 2K W L Id 2Id VGT

Therefore gm =

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Which formula?
To increase gm should we increase VGT ? or decrease it? W 2K Is gm linearly dependent on Id gm = L transistor size? dependent on its square root? 2I gm = d or is it independent of transistor VGT size? In fact, which formula should be applied depends on how the transistor is biased and sized. If size and VGT are known, the rst formula applies. If the drain current and size are known, the second one does. If gate voltage and drain current are given and the transistor is accordingly sized, the third formula should be used. gm = VGT
Dinesh Sharma CMOS Mixed Signal Design

K W L

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Which formula?
To increase gm should we increase VGT ? or decrease it? W 2K Is gm linearly dependent on Id gm = L transistor size? dependent on its square root? 2I gm = d or is it independent of transistor VGT size? In fact, which formula should be applied depends on how the transistor is biased and sized. If size and VGT are known, the rst formula applies. If the drain current and size are known, the second one does. If gate voltage and drain current are given and the transistor is accordingly sized, the third formula should be used. gm = VGT
Dinesh Sharma CMOS Mixed Signal Design

K W L

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Which formula?
To increase gm should we increase VGT ? or decrease it? W 2K Is gm linearly dependent on gm = Id L transistor size? dependent on its square root? 2I gm = d or is it independent of transistor VGT size? In fact, which formula should be applied depends on how the transistor is biased and sized. If size and VGT are known, the rst formula applies. If the drain current and size are known, the second one does. If gate voltage and drain current are given and the transistor is accordingly sized, the third formula should be used. gm = VGT
Dinesh Sharma CMOS Mixed Signal Design

K W L

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Which formula?
To increase gm should we increase VGT ? or decrease it? W 2K Is gm linearly dependent on Id gm = L transistor size? dependent on its square root? 2I gm = d or is it independent of transistor VGT size? In fact, which formula should be applied depends on how the transistor is biased and sized. If size and VGT are known, the rst formula applies. If the drain current and size are known, the second one does. If gate voltage and drain current are given and the transistor is accordingly sized, the third formula should be used. gm = VGT
Dinesh Sharma CMOS Mixed Signal Design

K W L

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Which formula?
To increase gm should we increase VGT ? or decrease it? W 2K Is gm linearly dependent on gm = Id L transistor size? dependent on its square root? 2I gm = d or is it independent of transistor VGT size? In fact, which formula should be applied depends on how the transistor is biased and sized. If size and VGT are known, the rst formula applies. If the drain current and size are known, the second one does. If gate voltage and drain current are given and the transistor is accordingly sized, the third formula should be used. gm = VGT
Dinesh Sharma CMOS Mixed Signal Design

K W L

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Which formula?
To increase gm should we increase VGT ? or decrease it? W 2K Is gm linearly dependent on gm = Id L transistor size? dependent on its square root? 2I gm = d or is it independent of transistor VGT size? In fact, which formula should be applied depends on how the transistor is biased and sized. If size and VGT are known, the rst formula applies. If the drain current and size are known, the second one does. If gate voltage and drain current are given and the transistor is accordingly sized, the third formula should be used. gm = VGT
Dinesh Sharma CMOS Mixed Signal Design

K W L

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Which formula?
To increase gm should we increase VGT ? or decrease it? W 2K Is gm linearly dependent on Id gm = L transistor size? dependent on its square root? 2I gm = d or is it independent of transistor VGT size? In fact, which formula should be applied depends on how the transistor is biased and sized. If size and VGT are known, the rst formula applies. If the drain current and size are known, the second one does. If gate voltage and drain current are given and the transistor is accordingly sized, the third formula should be used. gm = VGT
Dinesh Sharma CMOS Mixed Signal Design

K W L

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Which formula?
To increase gm should we increase VGT ? or decrease it? W 2K Is gm linearly dependent on Id gm = L transistor size? dependent on its square root? 2I gm = d or is it independent of transistor VGT size? In fact, which formula should be applied depends on how the transistor is biased and sized. If size and VGT are known, the rst formula applies. If the drain current and size are known, the second one does. If gate voltage and drain current are given and the transistor is accordingly sized, the third formula should be used. gm = VGT
Dinesh Sharma CMOS Mixed Signal Design

K W L

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Output conductance
Assuming a simple Early effect like model, we can write for g o : go Id /L

where L is the channel length and is a technology dependent parameter. In terms of geometry and V GT , we can write: go = K W 2 V 2 L2 GT

The Early Voltage VA is L/ . So, go Id /VA =

Dinesh Sharma

KW 2

VGT VA

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Voltage Gain
The voltage gain in terms of geometry and V GT : Ao = 2L VGT

In terms of drain current and geometry: Ao = 1 2K WL Id

Thus, if the transistor is biased at constant current, the DC gain is determined by the square root of the gate area.

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

AC Behaviour

Cgd G vi Cg S gm vi ro

vo

D Co S

sCgd (vi vo ) gm vi

vo sCo vo = 0 ro 1 + sCo ro =0

vi sCgd gm vo sCgd + So the AC gain A1 =

1 sCgd /gm vo = gm ro vi 1 + sro (cgd + co )

CMOS Mixed Signal Design

Dinesh Sharma

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Bandwidth
A1 = gm ro 1 sCgd /gm 1 + sro (cgd + co ) 1 sCgd /gm 1 + sro Ctot

Let Ctot Cgd + Co Then, A1 = Ao Normally, Cgd /gm << 1 Therefore, A1 Ao 1 + sro Ctot

This describes the frequency response of a system with one dominant pole. The bandwidth is given by 1/r o Ctot .
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Gain Bandwidth Product

Ao A - 3db o

0 db BW Frequency GBW

Gain (db)

GBW = gm ro

1 gm = ro Ctot Ctot

The gain bandwidth product (or the cutoff frequency) is independent of ro .

Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Maximum GBW
GBW is max. when there is no load connected and the load is entirely due to the device capacitance itself. Then the load capacitance is proportional to the device width. Ctot = W where is a technological parameter. gm GBWmax = W GBWmax = = =
Dinesh Sharma

K VGT L 1 2K Id L 2Id WVGT

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Summary

Free Design Variables: Parameters W , L, VGT W , L, Id L, VGT , Id gm go Ao GBW GBW max

K WVGT L 2 K WVGT 2L2 2L VGT K WVGT LCtot K VGT L 2K WId L Id L 2K WL Id 2Id VGT Id L 2L VGT 2Id VGT Ctot K VGT L

2K WId 1 L Ctot 2K Id 1 WL

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Transistor Characteristics DC Voltage Gain AC Behaviour

Technological Constraint

Ao GBWmax =

2L K VGT 1 = VGT L So Ao GBWmax =

2K WL 1 Id 2K

2K Id WL

Therefore, this quantity is a technological constant and the designer has no control over it. What if an application requires a Gain-GBW product higher than this value?

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

Cascode Amplier
I

d V d2 v out M2 V d1 M1

dId = gmeq dVg 1 + goeq dVd 2 So gmeq = and goeq = Id with dVd 2 = 0 Vg 1 Id with dVg 1 = 0 Vd 2

ref

Vg2

Vg1 v in

To calculate gmeq , we put a voltage source at Id the output node and calculate Vg 1 . goeq is calculated by putting a voltage source at Id vg1 and calculating Vd 2 .

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

Equivalent gm of Cascode
gmeq =
I d V d2
V ref

dVds2
v out M2

Id Vg 1 = dVd 1 ,

with dVd 2 = 0 dVgs2 = dVd 1

Vg2

id id

= g m 1 vg 1 + g o 1 vd 1 = gm2 vd 1 go2 vd 1 id = gm 2 + g o 2 go 1 = g m 1 vg 1 i d gm 2 + g o 2 id gm 2 + g o 2 = gm 1 vg 1 go 1 + g o 2 + g m 2
CMOS Mixed Signal Design

Vg1 v in

V d1 M1

So vd 1 id gmeq =
Dinesh Sharma

gm 1

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

Equivalent go of Cascode
goeq = dVgs1 = 0,
I d V d2
V ref

Id Vd 2

with dVg 1 = 0

dVgs2 = dVd 1 , dVds2 = dVd 2 dVd 1 i id = 0 + g o 1 vd 1 , sovd 1 = d go 1

v out

id = gm2 vd 1 + go2 (vd 2 vd 1 ) id = id goeq = gm 2 + g o 2 + g o 2 vd 2 go 1

Vg2

M2 V d1 M1

Vg1 v in

id go 1 go 2 = vd 2 go 1 + g o 2 + g m 2 go 2 goeq go1 gm 2

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

DC gain of Cascode
gmeq gm1 (gm2 + go2 ) g01 + g02 + gm2 = goeq g01 + g02 + gm2 g01 g02

Ao = So

gm 1 gm 2 gm1 (gm2 + go2 ) = 1+ g01 g02 g01 g02 gm 1 common source gain Let A01 g01 gm 2 And A02 1 + common gate gain g02 Ao = Then, Ao = A01 A02

DC gain = the product of the DC gain of the two transistors.

Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

AC Behaviour of Cascode
I

d V d2 v out M2 V d1 M1

ref

Vg2

G S

Cdg1 vx ro1

ro2 vo gm2 vx Co

vi Cg1 gm1 vi

Vg1 v in

We shall see presently that vx is quite small.

Initially, we shall ignore the effect of the drain capacitance of the lower transistor and the gate capacitance of the upper one. If necessary, we can always replace r o1 by ro1 Cds1 Cg 2 .

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

Cdg1 vx ro1

ro2 vo gm2 vx Co

vi Cg1 gm1 vi S
gm 2 vx + vx =

vx v o = sCo vo ro 2

1 + sro2 Co 1 + sro2 Co vo = vo 1 + g m 2 ro 2 A2

Since A2 is quite large, vx is very small compared to vo .

Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

G S

Cdg1 vx ro1

ro2 vo gm2 vx Co

vi Cg1 gm1 vi

vx + sCo vo ro 1 (A1 sro1 Cdg )A2 vo = vi (1 + sro2 Co )(1 + sro1 Cdg ) + A2 sCo ro1 sCdg 1 (vi vx ) = gm1 vx + If sro1 Cdg is small, Voltage gain = vo A1 A2 = vi 1 + sro1 Co (A2 + ro2 /ro1 )

This shows that the DC gain is multiplied by A 2 and the bandwidth is reduced by roughly the same factor.
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

Current Source Loads

Up to now we have assumed current source loads. How do we implement these? A transistor in saturation has a (nearly) constant current in saturation. Therefore single transistors (preferably with long channels) can be used as current sources/sinks. These act as current sources/sinks only over some voltage range not for all voltages. There is a weak dependence on voltage due to nonzero output conductance. This dependence can be reduced by using a cascode stage.
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

A simple Current Mirror

Iref Io
For M1, Vds = Vgs > Vgs VT Therefore M1 is saturated. Iref = K (V VT )2 2 ref

M1

Vref

M2

2Iref K If M2 is also saturated, Io = Iref Therefore Vref = VT +

Thus M2 can act as a current source load if Vo > Vref VT

Dinesh Sharma

i.e.

Vo >

2Iref K

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

Load for a Cascode stage

The output resistance of the load appears in parallel with that of the amplifying stage. If we use a single transistor current load for a cascode, the output resistance of the load will be ro while that of the cascode stage will be A ro . The effective output resistance will thus be dominated by the much lower resistance of the load and we shall lose the advantages of the cascode stage. It is important, therefore, that the load also should be a current source made from a cascode pair.
Dinesh Sharma CMOS Mixed Signal Design

Vbiasp1

Vbiasp2 vout Vbiasn vin

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

A cascode current mirror

Iref Io

Vx M1

A single transistor current mirror will have some dependence on the drain voltage due to its output resistance. Vb M3 This dependence can be reduced substantially by using a cascode stage. Vy Vref However, this reduces the available M2 voltage range over which the transistors are saturated. 2Iref For saturation of M2 Vy Vref VT = K 2Iref Therefore Vb 2 + VT K 2Iref For saturation of M3 Vo 2 K
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

Self biased Cascode current mirror

Iref Io

This circuit does not need an external voltage bias.

M0 Vb Vx M1 Vref Vy M2 M3

The reference side of the mirror generates the bias voltages for both the transistors of the cascode output side.

However, this reduces the voltage range over which the the output may swing. 2Iref Vb = 2 + 2VT K 2Iref For saturation of M3 Vo 2 + VT K

The output voltage needs to be a VT higher than the minimum.

Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

Folded Cascode
Vbiasp1 M3 M2 Load

vin

M1

Vbiasp2 vout

The two transistors forming the cascode pair can be of different channel types. Here M1 (n type) and M2 (p type) form the cascode pair. M3 provides the bias current.

This arrangement is called a folded cascode. rout = (1 + gm2 ro2 )(ro1 ||ro3 ) + ro2 This is lower than the output resistance of the telescopic cascode stage, because of the paralleling of r o1 and ro3 . However, it is much higher than the single transistor output resistance.
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Cascode eq. gm Cascode eq. go DC gain of Cascode AC Behaviour of Cascode Folded Cascode

Practical Folded Cascode

M3 M2

Vbiasp1

Vbiasp2 vout Vbiasn2 Vbiasn1

vin

M1

The load for the folded cascode should also be a cascode pair. Here two n channel transistors in cascode conguration are used as the load.

One major advantage of the folded cascode is that the output can be directly coupled to the input for negative feedback.

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Why diffamps? Difference amplier

Why diffamps?

Circuits which amplify the difference of two input voltages (each of which has equal and opposite signal excursions) have many advantages over single ended ampliers. Noise picked up by both inputs gets canceled in the output. Input and feedback paths can be isolated. If both inputs have the same DC bias, the output is insensitive to changes in the bias.

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Why diffamps? Difference amplier

Some denitions
It is more convenient to represent the two input voltages and the two output voltages by their mean and difference values. vi 1 vi 2 vi 1 + v i 2 vicm 2 vod vo1 vo2 vo 1 + v o 2 vocm 2 The common mode and differential gains are: vod Adiff vid vocm Acm vicm vid
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Why diffamps? Difference amplier

Common Mode Rejection Ratio

For a good diff amp, the differential gain should be high and independent of input common mode voltage, whereas the common mode gain should be as low as possible. The common mode rejection ratio is: CMRR 20 log Adiff dB Acm

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Why diffamps? Difference amplier

Will this do?

Vdd vo 1 vo 2 vi 1 vi 2

One (not very good) way of implementing a diff amp is to use two single ended ampliers as shown above. Output = Vo1 Vo2 Here the transistor currents, and hence the differential gain, will depend on the common mode voltage. This is not desirable as we would like the circuit to ignore the common mode voltage and to amplify just the difference signal. Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Why diffamps? Difference amplier

The long tail pair

A better diff amp can be implemented by adding a current source to keep the total current constant.
Vdd vo 1 vo 2 vi 1 vi 2

Vs
Is

If the common mode voltage appearing at the two inputs changes, it will only change the voltage at the node where the two sources join (Vs ). However, the current remains unchanged due to the current source - and therefore, the differential gain is unaffected by the common mode voltage.

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Why diffamps? Difference amplier

Diff amp with single ended output

Vdd

iout = I (Mp 2) I (Mn2) I (Mp 2) = I (Mp 1) (current mirror) I (Mp 1) = I (Mn1) (series connection)

Mp1
vi 1

Mp2
i out

Mn1

Mn2 Vs
Is

vi 2

iout = I (Mn1) I (Mn2) = gm (vi1 vi2 )

iout Gm (vi1 vi2 ) = Gm vid Thus we have a single output which is proportional to the difference of inputs. The effective Gm is just the gm of either of the diff-pair transistors.
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Why diffamps? Difference amplier

Gain of the OTA

Vdd

Mp1
vi 1

Mp2
i out

Mn1

Mn2 Vs
Is

vi 2

This circuit is also called an operational transconductance amplier (OTA) because the output is a current. Rout = ro (Mn2) ro (Mp 2) So DC voltage gain = gm (ro (Mn2) ro (Mp 2)) gm and GBW = CL CL includes Cdg and Cd for Mn2 and Mp2, as well as the load capacitance.
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Two stage op-amp

Vdd

Mp1
vi 1

Mp2
i out

Mp3

Mn1

Mn2 Vs
Mn4

vi 2

vout

Vbias

Mn3

A simple two stage op-amp can be constructed by following the diff amp by a common source stage with a constant current load. The current source for the diff amp is implemented by an n channel MOS transistor in saturation.

The two stage design permits us to optimize the output stage for driving the load and the input stage for providing good differential gain and CMRR. A diff amp with n transistors and an output stage with p driver is shown. However, a ptype diff amp with n type common source stage is better for low noise operation.
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

op-amp eq. circuit

Differential Stage gm11 v1 v2 gm22 v2 Output Stage v0

R1

C1

R2

C2

Each stage of the opamp can be considered a gain stage with a single pole frequency response. Notice that the phase of the output of each stage will undergo a phase change of 90o around its pole frequency.

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

op-amp Compensation
Most opamps are used with negative feedback. If the opamp stages themselves contribute a phase difference of 180o , the negative feedback will appear as positive feedback. If the gain at this frequency is > 1, the circuit will become unstable. Both stages of the opamp have a single pole frequency response. The poles for both the stages can be quite close together. As a result, they can contribute a total of 180 o phase shift over a relatively narrow frequency range.

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Pole Splitting
To avoid instability, we would like to arrange things such that the gain drops to below one by the time the phase shift through the opamp becomes 180o . - Even if it means that we have to reduce the bandwidth of the op amp. This is often achieved by a technique called pole splitting. The lower frequency pole is brought to a low enough frequency, so that the gain diminishes to below one by the time the second pole is reached. One way of doing this is to use a Miller capacitor.

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Eq. Circuit of compensated Opamp

Differential Stage v2

Cc

Output Stage v0

R1 gm11 v1

C1 gm22 v2

R2

C2

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Miller Compensation
C

A1

A2

The diff amp stage sees a load capacitance A 2 C . 1 . This brings its pole to ro1 A 2C The total DC gain is A1 A2 . The bandwidth is set by the diff amp stage. Therefore the gain-bandwidth product is: A1 A1 A2 = ro 1 A2 C ro 1C
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Slew rate
Miller compensation also sets the slew rate of the op amp. For large signal input, the output current of the Vdd Mp3 Mp1 Mp2 OTA = tail current. i out vout The effective load capacitance for this stage is vi 1 Mn1 Mn2 vi 2 Vs A2 C . dV Mn3 Vbias Mn4 = I (Mn4) A2 C dt (Mn4) . Output of the OTA slews at a rate IA 2 C So the op amp slews at a rate which is A 2 times this value. 4) Hence the slew rate of the op amp is I (Mn C .

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Design Equations-I
All transistors must be saturated
Vdd

Mp1
vi 1

Mp2
i out

Mp3

Mn1

Mn2 Vs
Mn4

vi 2

vout

I (Mn1) = I (Mn2) = I (Mn1) = I (Mp 1)

Vbias

Mn3

I (Mn4) 2 (Series connection)

I (Mp 1) = I (MP 2) (Mirror) Mp1 is always saturated. Mp1, Mp2 have the same Vs , Vg , Id Since W/L(Mp2) = W/L(Mp1), MP2 will have the same V d as Mp1, and so, will be saturated.

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Design Equations-II
Vdd

Mp3 has the same Vs , Vg as Mp1.

Mp3 vout

Mp1
vi 1

Mp2
i out

Mn1

Mn2 Vs
Mn4

vi 2

If

W /L(Mp 3) I (Mp 3) = I (Mp 1) W /L(Mp 1)

Vbias

Mn3

Mp3 will have the same Vd as Mp1 and will be saturated.

The slew rate determines I(Mn4). I (Mn4) = C Slew Rate I (Mn4) I (Mn1) = I (Mn2) = 2
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Design Equations-III
Vdd

Mp1
vi 1

Mp2
i out

Mp3

GBW determines gm of Mn1, Mn2. GBW = gm (Mn2) C

Mn1

Mn2 Vs
Mn4

vi 2

vout

Vbias

Mn3

Since the current as well as gm of Mn1 and Mn2 are now known gm (Mn2) = 2K W /L(Mn2)I (Mn2)

W /L(Mn1) = W /L(Mn2) This will detrmine the geometries of Mn1 and Mn2.

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Design Equations-IV
Currents through Mn2,Mp2, Mp3 and Mn3 are known

(go = Id /VA )

where VA is the Early voltage = L/

The overall DC gain is given by A= gm (Mn2)gm (Mp 3) (go (Mn2)||go (Mp 2))(go (Mp 3)||go (Mn3))

As gm for Mn2 and all go values are known, this determines the gm for MP3. Once we know the gm as well as the current for Mp3, we can calculate its geometry.
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Example Design: Specications

K (n) = 120A/V2, K (p ) = 60A/V2 VT (n) = 0.4V, VT (p ) = 0.4V Early Voltage VA = 20V Op amp DC gain for both p and n channel transistors = 80dB (Voltage gain of 10000)

Gain Bandwidth product = 50MHz , slew rate = 20V /s

Dinesh Sharma

CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Example Design-1
Vdd

Mp1
vi 1

Mp2
i out

Mp3

Mn1

Mn2 Vs
Mn4

vi 2

vout

Vbias

Mn3

We choose a compensation capacitor value of 2 pF. We shall bias the second stage at 5 times the tail current of the differential stage. From the slew rate, I(Mn4) = 2 1012
20 106

= 40A

Therefore I(Mn1) = I(Mn2) = I(Mp1) = I(Mp2) = 20A and I(Mp3) = I(Mn3) = = 200A
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Example Design-2
Vdd

Mp1
vi 1

Mp2
i out

Mp3

Mn1

Mn2 Vs
Mn4

vi 2

vout

Vbias

Mn3

From the GBW requirement, 2 50 106 = gm (Mn2) 2 1012

This gives gm (Mn2) 628 . To get a gm of 628 with a current of 20A, 628 106 = 2 120 106 (W /L) 20 106

this gives W/L(Mn2) 82 = W/L(Mn1)

Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Example Design-3
Vdd

Mp1
vi 1

Mp2
i out

Mp3

Mn1

Mn2 Vs
Mn4

vi 2

vout

Vbias

Mn3

go of Mn2 and Mp2 = 20A/20V = 1 . Therefore go (Mn2) go (Mp2) = 2 . go of Mn3 and Mp3 is = 200A/20V = 10 . Therefore go (Mp3) go (Mn3) = 20 . DC gain = 10000 = 628 gm(Mp 3) 2 20 So, gm (Mp 3) 637
CMOS Mixed Signal Design

Dinesh Sharma

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Example Design-4
Vdd

Mp1
vi 1

Mp2
i out

Mp3

Mn1

Mn2 Vs
Mn4

vi 2

vout

Vbias

Mn3

To get a gm of 637 with a drain current of 200A, we should have 637 106 = 2 60 106 (W /L) 200 106

which gives the W/L of Mp3 17. Since the geometry of Mp1 and Mp2 has to be in the current ratio with Mp3, W/L of Mp1 and Mp2 should be 1.7.
Dinesh Sharma CMOS Mixed Signal Design

Introduction Single Transistor Amplier Cascode Amplier Differential Ampliers The two stage op-amp

Compensation Slew Rate Design equations for the op amp

Example Design-5

Vdd

Mp1
vi 1

Mp2
i out

Mp3

Mn1

Mn2 Vs
Mn4

vi 2

vout

Vbias

Mn3

Finally, we assume that an n type reference bias transistor of W/L = 4 is available with a current of 10 A. This will give the W/L of Mn4 and Mn3 as 16 and 80 respectively. This completes the design for the simple op amp.

Dinesh Sharma

CMOS Mixed Signal Design